1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
11 #include "xusb-padctl-common.h"
13 #include <asm/arch/clock.h>
15 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
17 if (phy && phy->ops && phy->ops->prepare)
18 return phy->ops->prepare(phy);
20 return phy ? -ENOSYS : -EINVAL;
23 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
25 if (phy && phy->ops && phy->ops->enable)
26 return phy->ops->enable(phy);
28 return phy ? -ENOSYS : -EINVAL;
31 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
33 if (phy && phy->ops && phy->ops->disable)
34 return phy->ops->disable(phy);
36 return phy ? -ENOSYS : -EINVAL;
39 int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
41 if (phy && phy->ops && phy->ops->unprepare)
42 return phy->ops->unprepare(phy);
44 return phy ? -ENOSYS : -EINVAL;
47 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
49 struct tegra_xusb_phy *phy;
52 for (i = 0; i < padctl.socdata->num_phys; i++) {
53 phy = &padctl.socdata->phys[i];
54 if (phy->type != type)
62 static const struct tegra_xusb_padctl_lane *
63 tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
67 for (i = 0; i < padctl->socdata->num_lanes; i++)
68 if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
69 return &padctl->socdata->lanes[i];
75 tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
76 struct tegra_xusb_padctl_group *group,
82 group->name = ofnode_get_name(node);
84 len = ofnode_read_string_count(node, "nvidia,lanes");
86 pr_err("failed to parse \"nvidia,lanes\" property");
90 group->num_pins = len;
92 for (i = 0; i < group->num_pins; i++) {
93 ret = ofnode_read_string_index(node, "nvidia,lanes", i,
96 pr_err("failed to read string from \"nvidia,lanes\" property");
101 group->num_pins = len;
103 ret = ofnode_read_string_index(node, "nvidia,function", 0,
106 pr_err("failed to parse \"nvidia,func\" property");
110 group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);
115 static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
120 for (i = 0; i < padctl->socdata->num_functions; i++)
121 if (strcmp(name, padctl->socdata->functions[i]) == 0)
128 tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
129 const struct tegra_xusb_padctl_lane *lane,
135 func = tegra_xusb_padctl_find_function(padctl, name);
139 for (i = 0; i < lane->num_funcs; i++)
140 if (lane->funcs[i] == func)
147 tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
148 const struct tegra_xusb_padctl_group *group)
152 for (i = 0; i < group->num_pins; i++) {
153 const struct tegra_xusb_padctl_lane *lane;
157 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
159 pr_err("no lane for pin %s", group->pins[i]);
163 func = tegra_xusb_padctl_lane_find_function(padctl, lane,
166 pr_err("function %s invalid for lane %s: %d",
167 group->func, lane->name, func);
171 value = padctl_readl(padctl, lane->offset);
173 /* set pin function */
174 value &= ~(lane->mask << lane->shift);
175 value |= func << lane->shift;
178 * Set IDDQ if supported on the lane and specified in the
181 if (lane->iddq > 0 && group->iddq >= 0) {
182 if (group->iddq != 0)
183 value &= ~(1 << lane->iddq);
185 value |= 1 << lane->iddq;
188 padctl_writel(padctl, value, lane->offset);
195 tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
196 struct tegra_xusb_padctl_config *config)
200 for (i = 0; i < config->num_groups; i++) {
201 const struct tegra_xusb_padctl_group *group;
204 group = &config->groups[i];
206 err = tegra_xusb_padctl_group_apply(padctl, group);
208 pr_err("failed to apply group %s: %d",
218 tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
219 struct tegra_xusb_padctl_config *config,
224 config->name = ofnode_get_name(node);
226 ofnode_for_each_subnode(subnode, node) {
227 struct tegra_xusb_padctl_group *group;
230 group = &config->groups[config->num_groups];
232 err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
234 pr_err("failed to parse group %s", group->name);
238 config->num_groups++;
244 static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
250 err = ofnode_read_resource(node, 0, &padctl->regs);
252 pr_err("registers not found");
256 ofnode_for_each_subnode(subnode, node) {
257 struct tegra_xusb_padctl_config *config = &padctl->config;
259 debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
260 err = tegra_xusb_padctl_config_parse_dt(padctl, config,
263 pr_err("failed to parse entry %s: %d",
268 debug("%s: done\n", __func__);
273 struct tegra_xusb_padctl padctl;
275 int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
276 const struct tegra_xusb_padctl_soc *socdata)
281 debug("%s: count=%d\n", __func__, count);
282 for (i = 0; i < count; i++) {
283 debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
284 if (!ofnode_is_available(nodes[i]))
287 padctl.socdata = socdata;
289 err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
291 pr_err("failed to parse DT: %d", err);
295 /* deassert XUSB padctl reset */
296 reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
298 err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
300 pr_err("failed to apply pinmux: %d", err);
304 /* only a single instance is supported */
307 debug("%s: done\n", __func__);