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   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * MCF547x_8x Internal Memory Map
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  */
   8
   9 #ifndef __IMMAP_547x_8x__
  10 #define __IMMAP_547x_8x__
  11
  12 #define MMAP_SIU        (CONFIG_SYS_MBAR + 0x00000000)
  13 #define MMAP_SDRAM      (CONFIG_SYS_MBAR + 0x00000100)
  14 #define MMAP_XARB       (CONFIG_SYS_MBAR + 0x00000240)
  15 #define MMAP_FBCS       (CONFIG_SYS_MBAR + 0x00000500)
  16 #define MMAP_INTC0      (CONFIG_SYS_MBAR + 0x00000700)
  17 #define MMAP_GPTMR      (CONFIG_SYS_MBAR + 0x00000800)
  18 #define MMAP_SLT0       (CONFIG_SYS_MBAR + 0x00000900)
  19 #define MMAP_SLT1       (CONFIG_SYS_MBAR + 0x00000910)
  20 #define MMAP_GPIO       (CONFIG_SYS_MBAR + 0x00000A00)
  21 #define MMAP_PCI        (CONFIG_SYS_MBAR + 0x00000B00)
  22 #define MMAP_PCIARB     (CONFIG_SYS_MBAR + 0x00000C00)
  23 #define MMAP_EXTDMA     (CONFIG_SYS_MBAR + 0x00000D00)
  24 #define MMAP_EPORT      (CONFIG_SYS_MBAR + 0x00000F00)
  25 #define MMAP_CTM        (CONFIG_SYS_MBAR + 0x00007F00)
  26 #define MMAP_MCDMA      (CONFIG_SYS_MBAR + 0x00008000)
  27 #define MMAP_SCPCI      (CONFIG_SYS_MBAR + 0x00008400)
  28 #define MMAP_UART0      (CONFIG_SYS_MBAR + 0x00008600)
  29 #define MMAP_UART1      (CONFIG_SYS_MBAR + 0x00008700)
  30 #define MMAP_UART2      (CONFIG_SYS_MBAR + 0x00008800)
  31 #define MMAP_UART3      (CONFIG_SYS_MBAR + 0x00008900)
  32 #define MMAP_DSPI       (CONFIG_SYS_MBAR + 0x00008A00)
  33 #define MMAP_I2C        (CONFIG_SYS_MBAR + 0x00008F00)
  34 #define MMAP_FEC0       (CONFIG_SYS_MBAR + 0x00009000)
  35 #define MMAP_FEC1       (CONFIG_SYS_MBAR + 0x00009800)
  36 #define MMAP_CAN0       (CONFIG_SYS_MBAR + 0x0000A000)
  37 #define MMAP_CAN1       (CONFIG_SYS_MBAR + 0x0000A800)
  38 #define MMAP_USBD       (CONFIG_SYS_MBAR + 0x0000B000)
  39 #define MMAP_SRAM       (CONFIG_SYS_MBAR + 0x00010000)
  40 #define MMAP_SRAMCFG    (CONFIG_SYS_MBAR + 0x0001FF00)
  41 #define MMAP_SEC        (CONFIG_SYS_MBAR + 0x00020000)
  42
  43 #include <asm/coldfire/dspi.h>
  44 #include <asm/coldfire/eport.h>
  45 #include <asm/coldfire/flexbus.h>
  46 #include <asm/coldfire/flexcan.h>
  47 #include <asm/coldfire/intctrl.h>
  48
  49 typedef struct siu {
  50         u32 mbar;               /* 0x00 */
  51         u32 drv;                /* 0x04 */
  52         u32 rsvd1[2];           /* 0x08 - 0x1F */
  53         u32 sbcr;               /* 0x10 */
  54         u32 rsvd2[3];           /* 0x14 - 0x1F */
  55         u32 cs0cfg;             /* 0x20 */
  56         u32 cs1cfg;             /* 0x24 */
  57         u32 cs2cfg;             /* 0x28 */
  58         u32 cs3cfg;             /* 0x2C */
  59         u32 rsvd3[2];           /* 0x30 - 0x37 */
  60         u32 secsacr;            /* 0x38 */
  61         u32 rsvd4[2];           /* 0x3C - 0x43 */
  62         u32 rsr;                /* 0x44 */
  63         u32 rsvd5[2];           /* 0x48 - 0x4F */
  64         u32 jtagid;             /* 0x50 */
  65 } siu_t;
  66
  67 typedef struct sdram {
  68         u32 mode;               /* 0x00 */
  69         u32 ctrl;               /* 0x04 */
  70         u32 cfg1;               /* 0x08 */
  71         u32 cfg2;               /* 0x0c */
  72 } sdram_t;
  73
  74 typedef struct xlb_arb {
  75         u32 cfg;                /* 0x240 */
  76         u32 ver;                /* 0x244 */
  77         u32 sr;                 /* 0x248 */
  78         u32 imr;                /* 0x24c */
  79         u32 adrcap;             /* 0x250 */
  80         u32 sigcap;             /* 0x254 */
  81         u32 adrto;              /* 0x258 */
  82         u32 datto;              /* 0x25c */
  83         u32 busto;              /* 0x260 */
  84         u32 prien;              /* 0x264 */
  85         u32 pri;                /* 0x268 */
  86 } xlbarb_t;
  87
  88 typedef struct gptmr {
  89         u8 ocpw;
  90         u8 octict;
  91         u8 ctrl;
  92         u8 mode;
  93
  94         u16 pre;                /* Prescale */
  95         u16 cnt;
  96
  97         u16 pwmwidth;
  98         u8 pwmop;               /* Output Polarity */
  99         u8 pwmld;               /* Immediate Update */
 100
 101         u16 cap;                /* Capture internal counter */
 102         u8 ovfpin;              /* Ovf and Pin */
 103         u8 intr;                /* Interrupts */
 104 } gptmr_t;
 105
 106 typedef struct canex_ctrl {
 107         can_msg_t msg[16];      /* 0x00 Message Buffer 0-15 */
 108 } canex_t;
 109
 110
 111 typedef struct slt {
 112         u32 tcnt;               /* 0x00 */
 113         u32 cr;                 /* 0x04 */
 114         u32 cnt;                /* 0x08 */
 115         u32 sr;                 /* 0x0C */
 116 } slt_t;
 117
 118 typedef struct gpio {
 119         /* Port Output Data Registers */
 120         u8 podr_fbctl;          /*0x00 */
 121         u8 podr_fbcs;           /*0x01 */
 122         u8 podr_dma;            /*0x02 */
 123         u8 rsvd1;               /*0x03 */
 124         u8 podr_fec0h;          /*0x04 */
 125         u8 podr_fec0l;          /*0x05 */
 126         u8 podr_fec1h;          /*0x06 */
 127         u8 podr_fec1l;          /*0x07 */
 128         u8 podr_feci2c;         /*0x08 */
 129         u8 podr_pcibg;          /*0x09 */
 130         u8 podr_pcibr;          /*0x0A */
 131         u8 rsvd2;               /*0x0B */
 132         u8 podr_psc3psc2;       /*0x0C */
 133         u8 podr_psc1psc0;       /*0x0D */
 134         u8 podr_dspi;           /*0x0E */
 135         u8 rsvd3;               /*0x0F */
 136
 137         /* Port Data Direction Registers */
 138         u8 pddr_fbctl;          /*0x10 */
 139         u8 pddr_fbcs;           /*0x11 */
 140         u8 pddr_dma;            /*0x12 */
 141         u8 rsvd4;               /*0x13 */
 142         u8 pddr_fec0h;          /*0x14 */
 143         u8 pddr_fec0l;          /*0x15 */
 144         u8 pddr_fec1h;          /*0x16 */
 145         u8 pddr_fec1l;          /*0x17 */
 146         u8 pddr_feci2c;         /*0x18 */
 147         u8 pddr_pcibg;          /*0x19 */
 148         u8 pddr_pcibr;          /*0x1A */
 149         u8 rsvd5;               /*0x1B */
 150         u8 pddr_psc3psc2;       /*0x1C */
 151         u8 pddr_psc1psc0;       /*0x1D */
 152         u8 pddr_dspi;           /*0x1E */
 153         u8 rsvd6;               /*0x1F */
 154
 155         /* Port Pin Data/Set Data Registers */
 156         u8 ppdsdr_fbctl;        /*0x20 */
 157         u8 ppdsdr_fbcs;         /*0x21 */
 158         u8 ppdsdr_dma;          /*0x22 */
 159         u8 rsvd7;               /*0x23 */
 160         u8 ppdsdr_fec0h;        /*0x24 */
 161         u8 ppdsdr_fec0l;        /*0x25 */
 162         u8 ppdsdr_fec1h;        /*0x26 */
 163         u8 ppdsdr_fec1l;        /*0x27 */
 164         u8 ppdsdr_feci2c;       /*0x28 */
 165         u8 ppdsdr_pcibg;        /*0x29 */
 166         u8 ppdsdr_pcibr;        /*0x2A */
 167         u8 rsvd8;               /*0x2B */
 168         u8 ppdsdr_psc3psc2;     /*0x2C */
 169         u8 ppdsdr_psc1psc0;     /*0x2D */
 170         u8 ppdsdr_dspi;         /*0x2E */
 171         u8 rsvd9;               /*0x2F */
 172
 173         /* Port Clear Output Data Registers */
 174         u8 pclrr_fbctl;         /*0x30 */
 175         u8 pclrr_fbcs;          /*0x31 */
 176         u8 pclrr_dma;           /*0x32 */
 177         u8 rsvd10;              /*0x33 */
 178         u8 pclrr_fec0h;         /*0x34 */
 179         u8 pclrr_fec0l;         /*0x35 */
 180         u8 pclrr_fec1h;         /*0x36 */
 181         u8 pclrr_fec1l;         /*0x37 */
 182         u8 pclrr_feci2c;        /*0x38 */
 183         u8 pclrr_pcibg;         /*0x39 */
 184         u8 pclrr_pcibr;         /*0x3A */
 185         u8 rsvd11;              /*0x3B */
 186         u8 pclrr_psc3psc2;      /*0x3C */
 187         u8 pclrr_psc1psc0;      /*0x3D */
 188         u8 pclrr_dspi;          /*0x3E */
 189         u8 rsvd12;              /*0x3F */
 190
 191         /* Pin Assignment Registers */
 192         u16 par_fbctl;          /*0x40 */
 193         u8 par_fbcs;            /*0x42 */
 194         u8 par_dma;             /*0x43 */
 195         u16 par_feci2cirq;      /*0x44 */
 196         u16 rsvd13;             /*0x46 */
 197         u16 par_pcibg;          /*0x48 */
 198         u16 par_pcibr;          /*0x4A */
 199         u8 par_psc3;            /*0x4C */
 200         u8 par_psc2;            /*0x4D */
 201         u8 par_psc1;            /*0x4E */
 202         u8 par_psc0;            /*0x4F */
 203         u16 par_dspi;           /*0x50 */
 204         u8 par_timer;           /*0x52 */
 205         u8 rsvd14;              /*0x53 */
 206 } gpio_t;
 207
 208 typedef struct pci {
 209         u32 idr;                /* 0x00 Device Id / Vendor Id */
 210         u32 scr;                /* 0x04 Status / command */
 211         u32 ccrir;              /* 0x08 Class Code / Revision Id */
 212         u32 cr1;                /* 0x0c Configuration 1 */
 213         u32 bar0;               /* 0x10 Base address register 0 */
 214         u32 bar1;               /* 0x14 Base address register 1 */
 215         u32 bar2;               /* 0x18 NA */
 216         u32 bar3;               /* 0x1c NA */
 217         u32 bar4;               /* 0x20 NA */
 218         u32 bar5;               /* 0x24 NA */
 219         u32 ccpr;               /* 0x28 Cardbus CIS Pointer */
 220         u32 sid;                /* 0x2c Subsystem ID / Subsystem Vendor ID */
 221         u32 erbar;              /* 0x30 Expansion ROM Base Address */
 222         u32 cpr;                /* 0x34 Capabilities Pointer */
 223         u32 rsvd1;              /* 0x38 */
 224         u32 cr2;                /* 0x3c Configuration 2 */
 225         u32 rsvd2[8];           /* 0x40 - 0x5f */
 226
 227         /* General control / status registers */
 228         u32 gscr;               /* 0x60 Global Status / Control */
 229         u32 tbatr0a;            /* 0x64 Target Base Adr Translation 0 */
 230         u32 tbatr1a;            /* 0x68 Target Base Adr Translation 1 */
 231         u32 tcr1;               /* 0x6c Target Control 1 Register */
 232         u32 iw0btar;            /* 0x70 Initiator Win 0 Base/Translation adr */
 233         u32 iw1btar;            /* 0x74 Initiator Win 1 Base/Translation adr */
 234         u32 iw2btar;            /* 0x78 NA */
 235         u32 rsvd3;              /* 0x7c */
 236         u32 iwcr;               /* 0x80 Initiator Window Configuration */
 237         u32 icr;                /* 0x84 Initiator Control */
 238         u32 isr;                /* 0x88 Initiator Status */
 239         u32 tcr2;               /* 0x8c NA */
 240         u32 tbatr0;             /* 0x90 NA */
 241         u32 tbatr1;             /* 0x94 NA */
 242         u32 tbatr2;             /* 0x98 NA */
 243         u32 tbatr3;             /* 0x9c NA */
 244         u32 tbatr4;             /* 0xa0 NA */
 245         u32 tbatr5;             /* 0xa4 NA */
 246         u32 intr;               /* 0xa8 NA */
 247         u32 rsvd4[19];          /* 0xac - 0xf7 */
 248         u32 car;                /* 0xf8 Configuration Address */
 249 } pci_t;
 250
 251 typedef struct pci_arbiter {
 252         /* Pci Arbiter Registers */
 253         union {
 254                 u32 acr;        /* Arbiter Control */
 255                 u32 asr;        /* Arbiter Status */
 256         };
 257 } pciarb_t;
 258 #endif                          /* __IMMAP_547x_8x__ */