1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011 The Chromium OS Authors.
6 #ifndef __MICROBLAZE_CACHE_H__
7 #define __MICROBLAZE_CACHE_H__
10 * The microblaze can have either a 4 or 16 byte cacheline depending on whether
11 * you are using OPB(4) or CacheLink(16). If the board config has not specified
12 * a cacheline size we assume the larger value of 16 bytes for DMA buffer
15 #ifdef CONFIG_SYS_CACHELINE_SIZE
16 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
18 #define ARCH_DMA_MINALIGN 16
21 #endif /* __MICROBLAZE_CACHE_H__ */