git.sur5r.net Git - u-boot/blob - arch/powerpc/cpu/mpc8xx/i2c.c

   1 /*
   2  * (C) Copyright 2000
   3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
   4  *
   5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  *
  26  * Back ported to the 8xx platform (from the 8260 platform) by
  27  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  28  */
  29
  30 #include <common.h>
  31
  32 #ifdef CONFIG_HARD_I2C
  33
  34 #include <commproc.h>
  35 #include <i2c.h>
  36 #ifdef CONFIG_LWMON
  37 #include <watchdog.h>
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
  43 #define TOUT_LOOP 1000000
  44
  45 #define NUM_RX_BDS 4
  46 #define NUM_TX_BDS 4
  47 #define MAX_TX_SPACE 256
  48 #define I2C_RXTX_LEN 128        /* maximum tx/rx buffer length */
  49
  50 typedef struct I2C_BD {
  51         unsigned short status;
  52         unsigned short length;
  53         unsigned char *addr;
  54 } I2C_BD;
  55
  56 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
  57
  58 #define BD_I2C_TX_CL    0x0001  /* collision error */
  59 #define BD_I2C_TX_UN    0x0002  /* underflow error */
  60 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
  61 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
  62
  63 #define BD_I2C_RX_ERR   BD_SC_OV
  64
  65 typedef void (*i2c_ecb_t) (int, int);   /* error callback function */
  66
  67 /* This structure keeps track of the bd and buffer space usage. */
  68 typedef struct i2c_state {
  69         int rx_idx;             /* index   to next free Rx BD */
  70         int tx_idx;             /* index   to next free Tx BD */
  71         void *rxbd;             /* pointer to next free Rx BD */
  72         void *txbd;             /* pointer to next free Tx BD */
  73         int tx_space;           /* number  of Tx bytes left   */
  74         unsigned char *tx_buf;  /* pointer to free Tx area    */
  75         i2c_ecb_t err_cb;       /* error callback function    */
  76 } i2c_state_t;
  77
  78
  79 /* flags for i2c_send() and i2c_receive() */
  80 #define I2CF_ENABLE_SECONDARY   0x01  /* secondary_address is valid           */
  81 #define I2CF_START_COND         0x02  /* tx: generate start condition         */
  82 #define I2CF_STOP_COND          0x04  /* tx: generate stop  condition         */
  83
  84 /* return codes */
  85 #define I2CERR_NO_BUFFERS       0x01  /* no more BDs or buffer space          */
  86 #define I2CERR_MSG_TOO_LONG     0x02  /* tried to send/receive to much data   */
  87 #define I2CERR_TIMEOUT          0x03  /* timeout in i2c_doio()                */
  88 #define I2CERR_QUEUE_EMPTY      0x04  /* i2c_doio called without send/receive */
  89
  90 /* error callback flags */
  91 #define I2CECB_RX_ERR           0x10  /* this is a receive error              */
  92 #define     I2CECB_RX_ERR_OV    0x02  /* receive overrun error                */
  93 #define     I2CECB_RX_MASK      0x0f  /* mask for error bits                  */
  94 #define I2CECB_TX_ERR           0x20  /* this is a transmit error             */
  95 #define     I2CECB_TX_CL        0x01  /* transmit collision error             */
  96 #define     I2CECB_TX_UN        0x02  /* transmit underflow error             */
  97 #define     I2CECB_TX_NAK       0x04  /* transmit no ack error                */
  98 #define     I2CECB_TX_MASK      0x0f  /* mask for error bits                  */
  99 #define I2CECB_TIMEOUT          0x40  /* this is a timeout error              */
 100
 101 /*
 102  * Returns the best value of I2BRG to meet desired clock speed of I2C with
 103  * input parameters (clock speed, filter, and predivider value).
 104  * It returns computer speed value and the difference between it and desired
 105  * speed.
 106  */
 107 static inline int
 108 i2c_roundrate(int hz, int speed, int filter, int modval,
 109               int *brgval, int *totspeed)
 110 {
 111         int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
 112
 113         debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
 114                 hz, speed, filter, modval);
 115
 116         div = moddiv * speed;
 117         brgdiv = (hz + div - 1) / div;
 118
 119         debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
 120
 121         *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
 122
 123         if ((*brgval < 0) || (*brgval > 255)) {
 124                 debug("\t\trejected brgval=%d\n", *brgval);
 125                 return -1;
 126         }
 127
 128         brgdiv = 2 * (*brgval + 3 + (2 * filter));
 129         div = moddiv * brgdiv;
 130         *totspeed = hz / div;
 131
 132         debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
 133
 134         return 0;
 135 }
 136
 137 /*
 138  * Sets the I2C clock predivider and divider to meet required clock speed.
 139  */
 140 static int i2c_setrate(int hz, int speed)
 141 {
 142         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 143         volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
 144         int     brgval,
 145                 modval, /* 0-3 */
 146                 bestspeed_diff = speed,
 147                 bestspeed_brgval = 0,
 148                 bestspeed_modval = 0,
 149                 bestspeed_filter = 0,
 150                 totspeed,
 151                 filter = 0;     /* Use this fixed value */
 152
 153         for (modval = 0; modval < 4; modval++) {
 154                 if (i2c_roundrate
 155                     (hz, speed, filter, modval, &brgval, &totspeed) == 0) {
 156                         int diff = speed - totspeed;
 157
 158                         if ((diff >= 0) && (diff < bestspeed_diff)) {
 159                                 bestspeed_diff = diff;
 160                                 bestspeed_modval = modval;
 161                                 bestspeed_brgval = brgval;
 162                                 bestspeed_filter = filter;
 163                         }
 164                 }
 165         }
 166
 167         debug("[I2C] Best is:\n");
 168         debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
 169                 hz,
 170                 speed,
 171                 bestspeed_filter,
 172                 bestspeed_modval,
 173                 bestspeed_brgval,
 174                 bestspeed_diff);
 175
 176         i2c->i2c_i2mod |=
 177                 ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
 178         i2c->i2c_i2brg = bestspeed_brgval & 0xff;
 179
 180         debug("[I2C] i2mod=%08x i2brg=%08x\n",
 181                 i2c->i2c_i2mod,
 182                 i2c->i2c_i2brg);
 183
 184         return 1;
 185 }
 186
 187 void i2c_init(int speed, int slaveaddr)
 188 {
 189         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 190         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 191         volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
 192         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 193         ulong rbase, tbase;
 194         volatile I2C_BD *rxbd, *txbd;
 195         uint dpaddr;
 196
 197 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 198         /* call board specific i2c bus reset routine before accessing the   */
 199         /* environment, which might be in a chip on that bus. For details   */
 200         /* about this problem see doc/I2C_Edge_Conditions.                  */
 201         i2c_init_board();
 202 #endif
 203
 204 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 205         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 206 #else
 207         /* Disable relocation */
 208         iip->iic_rpbase = 0;
 209 #endif
 210
 211 #ifdef CONFIG_SYS_ALLOC_DPRAM
 212         dpaddr = iip->iic_rbase;
 213         if (dpaddr == 0) {
 214                 /* need to allocate dual port ram */
 215                 dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) +
 216                                            (NUM_TX_BDS * sizeof(I2C_BD)) +
 217                                            MAX_TX_SPACE, 8);
 218         }
 219 #else
 220         dpaddr = CPM_I2C_BASE;
 221 #endif
 222
 223         /*
 224          * initialise data in dual port ram:
 225          *
 226          * dpaddr->rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 227          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 228          *                  tx buffer     (MAX_TX_SPACE bytes)
 229          */
 230
 231         rbase = dpaddr;
 232         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
 233
 234         /* Initialize Port B I2C pins. */
 235         cp->cp_pbpar |= 0x00000030;
 236         cp->cp_pbdir |= 0x00000030;
 237         cp->cp_pbodr |= 0x00000030;
 238
 239         /* Disable interrupts */
 240         i2c->i2c_i2mod = 0x00;
 241         i2c->i2c_i2cmr = 0x00;
 242         i2c->i2c_i2cer = 0xff;
 243         i2c->i2c_i2add = slaveaddr;
 244
 245         /*
 246          * Set the I2C BRG Clock division factor from desired i2c rate
 247          * and current CPU rate (we assume sccr dfbgr field is 0;
 248          * divide BRGCLK by 1)
 249          */
 250         debug("[I2C] Setting rate...\n");
 251         i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED);
 252
 253         /* Set I2C controller in master mode */
 254         i2c->i2c_i2com = 0x01;
 255
 256         /* Set SDMA bus arbitration level to 5 (SDCR) */
 257         immap->im_siu_conf.sc_sdcr = 0x0001;
 258
 259         /* Initialize Tx/Rx parameters */
 260         iip->iic_rbase = rbase;
 261         iip->iic_tbase = tbase;
 262         rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]);
 263         txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]);
 264
 265         debug("[I2C] rbase = %04x\n", iip->iic_rbase);
 266         debug("[I2C] tbase = %04x\n", iip->iic_tbase);
 267         debug("[I2C] rxbd = %08x\n", (int)rxbd);
 268         debug("[I2C] txbd = %08x\n", (int)txbd);
 269
 270         /* Set big endian byte order */
 271         iip->iic_tfcr = 0x10;
 272         iip->iic_rfcr = 0x10;
 273
 274         /* Set maximum receive size. */
 275         iip->iic_mrblr = I2C_RXTX_LEN;
 276
 277 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 278         /*
 279          *  Initialize required parameters if using microcode patch.
 280          */
 281         iip->iic_rbptr = iip->iic_rbase;
 282         iip->iic_tbptr = iip->iic_tbase;
 283         iip->iic_rstate = 0;
 284         iip->iic_tstate = 0;
 285 #else
 286         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 287         do {
 288                 __asm__ __volatile__("eieio");
 289         } while (cp->cp_cpcr & CPM_CR_FLG);
 290 #endif
 291
 292         /* Clear events and interrupts */
 293         i2c->i2c_i2cer = 0xff;
 294         i2c->i2c_i2cmr = 0x00;
 295 }
 296
 297 static void i2c_newio(i2c_state_t *state)
 298 {
 299         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 300         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 301         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 302
 303         debug("[I2C] i2c_newio\n");
 304
 305 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 306         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 307 #endif
 308         state->rx_idx = 0;
 309         state->tx_idx = 0;
 310         state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase];
 311         state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase];
 312         state->tx_space = MAX_TX_SPACE;
 313         state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
 314         state->err_cb = NULL;
 315
 316         debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
 317         debug("[I2C] txbd = %08x\n", (int)state->txbd);
 318         debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
 319
 320         /* clear the buffer memory */
 321         memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
 322 }
 323
 324 static int
 325 i2c_send(i2c_state_t *state,
 326          unsigned char address,
 327          unsigned char secondary_address,
 328          unsigned int flags, unsigned short size, unsigned char *dataout)
 329 {
 330         volatile I2C_BD *txbd;
 331         int i, j;
 332
 333         debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
 334                 address, secondary_address, flags, size);
 335
 336         /* trying to send message larger than BD */
 337         if (size > I2C_RXTX_LEN)
 338                 return I2CERR_MSG_TOO_LONG;
 339
 340         /* no more free bds */
 341         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
 342                 return I2CERR_NO_BUFFERS;
 343
 344         txbd = (I2C_BD *) state->txbd;
 345         txbd->addr = state->tx_buf;
 346
 347         debug("[I2C] txbd = %08x\n", (int)txbd);
 348
 349         if (flags & I2CF_START_COND) {
 350                 debug("[I2C] Formatting addresses...\n");
 351                 if (flags & I2CF_ENABLE_SECONDARY) {
 352                         /* Length of msg + dest addr */
 353                         txbd->length = size + 2;
 354
 355                         txbd->addr[0] = address << 1;
 356                         txbd->addr[1] = secondary_address;
 357                         i = 2;
 358                 } else {
 359                         /* Length of msg + dest addr */
 360                         txbd->length = size + 1;
 361                         /* Write dest addr to BD */
 362                         txbd->addr[0] = address << 1;
 363                         i = 1;
 364                 }
 365         } else {
 366                 txbd->length = size;    /* Length of message */
 367                 i = 0;
 368         }
 369
 370         /* set up txbd */
 371         txbd->status = BD_SC_READY;
 372         if (flags & I2CF_START_COND)
 373                 txbd->status |= BD_I2C_TX_START;
 374         if (flags & I2CF_STOP_COND)
 375                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 376
 377         /* Copy data to send into buffer */
 378         debug("[I2C] copy data...\n");
 379         for(j = 0; j < size; i++, j++)
 380                 txbd->addr[i] = dataout[j];
 381
 382         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 383                 txbd->length,
 384                 txbd->status,
 385                 txbd->addr[0],
 386                 txbd->addr[1]);
 387
 388         /* advance state */
 389         state->tx_buf += txbd->length;
 390         state->tx_space -= txbd->length;
 391         state->tx_idx++;
 392         state->txbd = (void *) (txbd + 1);
 393
 394         return 0;
 395 }
 396
 397 static int
 398 i2c_receive(i2c_state_t *state,
 399             unsigned char address,
 400             unsigned char secondary_address,
 401             unsigned int flags,
 402             unsigned short size_to_expect, unsigned char *datain)
 403 {
 404         volatile I2C_BD *rxbd, *txbd;
 405
 406         debug("[I2C] i2c_receive %02d %02d %02d\n",
 407                 address, secondary_address, flags);
 408
 409         /* Expected to receive too much */
 410         if (size_to_expect > I2C_RXTX_LEN)
 411                 return I2CERR_MSG_TOO_LONG;
 412
 413         /* no more free bds */
 414         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
 415             || state->tx_space < 2)
 416                 return I2CERR_NO_BUFFERS;
 417
 418         rxbd = (I2C_BD *) state->rxbd;
 419         txbd = (I2C_BD *) state->txbd;
 420
 421         debug("[I2C] rxbd = %08x\n", (int)rxbd);
 422         debug("[I2C] txbd = %08x\n", (int)txbd);
 423
 424         txbd->addr = state->tx_buf;
 425
 426         /* set up TXBD for destination address */
 427         if (flags & I2CF_ENABLE_SECONDARY) {
 428                 txbd->length = 2;
 429                 txbd->addr[0] = address << 1;   /* Write data */
 430                 txbd->addr[1] = secondary_address;      /* Internal address */
 431                 txbd->status = BD_SC_READY;
 432         } else {
 433                 txbd->length = 1 + size_to_expect;
 434                 txbd->addr[0] = (address << 1) | 0x01;
 435                 txbd->status = BD_SC_READY;
 436                 memset(&txbd->addr[1], 0, txbd->length);
 437         }
 438
 439         /* set up rxbd for reception */
 440         rxbd->status = BD_SC_EMPTY;
 441         rxbd->length = size_to_expect;
 442         rxbd->addr = datain;
 443
 444         txbd->status |= BD_I2C_TX_START;
 445         if (flags & I2CF_STOP_COND) {
 446                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 447                 rxbd->status |= BD_SC_WRAP;
 448         }
 449
 450         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 451                 txbd->length,
 452                 txbd->status,
 453                 txbd->addr[0],
 454                 txbd->addr[1]);
 455         debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 456                 rxbd->length,
 457                 rxbd->status,
 458                 rxbd->addr[0],
 459                 rxbd->addr[1]);
 460
 461         /* advance state */
 462         state->tx_buf += txbd->length;
 463         state->tx_space -= txbd->length;
 464         state->tx_idx++;
 465         state->txbd = (void *) (txbd + 1);
 466         state->rx_idx++;
 467         state->rxbd = (void *) (rxbd + 1);
 468
 469         return 0;
 470 }
 471
 472
 473 static int i2c_doio(i2c_state_t *state)
 474 {
 475         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 476         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 477         volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
 478         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 479         volatile I2C_BD *txbd, *rxbd;
 480         volatile int j = 0;
 481
 482         debug("[I2C] i2c_doio\n");
 483
 484 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 485         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 486 #endif
 487
 488         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
 489                 debug("[I2C] No I/O is queued\n");
 490                 return I2CERR_QUEUE_EMPTY;
 491         }
 492
 493         iip->iic_rbptr = iip->iic_rbase;
 494         iip->iic_tbptr = iip->iic_tbase;
 495
 496         /* Enable I2C */
 497         debug("[I2C] Enabling I2C...\n");
 498         i2c->i2c_i2mod |= 0x01;
 499
 500         /* Begin transmission */
 501         i2c->i2c_i2com |= 0x80;
 502
 503         /* Loop until transmit & receive completed */
 504
 505         if (state->tx_idx > 0) {
 506                 txbd = ((I2C_BD*)state->txbd) - 1;
 507
 508                 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
 509                         (ulong)txbd);
 510
 511                 while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
 512                         if (ctrlc())
 513                                 return (-1);
 514
 515                         __asm__ __volatile__("eieio");
 516                 }
 517         }
 518
 519         if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
 520                 rxbd = ((I2C_BD*)state->rxbd) - 1;
 521
 522                 debug("[I2C] Receiving...(rxbd=0x%08lx)\n",
 523                         (ulong)rxbd);
 524
 525                 while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
 526                         if (ctrlc())
 527                                 return (-1);
 528
 529                         __asm__ __volatile__("eieio");
 530                 }
 531         }
 532
 533         /* Turn off I2C */
 534         i2c->i2c_i2mod &= ~0x01;
 535
 536         if (state->err_cb != NULL) {
 537                 int n, i, b;
 538
 539                 /*
 540                  * if we have an error callback function, look at the
 541                  * error bits in the bd status and pass them back
 542                  */
 543
 544                 if ((n = state->tx_idx) > 0) {
 545                         for (i = 0; i < n; i++) {
 546                                 txbd = ((I2C_BD *) state->txbd) - (n - i);
 547                                 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
 548                                         (*state->err_cb) (I2CECB_TX_ERR | b,
 549                                                           i);
 550                         }
 551                 }
 552
 553                 if ((n = state->rx_idx) > 0) {
 554                         for (i = 0; i < n; i++) {
 555                                 rxbd = ((I2C_BD *) state->rxbd) - (n - i);
 556                                 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
 557                                         (*state->err_cb) (I2CECB_RX_ERR | b,
 558                                                           i);
 559                         }
 560                 }
 561
 562                 if (j >= TOUT_LOOP)
 563                         (*state->err_cb) (I2CECB_TIMEOUT, 0);
 564         }
 565
 566         return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
 567 }
 568
 569 static int had_tx_nak;
 570
 571 static void i2c_test_callback(int flags, int xnum)
 572 {
 573         if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
 574                 had_tx_nak = 1;
 575 }
 576
 577 int i2c_probe(uchar chip)
 578 {
 579         i2c_state_t state;
 580         int rc;
 581         uchar buf[1];
 582
 583         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 584
 585         i2c_newio(&state);
 586
 587         state.err_cb = i2c_test_callback;
 588         had_tx_nak = 0;
 589
 590         rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
 591                          buf);
 592
 593         if (rc != 0)
 594                 return (rc);
 595
 596         rc = i2c_doio(&state);
 597
 598         if ((rc != 0) && (rc != I2CERR_TIMEOUT))
 599                 return (rc);
 600
 601         return (had_tx_nak);
 602 }
 603
 604 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 605 {
 606         i2c_state_t state;
 607         uchar xaddr[4];
 608         int rc;
 609
 610 #ifdef CONFIG_LWMON
 611         WATCHDOG_RESET();
 612 #endif
 613
 614         xaddr[0] = (addr >> 24) & 0xFF;
 615         xaddr[1] = (addr >> 16) & 0xFF;
 616         xaddr[2] = (addr >> 8) & 0xFF;
 617         xaddr[3] = addr & 0xFF;
 618
 619 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 620         /*
 621          * EEPROM chips that implement "address overflow" are ones like
 622          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 623          * extra bits end up in the "chip address" bit slots.  This makes
 624          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 625          *
 626          * Note that we consider the length of the address field to still
 627          * be one byte because the extra address bits are hidden in the
 628          * chip address.
 629          */
 630         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 631 #endif
 632
 633         i2c_newio(&state);
 634
 635         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 636                       &xaddr[4 - alen]);
 637         if (rc != 0) {
 638                 printf("i2c_read: i2c_send failed (%d)\n", rc);
 639                 return 1;
 640         }
 641
 642         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
 643         if (rc != 0) {
 644                 printf("i2c_read: i2c_receive failed (%d)\n", rc);
 645                 return 1;
 646         }
 647
 648         rc = i2c_doio(&state);
 649         if (rc != 0) {
 650                 printf("i2c_read: i2c_doio failed (%d)\n", rc);
 651                 return 1;
 652         }
 653         return 0;
 654 }
 655
 656 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 657 {
 658         i2c_state_t state;
 659         uchar xaddr[4];
 660         int rc;
 661
 662         xaddr[0] = (addr >> 24) & 0xFF;
 663         xaddr[1] = (addr >> 16) & 0xFF;
 664         xaddr[2] = (addr >> 8) & 0xFF;
 665         xaddr[3] = addr & 0xFF;
 666
 667 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 668         /*
 669          * EEPROM chips that implement "address overflow" are ones like
 670          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 671          * extra bits end up in the "chip address" bit slots.  This makes
 672          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 673          *
 674          * Note that we consider the length of the address field to still
 675          * be one byte because the extra address bits are hidden in the
 676          * chip address.
 677          */
 678         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 679 #endif
 680
 681         i2c_newio(&state);
 682
 683         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 684                       &xaddr[4 - alen]);
 685         if (rc != 0) {
 686                 printf("i2c_write: first i2c_send failed (%d)\n", rc);
 687                 return 1;
 688         }
 689
 690         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
 691         if (rc != 0) {
 692                 printf("i2c_write: second i2c_send failed (%d)\n", rc);
 693                 return 1;
 694         }
 695
 696         rc = i2c_doio(&state);
 697         if (rc != 0) {
 698                 printf("i2c_write: i2c_doio failed (%d)\n", rc);
 699                 return 1;
 700         }
 701         return 0;
 702 }
 703
 704 #endif /* CONFIG_HARD_I2C */