1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
10 #define PCI_DEV_CONFIG(segbus, dev, fn) ( \
11 (((segbus) & 0xfff) << 20) | \
12 (((dev) & 0x1f) << 15) | \
13 (((fn) & 0x07) << 12))
15 /* Platform Controller Unit */
20 #define UART_CONT 0x80
22 /* SCORE Pad definitions */
23 #define UART_RXD_PAD 82
24 #define UART_TXD_PAD 83
26 /* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
27 #define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
30 #define IO_BASE_ADDRESS 0xfed0c000
31 #define IO_BASE_OFFSET_GPSCORE 0x0000
32 #define IO_BASE_OFFSET_GPNCORE 0x1000
33 #define IO_BASE_OFFSET_GPSSUS 0x2000
34 #define IO_BASE_SIZE 0x4000
36 static inline unsigned int score_pconf0(int pad_num)
38 return GPSCORE_PAD_BASE + pad_num * 16;
41 static void score_select_func(int pad, int func)
44 uint32_t pconf0_addr = score_pconf0(pad);
46 reg = readl(pconf0_addr);
49 writel(reg, pconf0_addr);
52 static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
56 addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
60 /* This can be called after memory-mapped PCI is working */
61 int setup_internal_uart(int enable)
63 /* Enable or disable the legacy UART hardware */
64 x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
67 /* All done for the disable part, so just return */
72 * Set up the pads to the UART function. This allows the signals to
75 score_select_func(UART_RXD_PAD, 1);
76 score_select_func(UART_TXD_PAD, 1);
78 /* TODO(sjg@chromium.org): Call debug_uart_init() */
83 void board_debug_uart_init(void)
85 setup_internal_uart(1);