1 // SPDX-License-Identifier: GPL-2.0
3 * From Coreboot northbridge/intel/sandybridge/northbridge.c
5 * Copyright (C) 2007-2009 coresystems GmbH
6 * Copyright (C) 2011 The Chromium Authors
13 #include <asm/intel_regs.h>
16 #include <asm/processor.h>
17 #include <asm/arch/pch.h>
18 #include <asm/arch/model_206ax.h>
19 #include <asm/arch/sandybridge.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 int bridge_silicon_revision(struct udevice *dev)
25 struct cpuid_result result;
30 stepping = result.eax & 0xf;
31 dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id);
33 return bridge_id | stepping;
36 static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len)
43 dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg);
45 if (!(pciexbar_reg & (1 << 0)))
48 switch ((pciexbar_reg >> 1) & 3) {
50 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
52 *len = 256 * 1024 * 1024;
55 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
56 (1 << 28) | (1 << 27));
57 *len = 128 * 1024 * 1024;
60 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
61 (1 << 28) | (1 << 27) | (1 << 26));
62 *len = 64 * 1024 * 1024;
69 static void add_fixed_resources(struct udevice *dev, int index)
71 u32 pcie_config_base, pcie_config_size;
73 if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) {
74 debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
75 pcie_config_base, pcie_config_size);
79 static void northbridge_dmi_init(struct udevice *dev, int rev)
81 /* Clear error status bits */
82 writel(0xffffffff, DMIBAR_REG(0x1c4));
83 writel(0xffffffff, DMIBAR_REG(0x1d0));
85 /* Steps prior to DMI ASPM */
86 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
87 clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
91 setbits_le32(DMIBAR_REG(0x238), 1 << 29);
93 if (rev >= SNB_STEP_D0) {
94 setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
95 } else if (rev >= SNB_STEP_D1) {
96 clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
97 setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
100 /* Enable ASPM on SNB link, should happen before PCH link */
101 if ((rev & BASE_REV_MASK) == BASE_REV_SNB)
102 setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
104 setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
107 static void northbridge_init(struct udevice *dev, int rev)
111 add_fixed_resources(dev, 6);
112 northbridge_dmi_init(dev, rev);
114 bridge_type = readl(MCHBAR_REG(0x5f10));
115 bridge_type &= ~0xff;
117 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
118 /* Enable Power Aware Interrupt Routing - fixed priority */
119 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
121 /* 30h for IvyBridge */
124 /* 20h for Sandybridge */
127 writel(bridge_type, MCHBAR_REG(0x5f10));
130 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
131 * that BIOS has initialized memory and power management
133 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1);
134 debug("Set BIOS_RESET_CPL\n");
136 /* Configure turbo power limits 1ms after reset complete bit */
138 set_power_limits(28);
141 * CPUs with configurable TDP also need power limits set
142 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
144 if (cpu_config_tdp_levels()) {
145 msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
147 writel(msr.lo, MCHBAR_REG(0x59A0));
148 writel(msr.hi, MCHBAR_REG(0x59A4));
151 /* Set here before graphics PM init */
152 writel(0x00100001, MCHBAR_REG(0x5500));
155 static void sandybridge_setup_northbridge_bars(struct udevice *dev)
157 /* Set up all hardcoded northbridge BARs */
158 debug("Setting up static registers\n");
159 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
160 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
161 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
162 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
163 /* 64MB - busses 0-63 */
164 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
165 dm_pci_write_config32(dev, PCIEXBAR + 4,
166 (0LL + DEFAULT_PCIEXBAR) >> 32);
167 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1);
168 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
170 /* Set C0000-FFFFF to access RAM on both reads and writes */
171 dm_pci_write_config8(dev, PAM0, 0x30);
172 dm_pci_write_config8(dev, PAM1, 0x33);
173 dm_pci_write_config8(dev, PAM2, 0x33);
174 dm_pci_write_config8(dev, PAM3, 0x33);
175 dm_pci_write_config8(dev, PAM4, 0x33);
176 dm_pci_write_config8(dev, PAM5, 0x33);
177 dm_pci_write_config8(dev, PAM6, 0x33);
180 static int bd82x6x_northbridge_early_init(struct udevice *dev)
182 const int chipset_type = SANDYBRIDGE_MOBILE;
186 /* Device ID Override Enable should be done very early */
187 dm_pci_read_config32(dev, 0xe4, &capid0_a);
188 if (capid0_a & (1 << 10)) {
189 dm_pci_read_config8(dev, 0xf3, ®8);
190 reg8 &= ~7; /* Clear 2:0 */
192 if (chipset_type == SANDYBRIDGE_MOBILE)
193 reg8 |= 1; /* Set bit 0 */
195 dm_pci_write_config8(dev, 0xf3, reg8);
198 sandybridge_setup_northbridge_bars(dev);
201 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
206 static int bd82x6x_northbridge_probe(struct udevice *dev)
210 if (!(gd->flags & GD_FLG_RELOC))
211 return bd82x6x_northbridge_early_init(dev);
213 rev = bridge_silicon_revision(dev);
214 northbridge_init(dev, rev);
219 static const struct udevice_id bd82x6x_northbridge_ids[] = {
220 { .compatible = "intel,bd82x6x-northbridge" },
224 U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
225 .name = "bd82x6x_northbridge",
226 .id = UCLASS_NORTHBRIDGE,
227 .of_match = bd82x6x_northbridge_ids,
228 .probe = bd82x6x_northbridge_probe,