git.sur5r.net Git - u-boot/blob - arch/x86/dts/crownbay.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/interrupt-router/intel-irq.h>
   9
  10 /include/ "skeleton.dtsi"
  11 /include/ "serial.dtsi"
  12 /include/ "keyboard.dtsi"
  13 /include/ "rtc.dtsi"
  14 /include/ "tsc_timer.dtsi"
  15
  16 / {
  17         model = "Intel Crown Bay";
  18         compatible = "intel,crownbay", "intel,queensbay";
  19
  20         aliases {
  21                 spi0 = &spi;
  22         };
  23
  24         config {
  25                 silent_console = <0>;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "cpu-x86";
  35                         reg = <0>;
  36                         intel,apic-id = <0>;
  37                 };
  38
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "cpu-x86";
  42                         reg = <1>;
  43                         intel,apic-id = <1>;
  44                 };
  45
  46         };
  47
  48         chosen {
  49                 /*
  50                  * By default the legacy superio serial port is used as the
  51                  * U-Boot serial console. If we want to use UART from Topcliff
  52                  * PCH as the console, change this property to &pciuart#.
  53                  *
  54                  * For example, stdout-path = &pciuart0 will use the first
  55                  * UART on Topcliff PCH.
  56                  */
  57                 stdout-path = "/serial";
  58         };
  59
  60         microcode {
  61                 update@0 {
  62 #include "microcode/m0220661105_cv.dtsi"
  63                 };
  64         };
  65
  66         pci {
  67                 #address-cells = <3>;
  68                 #size-cells = <2>;
  69                 compatible = "pci-x86";
  70                 u-boot,dm-pre-reloc;
  71                 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
  72                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  73                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  74
  75                 pcie@17,0 {
  76                         #address-cells = <3>;
  77                         #size-cells = <2>;
  78                         compatible = "pci-bridge";
  79                         u-boot,dm-pre-reloc;
  80                         reg = <0x0000b800 0x0 0x0 0x0 0x0>;
  81
  82                         topcliff@0,0 {
  83                                 #address-cells = <3>;
  84                                 #size-cells = <2>;
  85                                 compatible = "pci-bridge";
  86                                 u-boot,dm-pre-reloc;
  87                                 reg = <0x00010000 0x0 0x0 0x0 0x0>;
  88
  89                                 pciuart0: uart@a,1 {
  90                                         compatible = "pci8086,8811.00",
  91                                                         "pci8086,8811",
  92                                                         "pciclass,070002",
  93                                                         "pciclass,0700",
  94                                                         "ns16550";
  95                                         u-boot,dm-pre-reloc;
  96                                         reg = <0x00025100 0x0 0x0 0x0 0x0
  97                                                0x01025110 0x0 0x0 0x0 0x0>;
  98                                         reg-shift = <0>;
  99                                         clock-frequency = <1843200>;
 100                                         current-speed = <115200>;
 101                                 };
 102
 103                                 pciuart1: uart@a,2 {
 104                                         compatible = "pci8086,8812.00",
 105                                                         "pci8086,8812",
 106                                                         "pciclass,070002",
 107                                                         "pciclass,0700",
 108                                                         "ns16550";
 109                                         u-boot,dm-pre-reloc;
 110                                         reg = <0x00025200 0x0 0x0 0x0 0x0
 111                                                0x01025210 0x0 0x0 0x0 0x0>;
 112                                         reg-shift = <0>;
 113                                         clock-frequency = <1843200>;
 114                                         current-speed = <115200>;
 115                                 };
 116
 117                                 pciuart2: uart@a,3 {
 118                                         compatible = "pci8086,8813.00",
 119                                                         "pci8086,8813",
 120                                                         "pciclass,070002",
 121                                                         "pciclass,0700",
 122                                                         "ns16550";
 123                                         u-boot,dm-pre-reloc;
 124                                         reg = <0x00025300 0x0 0x0 0x0 0x0
 125                                                0x01025310 0x0 0x0 0x0 0x0>;
 126                                         reg-shift = <0>;
 127                                         clock-frequency = <1843200>;
 128                                         current-speed = <115200>;
 129                                 };
 130
 131                                 pciuart3: uart@a,4 {
 132                                         compatible = "pci8086,8814.00",
 133                                                         "pci8086,8814",
 134                                                         "pciclass,070002",
 135                                                         "pciclass,0700",
 136                                                         "ns16550";
 137                                         u-boot,dm-pre-reloc;
 138                                         reg = <0x00025400 0x0 0x0 0x0 0x0
 139                                                0x01025410 0x0 0x0 0x0 0x0>;
 140                                         reg-shift = <0>;
 141                                         clock-frequency = <1843200>;
 142                                         current-speed = <115200>;
 143                                 };
 144                         };
 145                 };
 146
 147                 pch@1f,0 {
 148                         reg = <0x0000f800 0 0 0 0>;
 149                         compatible = "intel,pch7";
 150                         #address-cells = <1>;
 151                         #size-cells = <1>;
 152
 153                         irq-router {
 154                                 compatible = "intel,queensbay-irq-router";
 155                                 intel,pirq-config = "pci";
 156                                 intel,actl-addr = <0x58>;
 157                                 intel,pirq-link = <0x60 8>;
 158                                 intel,pirq-mask = <0xcee0>;
 159                                 intel,pirq-routing = <
 160                                         /* TunnelCreek PCI devices */
 161                                         PCI_BDF(0, 2, 0) INTA PIRQE
 162                                         PCI_BDF(0, 3, 0) INTA PIRQF
 163                                         PCI_BDF(0, 23, 0) INTA PIRQA
 164                                         PCI_BDF(0, 23, 0) INTB PIRQB
 165                                         PCI_BDF(0, 23, 0) INTC PIRQC
 166                                         PCI_BDF(0, 23, 0) INTD PIRQD
 167                                         PCI_BDF(0, 24, 0) INTA PIRQB
 168                                         PCI_BDF(0, 24, 0) INTB PIRQC
 169                                         PCI_BDF(0, 24, 0) INTC PIRQD
 170                                         PCI_BDF(0, 24, 0) INTD PIRQA
 171                                         PCI_BDF(0, 25, 0) INTA PIRQC
 172                                         PCI_BDF(0, 25, 0) INTB PIRQD
 173                                         PCI_BDF(0, 25, 0) INTC PIRQA
 174                                         PCI_BDF(0, 25, 0) INTD PIRQB
 175                                         PCI_BDF(0, 26, 0) INTA PIRQD
 176                                         PCI_BDF(0, 26, 0) INTB PIRQA
 177                                         PCI_BDF(0, 26, 0) INTC PIRQB
 178                                         PCI_BDF(0, 26, 0) INTD PIRQC
 179                                         PCI_BDF(0, 27, 0) INTA PIRQG
 180                                         /*
 181                                         * Topcliff PCI devices
 182                                         *
 183                                         * Note on the Crown Bay board, Topcliff
 184                                         * chipset is connected to TunnelCreek
 185                                         * PCIe port 0, so its bus number is 1
 186                                         * for its PCIe port and 2 for its PCI
 187                                         * devices per U-Boot current PCI bus
 188                                         * enumeration algorithm.
 189                                         */
 190                                         PCI_BDF(1, 0, 0) INTA PIRQA
 191                                         PCI_BDF(2, 0, 1) INTA PIRQA
 192                                         PCI_BDF(2, 0, 2) INTA PIRQA
 193                                         PCI_BDF(2, 2, 0) INTB PIRQD
 194                                         PCI_BDF(2, 2, 1) INTB PIRQD
 195                                         PCI_BDF(2, 2, 2) INTB PIRQD
 196                                         PCI_BDF(2, 2, 3) INTB PIRQD
 197                                         PCI_BDF(2, 2, 4) INTB PIRQD
 198                                         PCI_BDF(2, 4, 0) INTC PIRQC
 199                                         PCI_BDF(2, 4, 1) INTC PIRQC
 200                                         PCI_BDF(2, 6, 0) INTD PIRQB
 201                                         PCI_BDF(2, 8, 0) INTA PIRQA
 202                                         PCI_BDF(2, 8, 1) INTA PIRQA
 203                                         PCI_BDF(2, 8, 2) INTA PIRQA
 204                                         PCI_BDF(2, 8, 3) INTA PIRQA
 205                                         PCI_BDF(2, 10, 0) INTB PIRQD
 206                                         PCI_BDF(2, 10, 1) INTB PIRQD
 207                                         PCI_BDF(2, 10, 2) INTB PIRQD
 208                                         PCI_BDF(2, 10, 3) INTB PIRQD
 209                                         PCI_BDF(2, 10, 4) INTB PIRQD
 210                                         PCI_BDF(2, 12, 0) INTC PIRQC
 211                                         PCI_BDF(2, 12, 1) INTC PIRQC
 212                                         PCI_BDF(2, 12, 2) INTC PIRQC
 213                                         PCI_BDF(2, 12, 3) INTC PIRQC
 214                                         PCI_BDF(2, 12, 4) INTC PIRQC
 215                                 >;
 216                         };
 217
 218                         spi: spi {
 219                                 #address-cells = <1>;
 220                                 #size-cells = <0>;
 221                                 compatible = "intel,ich7-spi";
 222                                 spi-flash@0 {
 223                                         reg = <0>;
 224                                         compatible = "sst,25vf016b",
 225                                                 "spi-flash";
 226                                         memory-map = <0xffe00000 0x00200000>;
 227                                 };
 228                         };
 229
 230                         gpioa {
 231                                 compatible = "intel,ich6-gpio";
 232                                 u-boot,dm-pre-reloc;
 233                                 reg = <0 0x20>;
 234                                 bank-name = "A";
 235                         };
 236
 237                         gpiob {
 238                                 compatible = "intel,ich6-gpio";
 239                                 u-boot,dm-pre-reloc;
 240                                 reg = <0x20 0x20>;
 241                                 bank-name = "B";
 242                         };
 243                 };
 244         };
 245
 246 };