git.sur5r.net Git - u-boot/blob - arch/x86/dts/galileo.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/mrc/quark.h>
   9 #include <dt-bindings/interrupt-router/intel-irq.h>
  10
  11 /include/ "skeleton.dtsi"
  12 /include/ "rtc.dtsi"
  13 /include/ "tsc_timer.dtsi"
  14
  15 / {
  16         model = "Intel Galileo";
  17         compatible = "intel,galileo", "intel,quark";
  18
  19         aliases {
  20                 spi0 = &spi;
  21         };
  22
  23         config {
  24                 silent_console = <0>;
  25         };
  26
  27         chosen {
  28                 stdout-path = &pciuart0;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "cpu-x86";
  38                         reg = <0>;
  39                         intel,apic-id = <0>;
  40                 };
  41         };
  42
  43         tsc-timer {
  44                 clock-frequency = <400000000>;
  45         };
  46
  47         mrc {
  48                 compatible = "intel,quark-mrc";
  49                 flags = <MRC_FLAG_SCRAMBLE_EN>;
  50                 dram-width = <DRAM_WIDTH_X8>;
  51                 dram-speed = <DRAM_FREQ_800>;
  52                 dram-type = <DRAM_TYPE_DDR3>;
  53                 rank-mask = <DRAM_RANK(0)>;
  54                 chan-mask = <DRAM_CHANNEL(0)>;
  55                 chan-width = <DRAM_CHANNEL_WIDTH_X16>;
  56                 addr-mode = <DRAM_ADDR_MODE0>;
  57                 refresh-rate = <DRAM_REFRESH_RATE_785US>;
  58                 sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
  59                 ron-value = <DRAM_RON_34OHM>;
  60                 rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
  61                 rd-odt-value = <DRAM_RD_ODT_OFF>;
  62                 dram-density = <DRAM_DENSITY_1G>;
  63                 dram-cl = <6>;
  64                 dram-ras = <0x0000927c>;
  65                 dram-wtr = <0x00002710>;
  66                 dram-rrd = <0x00002710>;
  67                 dram-faw = <0x00009c40>;
  68         };
  69
  70         pci {
  71                 #address-cells = <3>;
  72                 #size-cells = <2>;
  73                 compatible = "pci-x86";
  74                 u-boot,dm-pre-reloc;
  75                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
  76                           0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
  77                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  78
  79                 pciuart0: uart@14,5 {
  80                         compatible = "pci8086,0936.00",
  81                                         "pci8086,0936",
  82                                         "pciclass,070002",
  83                                         "pciclass,0700",
  84                                         "ns16550";
  85                         u-boot,dm-pre-reloc;
  86                         reg = <0x0000a500 0x0 0x0 0x0 0x0
  87                                0x0200a510 0x0 0x0 0x0 0x0>;
  88                         reg-shift = <2>;
  89                         clock-frequency = <44236800>;
  90                         current-speed = <115200>;
  91                 };
  92
  93                 pch@1f,0 {
  94                         reg = <0x0000f800 0 0 0 0>;
  95                         compatible = "intel,pch7";
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98
  99                         irq-router {
 100                                 compatible = "intel,quark-irq-router";
 101                                 intel,pirq-config = "pci";
 102                                 intel,actl-addr = <0x58>;
 103                                 intel,pirq-link = <0x60 8>;
 104                                 intel,pirq-mask = <0xdef8>;
 105                                 intel,pirq-routing = <
 106                                         PCI_BDF(0, 20, 0) INTA PIRQE
 107                                         PCI_BDF(0, 20, 1) INTB PIRQF
 108                                         PCI_BDF(0, 20, 2) INTC PIRQG
 109                                         PCI_BDF(0, 20, 3) INTD PIRQH
 110                                         PCI_BDF(0, 20, 4) INTA PIRQE
 111                                         PCI_BDF(0, 20, 5) INTB PIRQF
 112                                         PCI_BDF(0, 20, 6) INTC PIRQG
 113                                         PCI_BDF(0, 20, 7) INTD PIRQH
 114                                         PCI_BDF(0, 21, 0) INTA PIRQE
 115                                         PCI_BDF(0, 21, 1) INTB PIRQF
 116                                         PCI_BDF(0, 21, 2) INTC PIRQG
 117                                         PCI_BDF(0, 23, 0) INTA PIRQA
 118                                         PCI_BDF(0, 23, 1) INTB PIRQB
 119
 120                                         /* PCIe root ports downstream interrupts */
 121                                         PCI_BDF(1, 0, 0) INTA PIRQA
 122                                         PCI_BDF(1, 0, 0) INTB PIRQB
 123                                         PCI_BDF(1, 0, 0) INTC PIRQC
 124                                         PCI_BDF(1, 0, 0) INTD PIRQD
 125                                         PCI_BDF(2, 0, 0) INTA PIRQB
 126                                         PCI_BDF(2, 0, 0) INTB PIRQC
 127                                         PCI_BDF(2, 0, 0) INTC PIRQD
 128                                         PCI_BDF(2, 0, 0) INTD PIRQA
 129                                 >;
 130                         };
 131
 132                         spi: spi {
 133                                 #address-cells = <1>;
 134                                 #size-cells = <0>;
 135                                 compatible = "intel,ich7-spi";
 136                                 spi-flash@0 {
 137                                         #size-cells = <1>;
 138                                         #address-cells = <1>;
 139                                         reg = <0>;
 140                                         compatible = "winbond,w25q64",
 141                                                 "spi-flash";
 142                                         memory-map = <0xff800000 0x00800000>;
 143                                         rw-mrc-cache {
 144                                                 label = "rw-mrc-cache";
 145                                                 reg = <0x00010000 0x00010000>;
 146                                         };
 147                                 };
 148                         };
 149
 150                         gpioa {
 151                                 compatible = "intel,ich6-gpio";
 152                                 u-boot,dm-pre-reloc;
 153                                 reg = <0 0x20>;
 154                                 bank-name = "A";
 155                         };
 156
 157                         gpiob {
 158                                 compatible = "intel,ich6-gpio";
 159                                 u-boot,dm-pre-reloc;
 160                                 reg = <0x20 0x20>;
 161                                 bank-name = "B";
 162                         };
 163                 };
 164         };
 165
 166 };