git.sur5r.net Git - u-boot/blob - arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h

   1 /* SPDX-License-Identifier: Intel */
   2 /*
   3  * Copyright (C) 2015, Intel Corporation
   4  * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
   5  */
   6
   7 #ifndef __FSP_VPD_H__
   8 #define __FSP_VPD_H__
   9
  10 struct __packed memory_upd {
  11         u64 signature;                          /* Offset 0x0020 */
  12         u8 revision;                            /* Offset 0x0028 */
  13         u8 unused2[7];                          /* Offset 0x0029 */
  14         u16 mrc_init_tseg_size;                 /* Offset 0x0030 */
  15         u16 mrc_init_mmio_size;                 /* Offset 0x0032 */
  16         u8 mrc_init_spd_addr1;                  /* Offset 0x0034 */
  17         u8 mrc_init_spd_addr2;                  /* Offset 0x0035 */
  18         u8 mem_ch0_config;                      /* Offset 0x0036 */
  19         u8 mem_ch1_config;                      /* Offset 0x0037 */
  20         u32 memory_spd_ptr;                     /* Offset 0x0038 */
  21         u8 igd_dvmt50_pre_alloc;                /* Offset 0x003c */
  22         u8 aperture_size;                       /* Offset 0x003d */
  23         u8 gtt_size;                            /* Offset 0x003e */
  24         u8 legacy_seg_decode;                   /* Offset 0x003f */
  25         u8 enable_dvfs;                         /* Offset 0x0040 */
  26         u8 memory_type;                         /* Offset 0x0041 */
  27         u8 enable_ca_mirror;                    /* Offset 0x0042 */
  28         u8 reserved[189];                       /* Offset 0x0043 */
  29 };
  30
  31 struct gpio_family {
  32         u32 confg;
  33         u32 confg_changes;
  34         u32 misc;
  35         u32 mmio_addr;
  36         wchar_t *name;
  37 };
  38
  39 struct gpio_pad {
  40         u32 confg0;
  41         u32 confg0_changes;
  42         u32 confg1;
  43         u32 confg1_changes;
  44         u32 community;
  45         u32 mmio_addr;
  46         wchar_t *name;
  47         u32 misc;
  48 };
  49
  50 struct __packed silicon_upd {
  51         u64 signature;                          /* Offset 0x0100 */
  52         u8 revision;                            /* Offset 0x0108 */
  53         u8 unused3[7];                          /* Offset 0x0109 */
  54         u8 sdcard_mode;                         /* Offset 0x0110 */
  55         u8 enable_hsuart0;                      /* Offset 0x0111 */
  56         u8 enable_hsuart1;                      /* Offset 0x0112 */
  57         u8 enable_azalia;                       /* Offset 0x0113 */
  58         struct azalia_config *azalia_cfg_ptr;   /* Offset 0x0114 */
  59         u8 enable_sata;                         /* Offset 0x0118 */
  60         u8 enable_xhci;                         /* Offset 0x0119 */
  61         u8 lpe_mode;                            /* Offset 0x011a */
  62         u8 enable_dma0;                         /* Offset 0x011b */
  63         u8 enable_dma1;                         /* Offset 0x011c */
  64         u8 enable_i2c0;                         /* Offset 0x011d */
  65         u8 enable_i2c1;                         /* Offset 0x011e */
  66         u8 enable_i2c2;                         /* Offset 0x011f */
  67         u8 enable_i2c3;                         /* Offset 0x0120 */
  68         u8 enable_i2c4;                         /* Offset 0x0121 */
  69         u8 enable_i2c5;                         /* Offset 0x0122 */
  70         u8 enable_i2c6;                         /* Offset 0x0123 */
  71         u32 graphics_config_ptr;                /* Offset 0x0124 */
  72         struct gpio_family *gpio_familiy_ptr;   /* Offset 0x0128 */
  73         struct gpio_pad *gpio_pad_ptr;          /* Offset 0x012c */
  74         u8 disable_punit_pwr_config;            /* Offset 0x0130 */
  75         u8 chv_svid_config;                     /* Offset 0x0131 */
  76         u8 disable_dptf;                        /* Offset 0x0132 */
  77         u8 emmc_mode;                           /* Offset 0x0133 */
  78         u8 usb3_clk_ssc;                        /* Offset 0x0134 */
  79         u8 disp_clk_ssc;                        /* Offset 0x0135 */
  80         u8 sata_clk_ssc;                        /* Offset 0x0136 */
  81         u8 usb2_port0_pe_txi_set;               /* Offset 0x0137 */
  82         u8 usb2_port0_txi_set;                  /* Offset 0x0138 */
  83         u8 usb2_port0_tx_emphasis_en;           /* Offset 0x0139 */
  84         u8 usb2_port0_tx_pe_half;               /* Offset 0x013a */
  85         u8 usb2_port1_pe_txi_set;               /* Offset 0x013b */
  86         u8 usb2_port1_txi_set;                  /* Offset 0x013c */
  87         u8 usb2_port1_tx_emphasis_en;           /* Offset 0x013d */
  88         u8 usb2_port1_tx_pe_half;               /* Offset 0x013e */
  89         u8 usb2_port2_pe_txi_set;               /* Offset 0x013f */
  90         u8 usb2_port2_txi_set;                  /* Offset 0x0140 */
  91         u8 usb2_port2_tx_emphasis_en;           /* Offset 0x0141 */
  92         u8 usb2_port2_tx_pe_half;               /* Offset 0x0142 */
  93         u8 usb2_port3_pe_txi_set;               /* Offset 0x0143 */
  94         u8 usb2_port3_txi_set;                  /* Offset 0x0144 */
  95         u8 usb2_port3_tx_emphasis_en;           /* Offset 0x0145 */
  96         u8 usb2_port3_tx_pe_half;               /* Offset 0x0146 */
  97         u8 usb2_port4_pe_txi_set;               /* Offset 0x0147 */
  98         u8 usb2_port4_txi_set;                  /* Offset 0x0148 */
  99         u8 usb2_port4_tx_emphasis_en;           /* Offset 0x0149 */
 100         u8 usb2_port4_tx_pe_half;               /* Offset 0x014a */
 101         u8 usb3_lane0_ow2tap_gen2_deemph3p5;    /* Offset 0x014b */
 102         u8 usb3_lane1_ow2tap_gen2_deemph3p5;    /* Offset 0x014c */
 103         u8 usb3_lane2_ow2tap_gen2_deemph3p5;    /* Offset 0x014d */
 104         u8 usb3_lane3_ow2tap_gen2_deemph3p5;    /* Offset 0x014e */
 105         u8 sata_speed;                          /* Offset 0x014f */
 106         u8 usb_ssic_port;                       /* Offset 0x0150 */
 107         u8 usb_hsic_port;                       /* Offset 0x0151 */
 108         u8 pcie_rootport_speed;                 /* Offset 0x0152 */
 109         u8 enable_ssic;                         /* Offset 0x0153 */
 110         u32 logo_ptr;                           /* Offset 0x0154 */
 111         u32 logo_size;                          /* Offset 0x0158 */
 112         u8 rtc_lock;                            /* Offset 0x015c */
 113         u8 pmic_i2c_bus;                        /* Offset 0x015d */
 114         u8 enable_isp;                          /* Offset 0x015e */
 115         u8 isp_pci_dev_config;                  /* Offset 0x015f */
 116         u8 turbo_mode;                          /* Offset 0x0160 */
 117         u8 pnp_settings;                        /* Offset 0x0161 */
 118         u8 sd_detect_chk;                       /* Offset 0x0162 */
 119         u8 reserved[411];                       /* Offset 0x0163 */
 120 };
 121
 122 #define MEMORY_UPD_ID   0x244450554d454d24      /* '$MEMUPD$' */
 123 #define SILICON_UPD_ID  0x244450555f495324      /* '$SI_UPD$' */
 124
 125 struct __packed upd_region {
 126         u64 signature;                          /* Offset 0x0000 */
 127         u8 revision;                            /* Offset 0x0008 */
 128         u8 unused0[7];                          /* Offset 0x0009 */
 129         u32 memory_upd_offset;                  /* Offset 0x0010 */
 130         u32 silicon_upd_offset;                 /* Offset 0x0014 */
 131         u64 unused1;                            /* Offset 0x0018 */
 132         struct memory_upd memory_upd;           /* Offset 0x0020 */
 133         struct silicon_upd silicon_upd;         /* Offset 0x0100 */
 134         u16 terminator;                         /* Offset 0x02fe */
 135 };
 136
 137 #define VPD_IMAGE_ID    0x2450534657534224      /* '$BSWFSP$' */
 138
 139 struct __packed vpd_region {
 140         u64 sign;                               /* Offset 0x0000 */
 141         u32 img_rev;                            /* Offset 0x0008 */
 142         u32 upd_offset;                         /* Offset 0x000c */
 143 };
 144
 145 #endif /* __FSP_VPD_H__ */