1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * From Coreboot soc/intel/broadwell/include/soc/pei_data.h
5 * Copyright (C) 2014 Google Inc.
8 #ifndef ASM_ARCH_PEI_DATA_H
9 #define ASM_ARCH_PEI_DATA_H
11 #include <linux/linkage.h>
13 #define PEI_VERSION 22
15 typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
18 BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
19 BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */
20 BOARD_TYPE_USER1, /* SV mobile */
21 BOARD_TYPE_USER2, /* SV desktop */
22 BOARD_TYPE_USER3, /* SV server */
23 BOARD_TYPE_ULT, /* ULT */
24 BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */
28 #define MAX_USB2_PORTS 14
29 #define MAX_USB3_PORTS 6
30 #define USB_OC_PIN_SKIP 8
32 enum usb2_port_location {
33 USB_PORT_BACK_PANEL = 0,
40 USB_PORT_NGFF_DEVICE_DOWN,
43 struct usb2_port_setting {
46 * [16:4] = length in inches in octal format
47 * [3:0] = decimal point
55 struct usb3_port_setting {
59 * Set to 0 if trace length is > 5 inches
60 * Set to 1 if trace length is <= 5 inches
69 enum board_type board_type;
83 uint32_t temp_mmio_base;
87 * 0 = leave channel enabled
88 * 1 = disable dimm 0 on channel
89 * 2 = disable dimm 1 on channel
90 * 3 = disable dimm 0+1 on channel
92 int dimm_channel0_disabled;
93 int dimm_channel1_disabled;
94 /* Set to 0 for memory down */
95 uint8_t spd_addresses[4];
96 /* Enable 2x Refresh Mode */
98 /* DQ pins are interleaved on board */
99 int dq_pins_interleaved;
100 /* Limit DDR3 frequency */
102 /* Disable self refresh */
103 int disable_self_refresh;
104 /* Disable cmd power/CKEPD */
107 /* USB port configuration */
108 struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
109 struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
112 * USB3 board specific PHY tuning
115 /* Valid range: 0x69 - 0x80 */
116 uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
117 /* Valid range: 0x80 - 0x9c */
118 uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
119 /* Valid range: 0x39 - 0x80 */
120 uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
121 /* Valid range: 0x3d - 0x4a */
122 uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
124 /* Console output function */
125 tx_byte_func tx_byte;
128 * DIMM SPD data for memory down configurations
129 * [CHANNEL][SLOT][SPD]
131 uint8_t spd_data[2][2][512];
135 * [CHANNEL][ITERATION][2]
137 * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
138 * DQByteMap[0] - ClkDQByteMap:
139 * - If clock is per rank, program to [0xFF, 0xFF]
140 * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
141 * - If clock is shared by 2 ranks but does not go to all bytes,
142 * Entry[i] defines which DQ bytes Group i services
143 * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
144 * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
145 * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
146 * For DDR, DQByteMap[3:1] = [0xFF, 0]
147 * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
148 * since we have 1 CTL / rank
149 * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
150 * since we have 1 CA Vref
152 uint8_t dq_map[2][6][2];
155 * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
156 * [CHANNEL][MAX_BYTES]
158 uint8_t dqs_map[2][8];
160 /* Data read from flash and passed into MRC */
161 const void *saved_data;
164 /* Disable use of saved data (can be set by mainboard) */
165 int disable_saved_data;
167 /* Data from MRC that should be saved to flash */
169 int data_to_save_size;
170 struct pei_memory_info meminfo;
173 void mainboard_fill_pei_data(struct pei_data *pei_data);
174 void broadwell_fill_pei_data(struct pei_data *pei_data);