git.sur5r.net Git - u-boot/blob - board/compulab/cm_t43/spl.c

   1 /*
   2  * Copyright (C) 2016 Compulab, Ltd.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <spl.h>
   9 #include <i2c.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/ddr_defs.h>
  12 #include <asm/gpio.h>
  13 #include <power/pmic.h>
  14 #include <power/tps65218.h>
  15 #include "board.h"
  16
  17 const struct dpll_params dpll_mpu  = { 800,  24, 1,  -1, -1, -1, -1 };
  18 const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10,  8,  4 };
  19 const struct dpll_params dpll_per  = { 960,  24, 5,  -1, -1, -1, -1 };
  20 const struct dpll_params dpll_ddr  = { 400,  23, 1,  -1,  1, -1, -1 };
  21
  22 const struct ctrl_ioregs ioregs_ddr3 = {
  23         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
  24         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
  25         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
  26         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
  27         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
  28         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
  29         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
  30         .emif_sdram_config_ext  = 0x0143,
  31 };
  32
  33 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
  34 struct emif_regs ddr3_emif_regs = {
  35         .sdram_config                   = 0x638413B2,
  36         .ref_ctrl                       = 0x00000C30,
  37         .sdram_tim1                     = 0xEAAAD4DB,
  38         .sdram_tim2                     = 0x266B7FDA,
  39         .sdram_tim3                     = 0x107F8678,
  40         .read_idle_ctrl                 = 0x00050000,
  41         .zq_config                      = 0x50074BE4,
  42         .temp_alert_config              = 0x0,
  43         .emif_ddr_phy_ctlr_1            = 0x0E004008,
  44         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
  45         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
  46         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
  47         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
  48         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
  49         .emif_rd_wr_exec_thresh         = 0x80000405,
  50         .emif_prio_class_serv_map       = 0x80000001,
  51         .emif_connect_id_serv_1_map     = 0x80000094,
  52         .emif_connect_id_serv_2_map     = 0x00000000,
  53         .emif_cos_config                = 0x000FFFFF
  54 };
  55
  56 const u32 ext_phy_ctrl_const_base_ddr3[] = {
  57         0x00000000,
  58         0x00000044,
  59         0x00000044,
  60         0x00000046,
  61         0x00000046,
  62         0x00000000,
  63         0x00000059,
  64         0x00000077,
  65         0x00000093,
  66         0x000000A8,
  67         0x00000000,
  68         0x00000019,
  69         0x00000037,
  70         0x00000053,
  71         0x00000068,
  72         0x00000000,
  73         0x0,
  74         0x0,
  75         0x40000000,
  76         0x08102040
  77 };
  78
  79 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  80 {
  81         *regs = ext_phy_ctrl_const_base_ddr3;
  82         *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
  83 }
  84
  85 const struct dpll_params *get_dpll_ddr_params(void)
  86 {
  87         return &dpll_ddr;
  88 }
  89
  90 const struct dpll_params *get_dpll_mpu_params(void)
  91 {
  92         return &dpll_mpu;
  93 }
  94
  95 const struct dpll_params *get_dpll_core_params(void)
  96 {
  97         return &dpll_core;
  98 }
  99
 100 const struct dpll_params *get_dpll_per_params(void)
 101 {
 102         return &dpll_per;
 103 }
 104
 105 void scale_vcores(void)
 106 {
 107         set_i2c_pin_mux();
 108         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 109         if (i2c_probe(TPS65218_CHIP_PM))
 110                 return;
 111
 112         tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV);
 113         tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV);
 114 }
 115
 116 void sdram_init(void)
 117 {
 118         unsigned long ram_size;
 119
 120         config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
 121         ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 122         if (ram_size == 0x80000000 ||
 123             ram_size == 0x40000000 ||
 124             ram_size == 0x20000000)
 125                 return;
 126
 127         ddr3_emif_regs.sdram_config = 0x638453B2;
 128         config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
 129         ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 130         if (ram_size == 0x08000000)
 131                 return;
 132
 133         hang();
 134 }
 135