git.sur5r.net Git - u-boot/blob - board/esd/plu405/plu405.c

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/io.h>
  27 #include <command.h>
  28 #include <malloc.h>
  29 #include <sja1000.h>
  30
  31 #undef FPGA_DEBUG
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  36 extern void lxt971_no_sleep(void);
  37
  38 /* fpga configuration data - gzip compressed and generated by bin2c */
  39 const unsigned char fpgadata[] =
  40 {
  41 #include "fpgadata.c"
  42 };
  43
  44 /*
  45  * include common fpga code (for esd boards)
  46  */
  47 #include "../common/fpga.c"
  48
  49 int board_early_init_f(void)
  50 {
  51         /*
  52          * IRQ 0-15  405GP internally generated; active high; level sensitive
  53          * IRQ 16    405GP internally generated; active low; level sensitive
  54          * IRQ 17-24 RESERVED
  55          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  56          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  57          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  58          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  59          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  60          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  61          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  62          */
  63         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  64         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
  65         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
  66         mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
  67         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
  68         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
  69         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  70
  71         /*
  72          * EBC Configuration Register: set ready timeout to
  73          * 512 ebc-clks -> ca. 15 us
  74          */
  75         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
  76
  77         return 0;
  78 }
  79
  80 int misc_init_r(void)
  81 {
  82         unsigned char *dst;
  83         unsigned char fctr;
  84         ulong len = sizeof(fpgadata);
  85         int status;
  86         int index;
  87         int i;
  88
  89         /* adjust flash start and offset */
  90         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  91         gd->bd->bi_flashoffset = 0;
  92
  93         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
  94         if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
  95                    (uchar *)fpgadata, &len) != 0) {
  96                 printf("GUNZIP ERROR - must RESET board to recover\n");
  97                 do_reset(NULL, 0, 0, NULL);
  98         }
  99
 100         status = fpga_boot(dst, len);
 101         if (status != 0) {
 102                 printf("\nFPGA: Booting failed ");
 103                 switch (status) {
 104                 case ERROR_FPGA_PRG_INIT_LOW:
 105                         printf("(Timeout: INIT not low "
 106                                "after asserting PROGRAM*)\n");
 107                         break;
 108                 case ERROR_FPGA_PRG_INIT_HIGH:
 109                         printf("(Timeout: INIT not high "
 110                                "after deasserting PROGRAM*)\n");
 111                         break;
 112                 case ERROR_FPGA_PRG_DONE:
 113                         printf("(Timeout: DONE not high "
 114                                "after programming FPGA)\n");
 115                         break;
 116                 }
 117
 118                 /* display infos on fpgaimage */
 119                 index = 15;
 120                 for (i=0; i<4; i++) {
 121                         len = dst[index];
 122                         printf("FPGA: %s\n", &(dst[index+1]));
 123                         index += len+3;
 124                 }
 125                 putc ('\n');
 126                 /* delayed reboot */
 127                 for (i=20; i>0; i--) {
 128                         printf("Rebooting in %2d seconds \r",i);
 129                         for (index=0;index<1000;index++)
 130                                 udelay(1000);
 131                 }
 132                 putc('\n');
 133                 do_reset(NULL, 0, 0, NULL);
 134         }
 135
 136         puts("FPGA:  ");
 137
 138         /* display infos on fpgaimage */
 139         index = 15;
 140         for (i=0; i<4; i++) {
 141                 len = dst[index];
 142                 printf("%s ", &(dst[index+1]));
 143                 index += len+3;
 144         }
 145         putc('\n');
 146
 147         free(dst);
 148
 149         /*
 150          * Reset FPGA via FPGA_DATA pin
 151          */
 152         SET_FPGA(FPGA_PRG | FPGA_CLK);
 153         udelay(1000); /* wait 1ms */
 154         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 155         udelay(1000); /* wait 1ms */
 156
 157         /*
 158          * Reset external DUARTs
 159          */
 160         out_be32((void*)GPIO0_OR,
 161                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
 162         udelay(10);
 163         out_be32((void*)GPIO0_OR,
 164                  in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
 165         udelay(1000);
 166
 167         /*
 168          * Set NAND-FLASH GPIO signals to default
 169          */
 170         out_be32((void*)GPIO0_OR,
 171                  in_be32((void*)GPIO0_OR) &
 172                  ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
 173         out_be32((void*)GPIO0_OR,
 174                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 175
 176         /*
 177          * Setup EEPROM write protection
 178          */
 179         out_be32((void*)GPIO0_OR,
 180                  in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 181         out_be32((void*)GPIO0_TCR,
 182                  in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 183
 184         /*
 185          * Enable interrupts in exar duart mcr[3]
 186          */
 187         out_8((void *)DUART0_BA + 4, 0x08);
 188         out_8((void *)DUART1_BA + 4, 0x08);
 189
 190         /*
 191          * Enable auto RS485 mode in 2nd external uart
 192          */
 193         out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
 194         fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
 195         fctr |= 0x08;                       /* enable RS485 mode */
 196         out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
 197         out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
 198
 199         /*
 200          * Init magnetic couplers
 201          */
 202         if (!getenv("noinitcoupler")) {
 203                 init_coupler(CAN0_BA);
 204                 init_coupler(CAN1_BA);
 205         }
 206         return 0;
 207 }
 208
 209 /*
 210  * Check Board Identity:
 211  */
 212 int checkboard(void)
 213 {
 214         char str[64];
 215         int i = getenv_r("serial#", str, sizeof(str));
 216
 217         puts("Board: ");
 218
 219         if (i == -1)
 220                 puts("### No HW ID - assuming PLU405");
 221         else
 222                 puts(str);
 223
 224         putc('\n');
 225         return 0;
 226 }
 227
 228 #ifdef CONFIG_IDE_RESET
 229 #define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 230 void ide_set_reset(int on)
 231 {
 232         /*
 233          * Assert or deassert CompactFlash Reset Pin
 234          */
 235         if (on) {               /* assert RESET */
 236                 out_be16((void *)FPGA_CTRL,
 237                          in_be16((void *)FPGA_CTRL) &
 238                          ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 239         } else {                /* release RESET */
 240                 out_be16((void *)FPGA_CTRL,
 241                          in_be16((void *)FPGA_CTRL) |
 242                          CONFIG_SYS_FPGA_CTRL_CF_RESET);
 243         }
 244 }
 245 #endif /* CONFIG_IDE_RESET */
 246
 247 void reset_phy(void)
 248 {
 249 #ifdef CONFIG_LXT971_NO_SLEEP
 250
 251         /*
 252          * Disable sleep mode in LXT971
 253          */
 254         lxt971_no_sleep();
 255 #endif
 256 }
 257
 258 #if defined(CONFIG_SYS_EEPROM_WREN)
 259 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 260  *             <state> -1: deliver current state
 261  *                      0: disable write
 262  *                      1: enable write
 263  *  Returns:           -1: wrong device address
 264  *                      0: dis-/en- able done
 265  *                    0/1: current state if <state> was -1.
 266  */
 267 int eeprom_write_enable(unsigned dev_addr, int state)
 268 {
 269         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 270                 return -1;
 271         } else {
 272                 switch (state) {
 273                 case 1:
 274                         /* Enable write access, clear bit GPIO0. */
 275                         out_be32((void*)GPIO0_OR,
 276                                  in_be32((void*)GPIO0_OR) &
 277                                  ~CONFIG_SYS_EEPROM_WP);
 278                         state = 0;
 279                         break;
 280                 case 0:
 281                         /* Disable write access, set bit GPIO0. */
 282                         out_be32((void*)GPIO0_OR,
 283                                  in_be32((void*)GPIO0_OR) |
 284                                  CONFIG_SYS_EEPROM_WP);
 285                         state = 0;
 286                         break;
 287                 default:
 288                         /* Read current status back. */
 289                         state = ((in_be32((void*)GPIO0_OR) &
 290                                        CONFIG_SYS_EEPROM_WP) == 0);
 291                         break;
 292                 }
 293         }
 294         return state;
 295 }
 296
 297 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 298 {
 299         int query = argc == 1;
 300         int state = 0;
 301
 302         if (query) {
 303                 /* Query write access state. */
 304                 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 305                 if (state < 0) {
 306                         puts("Query of write access state failed.\n");
 307                 } else {
 308                         printf("Write access for device 0x%0x is %sabled.\n",
 309                                CONFIG_SYS_I2C_EEPROM_ADDR,
 310                                state ? "en" : "dis");
 311                         state = 0;
 312                 }
 313         } else {
 314                 if (argv[1][0] == '0') {
 315                         /* Disable write access. */
 316                         state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
 317                                                     0);
 318                 } else {
 319                         /* Enable write access. */
 320                         state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
 321                                                     1);
 322                 }
 323                 if (state < 0)
 324                         puts("Setup of write access state failed.\n");
 325         }
 326
 327         return state;
 328 }
 329
 330 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 331         "Enable / disable / query EEPROM write access",
 332         ""
 333 );
 334 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */