git.sur5r.net Git - u-boot/blob - board/exmeritus/hww1u1a/tlb.c

   1 /*
   2  * Copyright 2009-2010 eXMeritus, A Boeing Company
   3  * Copyright 2008-2009 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <asm/mmu.h>
  29
  30 struct fsl_e_tlb_entry tlb_table[] = {
  31         /* TLB 0 - for temp stack in cache */
  32         SET_TLB_ENTRY(0,        CONFIG_SYS_INIT_RAM_ADDR      +  0 * 1024,
  33                                 CONFIG_SYS_INIT_RAM_ADDR_PHYS +  0 * 1024,
  34                                 MAS3_SX|MAS3_SW|MAS3_SR, 0,
  35                                 0, 0, BOOKE_PAGESZ_4K, 0),
  36
  37         SET_TLB_ENTRY(0,        CONFIG_SYS_INIT_RAM_ADDR      +  4 * 1024,
  38                                 CONFIG_SYS_INIT_RAM_ADDR_PHYS +  4 * 1024,
  39                                 MAS3_SX|MAS3_SW|MAS3_SR, 0,
  40                                 0, 0, BOOKE_PAGESZ_4K, 0),
  41
  42         SET_TLB_ENTRY(0,        CONFIG_SYS_INIT_RAM_ADDR      +  8 * 1024,
  43                                 CONFIG_SYS_INIT_RAM_ADDR_PHYS +  8 * 1024,
  44                                 MAS3_SX|MAS3_SW|MAS3_SR, 0,
  45                                 0, 0, BOOKE_PAGESZ_4K, 0),
  46
  47         SET_TLB_ENTRY(0,        CONFIG_SYS_INIT_RAM_ADDR      + 12 * 1024,
  48                                 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  49                                 MAS3_SX|MAS3_SW|MAS3_SR, 0,
  50                                 0, 0, BOOKE_PAGESZ_4K, 0),
  51
  52         /* TLB 1 */
  53         /* *I*** - Boot page */
  54         SET_TLB_ENTRY(1,        CONFIG_BPTR_VIRT_ADDR,
  55                                 CONFIG_BPTR_VIRT_ADDR,
  56                                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57                                 0, 0, BOOKE_PAGESZ_4K, 1),
  58
  59         /* *I*G* - CCSRBAR */
  60         SET_TLB_ENTRY(1,        CONFIG_SYS_CCSRBAR,
  61                                 CONFIG_SYS_CCSRBAR_PHYS,
  62                                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  63                                 0, 1, BOOKE_PAGESZ_1M, 1),
  64
  65         /*
  66          * W**G* - FLASH (Will be *I*G* after relocation to RAM)
  67          *
  68          * This maps both SPI FLASH chips (128MByte per chip)
  69          */
  70         SET_TLB_ENTRY(1,        CONFIG_SYS_FLASH_BASE,
  71                                 CONFIG_SYS_FLASH_BASE_PHYS,
  72                                 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  73                                 0, 2, BOOKE_PAGESZ_256M, 1),
  74
  75         /*
  76          * *I*G* - PCI memory
  77          *
  78          * We have 1.5GB total PCI-E memory space to map and we want to use
  79          * the minimum possible number of TLB entries.  Since Book-E TLB
  80          * entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
  81          */
  82         SET_TLB_ENTRY(1,        CONFIG_SYS_PCIE3_MEM_VIRT,
  83                                 CONFIG_SYS_PCIE3_MEM_PHYS,
  84                                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  85                                 0, 3, BOOKE_PAGESZ_1G, 1),
  86         SET_TLB_ENTRY(1,        CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
  87                                 CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
  88                                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  89                                 0, 4, BOOKE_PAGESZ_256M, 1),
  90         SET_TLB_ENTRY(1,        CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
  91                                 CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
  92                                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  93                                 0, 5, BOOKE_PAGESZ_256M, 1),
  94
  95         /*
  96          * *I*G* - PCI I/O
  97          *
  98          * This one entry covers all 3 64k PCI-E I/O windows
  99          */
 100         SET_TLB_ENTRY(1,        CONFIG_SYS_PCIE3_IO_VIRT,
 101                                 CONFIG_SYS_PCIE3_IO_PHYS,
 102                                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 103                                 0, 6, BOOKE_PAGESZ_256K, 1),
 104 };
 105
 106 int num_tlb_entries = ARRAY_SIZE(tlb_table);