1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 DECLARE_GLOBAL_DATA_PTR;
14 puts ("Board: Freescale M5282EVB Evaluation Board\n");
20 u32 dramsize, i, dramclk;
22 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
23 for (i = 0x13; i < 0x20; i++) {
24 if (dramsize == (1 << i))
29 if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
31 dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
33 /* Initialize DRAM Control Register: DCR */
35 | MCFSDRAMC_DCR_RTIM_6
36 | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
39 /* Initialize DACR0 */
41 | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
42 | MCFSDRAMC_DACR_CASL(1)
43 | MCFSDRAMC_DACR_CBM(3)
44 | MCFSDRAMC_DACR_PS_32);
49 | ((dramsize - 1) & 0xFFFC0000)
53 /* Set IP (bit 3) in DACR */
54 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
57 /* Wait 30ns to allow banks to precharge */
58 for (i = 0; i < 5; i++) {
62 /* Write to this block to initiate precharge */
63 *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
66 /* Set RE (bit 15) in DACR */
67 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
70 /* Wait for at least 8 auto refresh cycles to occur */
71 for (i = 0; i < 2000; i++) {
75 /* Finish the configuration by issuing the IMRS. */
76 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
79 /* Write to the SDRAM Mode Register */
80 *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
82 gd->ram_size = dramsize;