git.sur5r.net Git - u-boot/blob - board/freescale/mpc8536ds/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/mmu.h>
  11
  12 struct fsl_e_tlb_entry tlb_table[] = {
  13         /* TLB 0 - for temp stack in cache */
  14         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  15                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16                       0, 0, BOOKE_PAGESZ_4K, 0),
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25                       0, 0, BOOKE_PAGESZ_4K, 0),
  26
  27         SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
  28                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  29                       0, 0, BOOKE_PAGESZ_4K, 0),
  30
  31         /* TLB 1 */
  32         /* *I*G* - CCSRBAR */
  33         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  34                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  35                       0, 0, BOOKE_PAGESZ_1M, 1),
  36
  37         /* W**G* - Flash/promjet, localbus */
  38         /* This will be changed to *I*G* after relocation to RAM. */
  39         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  40                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  41                       0, 1, BOOKE_PAGESZ_256M, 1),
  42
  43         /* *I*G* - PCI */
  44         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
  45                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  46                       0, 2, BOOKE_PAGESZ_1G, 1),
  47
  48         /* *I*G* - PCI I/O */
  49         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
  50                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  51                       0, 3, BOOKE_PAGESZ_256K, 1),
  52
  53         /* *I*G - NAND */
  54         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  55                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56                       0, 4, BOOKE_PAGESZ_1M, 1),
  57
  58 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  59         /* *I*G - L2SRAM */
  60         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  61                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  62                       0, 5, BOOKE_PAGESZ_256K, 1),
  63         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  64                       CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  65                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  66                       0, 6, BOOKE_PAGESZ_256K, 1),
  67 #endif
  68 };
  69
  70 int num_tlb_entries = ARRAY_SIZE(tlb_table);