git.sur5r.net Git - u-boot/blob - board/freescale/mpc8572ds/mpc8572ds.c

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37
  38 #include "../common/pixis.h"
  39 #include "../common/sgmii_riser.h"
  40
  41 long int fixed_sdram(void);
  42
  43 int checkboard (void)
  44 {
  45         u8 vboot;
  46         u8 *pixis_base = (u8 *)PIXIS_BASE;
  47
  48         puts ("Board: MPC8572DS ");
  49 #ifdef CONFIG_PHYS_64BIT
  50         puts ("(36-bit addrmap) ");
  51 #endif
  52         printf ("Sys ID: 0x%02x, "
  53                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  54                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  55                 in_8(pixis_base + PIXIS_PVER));
  56
  57         vboot = in_8(pixis_base + PIXIS_VBOOT);
  58         switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
  59                 case PIXIS_VBOOT_LBMAP_NOR0:
  60                         puts ("vBank: 0\n");
  61                         break;
  62                 case PIXIS_VBOOT_LBMAP_PJET:
  63                         puts ("Promjet\n");
  64                         break;
  65                 case PIXIS_VBOOT_LBMAP_NAND:
  66                         puts ("NAND\n");
  67                         break;
  68                 case PIXIS_VBOOT_LBMAP_NOR1:
  69                         puts ("vBank: 1\n");
  70                         break;
  71         }
  72
  73         return 0;
  74 }
  75
  76 phys_size_t initdram(int board_type)
  77 {
  78         phys_size_t dram_size = 0;
  79
  80         puts("Initializing....");
  81
  82 #ifdef CONFIG_SPD_EEPROM
  83         dram_size = fsl_ddr_sdram();
  84 #else
  85         dram_size = fixed_sdram();
  86 #endif
  87         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  88         dram_size *= 0x100000;
  89
  90         puts("    DDR: ");
  91         return dram_size;
  92 }
  93
  94 #if !defined(CONFIG_SPD_EEPROM)
  95 /*
  96  * Fixed sdram init -- doesn't use serial presence detect.
  97  */
  98
  99 phys_size_t fixed_sdram (void)
 100 {
 101         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 102         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 103         uint d_init;
 104
 105         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 106         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 107
 108         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 109         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 110         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 111         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 112         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 113         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 114         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 115         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 116         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 117         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 118
 119 #if defined (CONFIG_DDR_ECC)
 120         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 121         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 122         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 123 #endif
 124         asm("sync;isync");
 125
 126         udelay(500);
 127
 128         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 129
 130 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 131         d_init = 1;
 132         debug("DDR - 1st controller: memory initializing\n");
 133         /*
 134          * Poll until memory is initialized.
 135          * 512 Meg at 400 might hit this 200 times or so.
 136          */
 137         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 138                 udelay(1000);
 139         }
 140         debug("DDR: memory initialized\n\n");
 141         asm("sync; isync");
 142         udelay(500);
 143 #endif
 144
 145         return 512 * 1024 * 1024;
 146 }
 147
 148 #endif
 149
 150 #ifdef CONFIG_PCIE1
 151 static struct pci_controller pcie1_hose;
 152 #endif
 153
 154 #ifdef CONFIG_PCIE2
 155 static struct pci_controller pcie2_hose;
 156 #endif
 157
 158 #ifdef CONFIG_PCIE3
 159 static struct pci_controller pcie3_hose;
 160 #endif
 161
 162 int first_free_busno=0;
 163 #ifdef CONFIG_PCI
 164 void pci_init_board(void)
 165 {
 166         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 167         uint devdisr = gur->devdisr;
 168         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 169         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 170
 171         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 172                         devdisr, io_sel, host_agent);
 173
 174         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 175                 printf ("    eTSEC1 is in sgmii mode.\n");
 176         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 177                 printf ("    eTSEC2 is in sgmii mode.\n");
 178         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 179                 printf ("    eTSEC3 is in sgmii mode.\n");
 180         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 181                 printf ("    eTSEC4 is in sgmii mode.\n");
 182
 183
 184 #ifdef CONFIG_PCIE3
 185         {
 186                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 187                 struct pci_controller *hose = &pcie3_hose;
 188                 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 189                         (host_agent == 5) || (host_agent == 6);
 190                 int pcie_configured  = (io_sel == 0x7);
 191                 struct pci_region *r = hose->regions;
 192                 u32 temp32;
 193
 194                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 195                         printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 196                                         pcie_ep ? "End Point" : "Root Complex",
 197                                         (uint)pci);
 198                         if (pci->pme_msg_det) {
 199                                 pci->pme_msg_det = 0xffffffff;
 200                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 201                         }
 202                         printf ("\n");
 203
 204                         /* inbound */
 205                         r += fsl_pci_setup_inbound_windows(r);
 206
 207                         /* outbound memory */
 208                         pci_set_region(r++,
 209                                         CONFIG_SYS_PCIE3_MEM_BUS,
 210                                         CONFIG_SYS_PCIE3_MEM_PHYS,
 211                                         CONFIG_SYS_PCIE3_MEM_SIZE,
 212                                         PCI_REGION_MEM);
 213
 214                         /* outbound io */
 215                         pci_set_region(r++,
 216                                         CONFIG_SYS_PCIE3_IO_BUS,
 217                                         CONFIG_SYS_PCIE3_IO_PHYS,
 218                                         CONFIG_SYS_PCIE3_IO_SIZE,
 219                                         PCI_REGION_IO);
 220
 221                         hose->region_count = r - hose->regions;
 222                         hose->first_busno=first_free_busno;
 223
 224                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 225
 226                         first_free_busno=hose->last_busno+1;
 227                         printf ("    PCIE3 on bus %02x - %02x\n",
 228                                         hose->first_busno,hose->last_busno);
 229
 230                         /*
 231                          * Activate ULI1575 legacy chip by performing a fake
 232                          * memory access.  Needed to make ULI RTC work.
 233                          * Device 1d has the first on-board memory BAR.
 234                          */
 235
 236                         pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 237                                         PCI_BASE_ADDRESS_1, &temp32);
 238                         if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 239                                 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 240                                                                 temp32, 4, 0);
 241                                 debug(" uli1572 read to %p\n", p);
 242                                 in_be32(p);
 243                         }
 244                 } else {
 245                         printf ("    PCIE3: disabled\n");
 246                 }
 247
 248         }
 249 #else
 250         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 251 #endif
 252
 253 #ifdef CONFIG_PCIE2
 254         {
 255                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 256                 struct pci_controller *hose = &pcie2_hose;
 257                 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 258                         (host_agent == 6) || (host_agent == 0);
 259                 int pcie_configured  = (io_sel == 0x3) || (io_sel == 0x7);
 260                 struct pci_region *r = hose->regions;
 261
 262                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 263                         printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 264                                         pcie_ep ? "End Point" : "Root Complex",
 265                                         (uint)pci);
 266                         if (pci->pme_msg_det) {
 267                                 pci->pme_msg_det = 0xffffffff;
 268                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 269                         }
 270                         printf ("\n");
 271
 272                         /* inbound */
 273                         r += fsl_pci_setup_inbound_windows(r);
 274
 275                         /* outbound memory */
 276                         pci_set_region(r++,
 277                                         CONFIG_SYS_PCIE2_MEM_BUS,
 278                                         CONFIG_SYS_PCIE2_MEM_PHYS,
 279                                         CONFIG_SYS_PCIE2_MEM_SIZE,
 280                                         PCI_REGION_MEM);
 281
 282                         /* outbound io */
 283                         pci_set_region(r++,
 284                                         CONFIG_SYS_PCIE2_IO_BUS,
 285                                         CONFIG_SYS_PCIE2_IO_PHYS,
 286                                         CONFIG_SYS_PCIE2_IO_SIZE,
 287                                         PCI_REGION_IO);
 288
 289                         hose->region_count = r - hose->regions;
 290                         hose->first_busno=first_free_busno;
 291
 292                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 293                         first_free_busno=hose->last_busno+1;
 294                         printf ("    PCIE2 on bus %02x - %02x\n",
 295                                         hose->first_busno,hose->last_busno);
 296
 297                 } else {
 298                         printf ("    PCIE2: disabled\n");
 299                 }
 300
 301         }
 302 #else
 303         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 304 #endif
 305 #ifdef CONFIG_PCIE1
 306         {
 307                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 308                 struct pci_controller *hose = &pcie1_hose;
 309                 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 310                         (host_agent == 5);
 311                 int pcie_configured  = (io_sel == 0x2) || (io_sel == 0x3) ||
 312                                         (io_sel == 0x7) || (io_sel == 0xb) ||
 313                                         (io_sel == 0xc) || (io_sel == 0xf);
 314                 struct pci_region *r = hose->regions;
 315
 316                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 317                         printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
 318                                         pcie_ep ? "End Point" : "Root Complex",
 319                                         (uint)pci);
 320                         if (pci->pme_msg_det) {
 321                                 pci->pme_msg_det = 0xffffffff;
 322                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 323                         }
 324                         printf ("\n");
 325
 326                         /* inbound */
 327                         r += fsl_pci_setup_inbound_windows(r);
 328
 329                         /* outbound memory */
 330                         pci_set_region(r++,
 331                                         CONFIG_SYS_PCIE1_MEM_BUS,
 332                                         CONFIG_SYS_PCIE1_MEM_PHYS,
 333                                         CONFIG_SYS_PCIE1_MEM_SIZE,
 334                                         PCI_REGION_MEM);
 335
 336                         /* outbound io */
 337                         pci_set_region(r++,
 338                                         CONFIG_SYS_PCIE1_IO_BUS,
 339                                         CONFIG_SYS_PCIE1_IO_PHYS,
 340                                         CONFIG_SYS_PCIE1_IO_SIZE,
 341                                         PCI_REGION_IO);
 342
 343                         hose->region_count = r - hose->regions;
 344                         hose->first_busno=first_free_busno;
 345
 346                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 347
 348                         first_free_busno=hose->last_busno+1;
 349                         printf("    PCIE1 on bus %02x - %02x\n",
 350                                         hose->first_busno,hose->last_busno);
 351
 352                 } else {
 353                         printf ("    PCIE1: disabled\n");
 354                 }
 355
 356         }
 357 #else
 358         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 359 #endif
 360 }
 361 #endif
 362
 363 int board_early_init_r(void)
 364 {
 365         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 366         const u8 flash_esel = 2;
 367
 368         /*
 369          * Remap Boot flash + PROMJET region to caching-inhibited
 370          * so that flash can be erased properly.
 371          */
 372
 373         /* Flush d-cache and invalidate i-cache of any FLASH data */
 374         flush_dcache();
 375         invalidate_icache();
 376
 377         /* invalidate existing TLB entry for flash + promjet */
 378         disable_tlb(flash_esel);
 379
 380         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 381                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 382                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 383
 384         return 0;
 385 }
 386
 387 #ifdef CONFIG_GET_CLK_FROM_ICS307
 388 /* decode S[0-2] to Output Divider (OD) */
 389 static unsigned char ics307_S_to_OD[] = {
 390         10, 2, 8, 4, 5, 7, 3, 6
 391 };
 392
 393 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 394  * the control bytes being programmed into it. */
 395 /* XXX: This function should probably go into a common library */
 396 static unsigned long
 397 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 398 {
 399         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 400         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 401         unsigned long RDW = cw2 & 0x7F;
 402         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 403         unsigned long freq;
 404
 405         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 406
 407         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 408          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 409          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 410          *
 411          * R6:R0 = Reference Divider Word (RDW)
 412          * V8:V0 = VCO Divider Word (VDW)
 413          * S2:S0 = Output Divider Select (OD)
 414          * F1:F0 = Function of CLK2 Output
 415          * TTL = duty cycle
 416          * C1:C0 = internal load capacitance for cyrstal
 417          */
 418
 419         /* Adding 1 to get a "nicely" rounded number, but this needs
 420          * more tweaking to get a "properly" rounded number. */
 421
 422         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 423
 424         debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 425                         freq);
 426         return freq;
 427 }
 428
 429 unsigned long get_board_sys_clk(ulong dummy)
 430 {
 431         u8 *pixis_base = (u8 *)PIXIS_BASE;
 432
 433         return ics307_clk_freq (
 434                         in_8(pixis_base + PIXIS_VSYSCLK0),
 435                         in_8(pixis_base + PIXIS_VSYSCLK1),
 436                         in_8(pixis_base + PIXIS_VSYSCLK2)
 437                         );
 438 }
 439
 440 unsigned long get_board_ddr_clk(ulong dummy)
 441 {
 442         u8 *pixis_base = (u8 *)PIXIS_BASE;
 443
 444         return ics307_clk_freq (
 445                         in_8(pixis_base + PIXIS_VDDRCLK0),
 446                         in_8(pixis_base + PIXIS_VDDRCLK1),
 447                         in_8(pixis_base + PIXIS_VDDRCLK2)
 448                         );
 449 }
 450 #else
 451 unsigned long get_board_sys_clk(ulong dummy)
 452 {
 453         u8 i;
 454         ulong val = 0;
 455         u8 *pixis_base = (u8 *)PIXIS_BASE;
 456
 457         i = in_8(pixis_base + PIXIS_SPD);
 458         i &= 0x07;
 459
 460         switch (i) {
 461                 case 0:
 462                         val = 33333333;
 463                         break;
 464                 case 1:
 465                         val = 40000000;
 466                         break;
 467                 case 2:
 468                         val = 50000000;
 469                         break;
 470                 case 3:
 471                         val = 66666666;
 472                         break;
 473                 case 4:
 474                         val = 83333333;
 475                         break;
 476                 case 5:
 477                         val = 100000000;
 478                         break;
 479                 case 6:
 480                         val = 133333333;
 481                         break;
 482                 case 7:
 483                         val = 166666666;
 484                         break;
 485         }
 486
 487         return val;
 488 }
 489
 490 unsigned long get_board_ddr_clk(ulong dummy)
 491 {
 492         u8 i;
 493         ulong val = 0;
 494         u8 *pixis_base = (u8 *)PIXIS_BASE;
 495
 496         i = in_8(pixis_base + PIXIS_SPD);
 497         i &= 0x38;
 498         i >>= 3;
 499
 500         switch (i) {
 501                 case 0:
 502                         val = 33333333;
 503                         break;
 504                 case 1:
 505                         val = 40000000;
 506                         break;
 507                 case 2:
 508                         val = 50000000;
 509                         break;
 510                 case 3:
 511                         val = 66666666;
 512                         break;
 513                 case 4:
 514                         val = 83333333;
 515                         break;
 516                 case 5:
 517                         val = 100000000;
 518                         break;
 519                 case 6:
 520                         val = 133333333;
 521                         break;
 522                 case 7:
 523                         val = 166666666;
 524                         break;
 525         }
 526         return val;
 527 }
 528 #endif
 529
 530 #ifdef CONFIG_TSEC_ENET
 531 int board_eth_init(bd_t *bis)
 532 {
 533         struct tsec_info_struct tsec_info[4];
 534         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 535         int num = 0;
 536
 537 #ifdef CONFIG_TSEC1
 538         SET_STD_TSEC_INFO(tsec_info[num], 1);
 539         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 540                 tsec_info[num].flags |= TSEC_SGMII;
 541         num++;
 542 #endif
 543 #ifdef CONFIG_TSEC2
 544         SET_STD_TSEC_INFO(tsec_info[num], 2);
 545         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 546                 tsec_info[num].flags |= TSEC_SGMII;
 547         num++;
 548 #endif
 549 #ifdef CONFIG_TSEC3
 550         SET_STD_TSEC_INFO(tsec_info[num], 3);
 551         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 552                 tsec_info[num].flags |= TSEC_SGMII;
 553         num++;
 554 #endif
 555 #ifdef CONFIG_TSEC4
 556         SET_STD_TSEC_INFO(tsec_info[num], 4);
 557         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 558                 tsec_info[num].flags |= TSEC_SGMII;
 559         num++;
 560 #endif
 561
 562         if (!num) {
 563                 printf("No TSECs initialized\n");
 564
 565                 return 0;
 566         }
 567
 568 #ifdef CONFIG_FSL_SGMII_RISER
 569         fsl_sgmii_riser_init(tsec_info, num);
 570 #endif
 571
 572         tsec_eth_init(bis, tsec_info, num);
 573
 574         return 0;
 575 }
 576 #endif
 577
 578 #if defined(CONFIG_OF_BOARD_SETUP)
 579 void ft_board_setup(void *blob, bd_t *bd)
 580 {
 581         phys_addr_t base;
 582         phys_size_t size;
 583
 584         ft_cpu_setup(blob, bd);
 585
 586         base = getenv_bootm_low();
 587         size = getenv_bootm_size();
 588
 589         fdt_fixup_memory(blob, (u64)base, (u64)size);
 590
 591 #ifdef CONFIG_PCIE3
 592         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 593 #endif
 594 #ifdef CONFIG_PCIE2
 595         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 596 #endif
 597 #ifdef CONFIG_PCIE1
 598         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 599 #endif
 600 #ifdef CONFIG_FSL_SGMII_RISER
 601         fsl_sgmii_riser_fdt_fixup(blob);
 602 #endif
 603 }
 604 #endif
 605
 606 #ifdef CONFIG_MP
 607 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 608
 609 void board_lmb_reserve(struct lmb *lmb)
 610 {
 611         cpu_mp_lmb_reserve(lmb);
 612 }
 613 #endif