git.sur5r.net Git - u-boot/blob - board/freescale/mx6slevk/mx6slevk.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-ddr.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/mach-imx/spi.h>
  20 #include <asm/io.h>
  21 #include <linux/sizes.h>
  22 #include <common.h>
  23 #include <fsl_esdhc.h>
  24 #include <i2c.h>
  25 #include <mmc.h>
  26 #include <netdev.h>
  27 #include <power/pmic.h>
  28 #include <power/pfuze100_pmic.h>
  29 #include "../common/pfuze.h"
  30 #include <usb.h>
  31 #include <usb/ehci-ci.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  36         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |                    \
  40         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  44         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  45         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  46
  47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  48                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  49
  50 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  51                         PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
  52                         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |       \
  53                         PAD_CTL_SRE_FAST)
  54
  55 #define ETH_PHY_POWER   IMX_GPIO_NR(4, 21)
  56
  57 int dram_init(void)
  58 {
  59         gd->ram_size = imx_ddr_size();
  60
  61         return 0;
  62 }
  63
  64 static iomux_v3_cfg_t const uart1_pads[] = {
  65         MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  66         MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  67 };
  68
  69 #ifdef CONFIG_SPL_BUILD
  70 static iomux_v3_cfg_t const usdhc1_pads[] = {
  71         /* 8 bit SD */
  72         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78         MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79         MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80         MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81         MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82
  83         /*CD pin*/
  84         MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  85 };
  86
  87 static iomux_v3_cfg_t const usdhc2_pads[] = {
  88         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94
  95         /*CD pin*/
  96         MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
  97 };
  98
  99 static iomux_v3_cfg_t const usdhc3_pads[] = {
 100         MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106
 107         /*CD pin*/
 108         MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 109 };
 110 #endif
 111
 112 static iomux_v3_cfg_t const fec_pads[] = {
 113         MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 114         MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122         MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 123         MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 124 };
 125
 126 #ifdef CONFIG_MXC_SPI
 127 static iomux_v3_cfg_t ecspi1_pads[] = {
 128         MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 129         MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 130         MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 131         MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
 132 };
 133
 134 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 135 {
 136         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
 137 }
 138
 139 static void setup_spi(void)
 140 {
 141         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 142 }
 143 #endif
 144
 145 static void setup_iomux_uart(void)
 146 {
 147         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 148 }
 149
 150 static void setup_iomux_fec(void)
 151 {
 152         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 153
 154         /* Power up LAN8720 PHY */
 155         gpio_request(ETH_PHY_POWER, "eth_pwr");
 156         gpio_direction_output(ETH_PHY_POWER , 1);
 157         udelay(15000);
 158 }
 159
 160 int board_mmc_get_env_dev(int devno)
 161 {
 162         return devno;
 163 }
 164
 165 #ifdef CONFIG_DM_PMIC_PFUZE100
 166 int power_init_board(void)
 167 {
 168         struct udevice *dev;
 169         int ret;
 170         u32 dev_id, rev_id, i;
 171         u32 switch_num = 6;
 172         u32 offset = PFUZE100_SW1CMODE;
 173
 174         ret = pmic_get("pfuze100", &dev);
 175         if (ret == -ENODEV)
 176                 return 0;
 177
 178         if (ret != 0)
 179                 return ret;
 180
 181         dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
 182         rev_id = pmic_reg_read(dev, PFUZE100_REVID);
 183         printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 184
 185         /* set SW1AB staby volatage 0.975V */
 186         pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
 187
 188         /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 189         pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
 190
 191         /* set SW1C staby volatage 0.975V */
 192         pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
 193
 194         /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 195         pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
 196
 197         /* Init mode to APS_PFM */
 198         pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
 199
 200         for (i = 0; i < switch_num - 1; i++)
 201                 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
 202
 203         return 0;
 204 }
 205 #endif
 206
 207 #ifdef CONFIG_FEC_MXC
 208 int board_eth_init(bd_t *bis)
 209 {
 210         setup_iomux_fec();
 211
 212         return cpu_eth_init(bis);
 213 }
 214
 215 static int setup_fec(void)
 216 {
 217         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 218
 219         /* clear gpr1[14], gpr1[18:17] to select anatop clock */
 220         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 221
 222         return enable_fec_anatop_clock(0, ENET_50MHZ);
 223 }
 224 #endif
 225
 226 #ifdef CONFIG_USB_EHCI_MX6
 227 #define USB_OTHERREGS_OFFSET    0x800
 228 #define UCTRL_PWR_POL           (1 << 9)
 229
 230 static iomux_v3_cfg_t const usb_otg_pads[] = {
 231         /* OTG1 */
 232         MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 233         MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
 234         /* OTG2 */
 235         MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 236 };
 237
 238 static void setup_usb(void)
 239 {
 240         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 241                                          ARRAY_SIZE(usb_otg_pads));
 242 }
 243
 244 int board_usb_phy_mode(int port)
 245 {
 246         if (port == 1)
 247                 return USB_INIT_HOST;
 248         else
 249                 return usb_phy_mode(port);
 250 }
 251
 252 int board_ehci_hcd_init(int port)
 253 {
 254         u32 *usbnc_usb_ctrl;
 255
 256         if (port > 1)
 257                 return -EINVAL;
 258
 259         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 260                                  port * 4);
 261
 262         /* Set Power polarity */
 263         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 264
 265         return 0;
 266 }
 267 #endif
 268
 269 int board_early_init_f(void)
 270 {
 271         setup_iomux_uart();
 272
 273         return 0;
 274 }
 275
 276 int board_init(void)
 277 {
 278         /* address of boot parameters */
 279         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 280
 281 #ifdef CONFIG_MXC_SPI
 282         gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
 283         setup_spi();
 284 #endif
 285
 286 #ifdef  CONFIG_FEC_MXC
 287         setup_fec();
 288 #endif
 289
 290 #ifdef CONFIG_USB_EHCI_MX6
 291         setup_usb();
 292 #endif
 293
 294         return 0;
 295 }
 296
 297 int checkboard(void)
 298 {
 299         puts("Board: MX6SLEVK\n");
 300
 301         return 0;
 302 }
 303
 304 #ifdef CONFIG_SPL_BUILD
 305 #include <spl.h>
 306 #include <libfdt.h>
 307
 308 #define USDHC1_CD_GPIO  IMX_GPIO_NR(4, 7)
 309 #define USDHC2_CD_GPIO  IMX_GPIO_NR(5, 0)
 310 #define USDHC3_CD_GPIO  IMX_GPIO_NR(3, 22)
 311
 312 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 313         {USDHC1_BASE_ADDR},
 314         {USDHC2_BASE_ADDR, 0, 4},
 315         {USDHC3_BASE_ADDR, 0, 4},
 316 };
 317
 318 int board_mmc_getcd(struct mmc *mmc)
 319 {
 320         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 321         int ret = 0;
 322
 323         switch (cfg->esdhc_base) {
 324         case USDHC1_BASE_ADDR:
 325                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 326                 break;
 327         case USDHC2_BASE_ADDR:
 328                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 329                 break;
 330         case USDHC3_BASE_ADDR:
 331                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 332                 break;
 333         }
 334
 335         return ret;
 336 }
 337
 338 int board_mmc_init(bd_t *bis)
 339 {
 340         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 341         u32 val;
 342         u32 port;
 343
 344         val = readl(&src_regs->sbmr1);
 345
 346         /* Boot from USDHC */
 347         port = (val >> 11) & 0x3;
 348         switch (port) {
 349         case 0:
 350                 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 351                                                  ARRAY_SIZE(usdhc1_pads));
 352                 gpio_direction_input(USDHC1_CD_GPIO);
 353                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 354                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 355                 break;
 356         case 1:
 357                 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 358                                                  ARRAY_SIZE(usdhc2_pads));
 359                 gpio_direction_input(USDHC2_CD_GPIO);
 360                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 361                 usdhc_cfg[0].max_bus_width = 4;
 362                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 363                 break;
 364         case 2:
 365                 imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
 366                                                  ARRAY_SIZE(usdhc3_pads));
 367                 gpio_direction_input(USDHC3_CD_GPIO);
 368                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 369                 usdhc_cfg[0].max_bus_width = 4;
 370                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 371                 break;
 372         }
 373
 374         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 375         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 376 }
 377
 378 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
 379         .dram_sdqs0 = 0x00003030,
 380         .dram_sdqs1 = 0x00003030,
 381         .dram_sdqs2 = 0x00003030,
 382         .dram_sdqs3 = 0x00003030,
 383         .dram_dqm0 = 0x00000030,
 384         .dram_dqm1 = 0x00000030,
 385         .dram_dqm2 = 0x00000030,
 386         .dram_dqm3 = 0x00000030,
 387         .dram_cas  = 0x00000030,
 388         .dram_ras  = 0x00000030,
 389         .dram_sdclk_0 = 0x00000028,
 390         .dram_reset = 0x00000030,
 391         .dram_sdba2 = 0x00000000,
 392         .dram_odt0 = 0x00000008,
 393         .dram_odt1 = 0x00000008,
 394 };
 395
 396 const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
 397         .grp_b0ds = 0x00000030,
 398         .grp_b1ds = 0x00000030,
 399         .grp_b2ds = 0x00000030,
 400         .grp_b3ds = 0x00000030,
 401         .grp_addds = 0x00000030,
 402         .grp_ctlds = 0x00000030,
 403         .grp_ddrmode_ctl = 0x00020000,
 404         .grp_ddrpke = 0x00000000,
 405         .grp_ddrmode = 0x00020000,
 406         .grp_ddr_type = 0x00080000,
 407 };
 408
 409 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 410         .p0_mpdgctrl0 =  0x20000000,
 411         .p0_mpdgctrl1 =  0x00000000,
 412         .p0_mprddlctl =  0x4241444a,
 413         .p0_mpwrdlctl =  0x3030312b,
 414         .mpzqlp2ctl = 0x1b4700c7,
 415 };
 416
 417 static struct mx6_lpddr2_cfg mem_ddr = {
 418         .mem_speed = 800,
 419         .density = 4,
 420         .width = 32,
 421         .banks = 8,
 422         .rowaddr = 14,
 423         .coladdr = 10,
 424         .trcd_lp = 2000,
 425         .trppb_lp = 2000,
 426         .trpab_lp = 2250,
 427         .trasmin = 4200,
 428 };
 429
 430 static void ccgr_init(void)
 431 {
 432         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 433
 434         writel(0xFFFFFFFF, &ccm->CCGR0);
 435         writel(0xFFFFFFFF, &ccm->CCGR1);
 436         writel(0xFFFFFFFF, &ccm->CCGR2);
 437         writel(0xFFFFFFFF, &ccm->CCGR3);
 438         writel(0xFFFFFFFF, &ccm->CCGR4);
 439         writel(0xFFFFFFFF, &ccm->CCGR5);
 440         writel(0xFFFFFFFF, &ccm->CCGR6);
 441
 442         writel(0x00260324, &ccm->cbcmr);
 443 }
 444
 445 static void spl_dram_init(void)
 446 {
 447         struct mx6_ddr_sysinfo sysinfo = {
 448                 .dsize = mem_ddr.width / 32,
 449                 .cs_density = 20,
 450                 .ncs = 2,
 451                 .cs1_mirror = 0,
 452                 .walat = 0,
 453                 .ralat = 2,
 454                 .mif3_mode = 3,
 455                 .bi_on = 1,
 456                 .rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
 457                 .rtt_nom = 0,
 458                 .sde_to_rst = 0,    /* LPDDR2 does not need this field */
 459                 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 460                 .ddr_type = DDR_TYPE_LPDDR2,
 461                 .refsel = 0,    /* Refresh cycles at 64KHz */
 462                 .refr = 3,      /* 4 refresh commands per refresh cycle */
 463         };
 464         mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 465         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 466 }
 467
 468 void board_init_f(ulong dummy)
 469 {
 470         /* setup AIPS and disable watchdog */
 471         arch_cpu_init();
 472
 473         ccgr_init();
 474
 475         /* iomux and setup of i2c */
 476         board_early_init_f();
 477
 478         /* setup GP timer */
 479         timer_init();
 480
 481         /* UART clocks enabled and gd valid - init serial console */
 482         preloader_console_init();
 483
 484         /* DDR initialization */
 485         spl_dram_init();
 486
 487         /* Clear the BSS. */
 488         memset(__bss_start, 0, __bss_end - __bss_start);
 489
 490         /* load/boot image from boot device */
 491         board_init_r(NULL, 0);
 492 }
 493 #endif