git.sur5r.net Git - u-boot/blob - board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/sata.h>
  19 #include <asm/mach-imx/spi.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/io.h>
  22 #include <asm/setup.h>
  23 #include <dm.h>
  24 #include <dm/platform_data/serial_mxc.h>
  25 #include <environment.h>
  26 #include <hwconfig.h>
  27 #include <i2c.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc.h>
  30 #include <jffs2/load_kernel.h>
  31 #include <linux/ctype.h>
  32 #include <miiphy.h>
  33 #include <mtd_node.h>
  34 #include <netdev.h>
  35 #include <pci.h>
  36 #include <power/pmic.h>
  37 #include <power/ltc3676_pmic.h>
  38 #include <power/pfuze100_pmic.h>
  39 #include <fdt_support.h>
  40 #include <jffs2/load_kernel.h>
  41 #include <spi_flash.h>
  42
  43 #include "gsc.h"
  44 #include "common.h"
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48
  49 /*
  50  * EEPROM board info struct populated by read_eeprom so that we only have to
  51  * read it once.
  52  */
  53 struct ventana_board_info ventana_info;
  54
  55 static int board_type;
  56
  57 /* ENET */
  58 static iomux_v3_cfg_t const enet_pads[] = {
  59         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  67                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  69                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  76                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         /* PHY nRST */
  78         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  79 };
  80
  81 #ifdef CONFIG_CMD_NAND
  82 static iomux_v3_cfg_t const nfc_pads[] = {
  83         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98 };
  99
 100 static void setup_gpmi_nand(void)
 101 {
 102         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 103
 104         /* config gpmi nand iomux */
 105         SETUP_IOMUX_PADS(nfc_pads);
 106
 107         /* config gpmi and bch clock to 100 MHz */
 108         clrsetbits_le32(&mxc_ccm->cs2cdr,
 109                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 110                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 111                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 112                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 113                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 114                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 115
 116         /* enable gpmi and bch clock gating */
 117         setbits_le32(&mxc_ccm->CCGR4,
 118                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 119                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 120                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 121                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 122                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 123
 124         /* enable apbh clock gating */
 125         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 126 }
 127 #endif
 128
 129 static void setup_iomux_enet(int gpio)
 130 {
 131         SETUP_IOMUX_PADS(enet_pads);
 132
 133         /* toggle PHY_RST# */
 134         gpio_request(gpio, "phy_rst#");
 135         gpio_direction_output(gpio, 0);
 136         mdelay(10);
 137         gpio_set_value(gpio, 1);
 138         mdelay(100);
 139 }
 140
 141 #ifdef CONFIG_USB_EHCI_MX6
 142 static iomux_v3_cfg_t const usb_pads[] = {
 143         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 144         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 145         /* OTG PWR */
 146         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 147 };
 148
 149 int board_ehci_hcd_init(int port)
 150 {
 151         int gpio;
 152
 153         SETUP_IOMUX_PADS(usb_pads);
 154
 155         /* Reset USB HUB */
 156         switch (board_type) {
 157         case GW53xx:
 158         case GW552x:
 159                 gpio = (IMX_GPIO_NR(1, 9));
 160                 break;
 161         case GW54proto:
 162         case GW54xx:
 163                 gpio = (IMX_GPIO_NR(1, 16));
 164                 break;
 165         default:
 166                 return 0;
 167         }
 168
 169         /* request and toggle hub rst */
 170         gpio_request(gpio, "usb_hub_rst#");
 171         gpio_direction_output(gpio, 0);
 172         mdelay(2);
 173         gpio_set_value(gpio, 1);
 174
 175         return 0;
 176 }
 177
 178 int board_ehci_power(int port, int on)
 179 {
 180         /* enable OTG VBUS */
 181         if (!port && board_type < GW_UNKNOWN) {
 182                 if (gpio_cfg[board_type].otgpwr_en)
 183                         gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
 184         }
 185         return 0;
 186 }
 187 #endif /* CONFIG_USB_EHCI_MX6 */
 188
 189 #ifdef CONFIG_MXC_SPI
 190 iomux_v3_cfg_t const ecspi1_pads[] = {
 191         /* SS1 */
 192         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 193         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 194         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 195         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 196 };
 197
 198 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 199 {
 200         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 201 }
 202
 203 static void setup_spi(void)
 204 {
 205         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 206         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 207         SETUP_IOMUX_PADS(ecspi1_pads);
 208 }
 209 #endif
 210
 211 /* configure eth0 PHY board-specific LED behavior */
 212 int board_phy_config(struct phy_device *phydev)
 213 {
 214         unsigned short val;
 215
 216         /* Marvel 88E1510 */
 217         if (phydev->phy_id == 0x1410dd1) {
 218                 /*
 219                  * Page 3, Register 16: LED[2:0] Function Control Register
 220                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 221                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 222                  */
 223                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 224                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 225                 val &= 0xff00;
 226                 val |= 0x0017;
 227                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 228                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 229         }
 230
 231         /* TI DP83867 */
 232         else if (phydev->phy_id == 0x2000a231) {
 233                 /* configure register 0x170 for ref CLKOUT */
 234                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
 235                 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
 236                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
 237                 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
 238                 val &= ~0x1f00;
 239                 val |= 0x0b00; /* chD tx clock*/
 240                 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
 241         }
 242
 243         if (phydev->drv->config)
 244                 phydev->drv->config(phydev);
 245
 246         return 0;
 247 }
 248
 249 #ifdef CONFIG_MV88E61XX_SWITCH
 250 int mv88e61xx_hw_reset(struct phy_device *phydev)
 251 {
 252         struct mii_dev *bus = phydev->bus;
 253
 254         /* GPIO[0] output, CLK125 */
 255         debug("enabling RGMII_REFCLK\n");
 256         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 257                    0x1a /*MV_SCRATCH_MISC*/,
 258                    (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
 259         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 260                    0x1a /*MV_SCRATCH_MISC*/,
 261                    (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
 262
 263         /* RGMII delay - Physical Control register bit[15:14] */
 264         debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
 265         /* forced 1000mbps full-duplex link */
 266         bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
 267         phydev->autoneg = AUTONEG_DISABLE;
 268         phydev->speed = SPEED_1000;
 269         phydev->duplex = DUPLEX_FULL;
 270
 271         /* LED configuration: 7:4-green (8=Activity)  3:0 amber (9=10Link) */
 272         bus->write(bus, 0x10, 0, 0x16, 0x8089);
 273         bus->write(bus, 0x11, 0, 0x16, 0x8089);
 274         bus->write(bus, 0x12, 0, 0x16, 0x8089);
 275         bus->write(bus, 0x13, 0, 0x16, 0x8089);
 276
 277         return 0;
 278 }
 279 #endif // CONFIG_MV88E61XX_SWITCH
 280
 281 int board_eth_init(bd_t *bis)
 282 {
 283 #ifdef CONFIG_FEC_MXC
 284         struct ventana_board_info *info = &ventana_info;
 285
 286         if (test_bit(EECONFIG_ETH0, info->config)) {
 287                 setup_iomux_enet(GP_PHY_RST);
 288                 cpu_eth_init(bis);
 289         }
 290 #endif
 291
 292 #ifdef CONFIG_E1000
 293         e1000_initialize(bis);
 294 #endif
 295
 296 #ifdef CONFIG_CI_UDC
 297         /* For otg ethernet*/
 298         usb_eth_initialize(bis);
 299 #endif
 300
 301         /* default to the first detected enet dev */
 302         if (!env_get("ethprime")) {
 303                 struct eth_device *dev = eth_get_dev_by_index(0);
 304                 if (dev) {
 305                         env_set("ethprime", dev->name);
 306                         printf("set ethprime to %s\n", env_get("ethprime"));
 307                 }
 308         }
 309
 310         return 0;
 311 }
 312
 313 #if defined(CONFIG_VIDEO_IPUV3)
 314
 315 static void enable_hdmi(struct display_info_t const *dev)
 316 {
 317         imx_enable_hdmi_phy();
 318 }
 319
 320 static int detect_i2c(struct display_info_t const *dev)
 321 {
 322         return i2c_set_bus_num(dev->bus) == 0 &&
 323                 i2c_probe(dev->addr) == 0;
 324 }
 325
 326 static void enable_lvds(struct display_info_t const *dev)
 327 {
 328         struct iomuxc *iomux = (struct iomuxc *)
 329                                 IOMUXC_BASE_ADDR;
 330
 331         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 332         u32 reg = readl(&iomux->gpr[2]);
 333         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 334         writel(reg, &iomux->gpr[2]);
 335
 336         /* Enable Backlight */
 337         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 338         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 339         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 340         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 341         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 342 }
 343
 344 struct display_info_t const displays[] = {{
 345         /* HDMI Output */
 346         .bus    = -1,
 347         .addr   = 0,
 348         .pixfmt = IPU_PIX_FMT_RGB24,
 349         .detect = detect_hdmi,
 350         .enable = enable_hdmi,
 351         .mode   = {
 352                 .name           = "HDMI",
 353                 .refresh        = 60,
 354                 .xres           = 1024,
 355                 .yres           = 768,
 356                 .pixclock       = 15385,
 357                 .left_margin    = 220,
 358                 .right_margin   = 40,
 359                 .upper_margin   = 21,
 360                 .lower_margin   = 7,
 361                 .hsync_len      = 60,
 362                 .vsync_len      = 10,
 363                 .sync           = FB_SYNC_EXT,
 364                 .vmode          = FB_VMODE_NONINTERLACED
 365 } }, {
 366         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 367         .bus    = 2,
 368         .addr   = 0x4,
 369         .pixfmt = IPU_PIX_FMT_LVDS666,
 370         .detect = detect_i2c,
 371         .enable = enable_lvds,
 372         .mode   = {
 373                 .name           = "Hannstar-XGA",
 374                 .refresh        = 60,
 375                 .xres           = 1024,
 376                 .yres           = 768,
 377                 .pixclock       = 15385,
 378                 .left_margin    = 220,
 379                 .right_margin   = 40,
 380                 .upper_margin   = 21,
 381                 .lower_margin   = 7,
 382                 .hsync_len      = 60,
 383                 .vsync_len      = 10,
 384                 .sync           = FB_SYNC_EXT,
 385                 .vmode          = FB_VMODE_NONINTERLACED
 386 } }, {
 387         /* DLC700JMG-T-4 */
 388         .bus    = 0,
 389         .addr   = 0,
 390         .detect = NULL,
 391         .enable = enable_lvds,
 392         .pixfmt = IPU_PIX_FMT_LVDS666,
 393         .mode   = {
 394                 .name           = "DLC700JMGT4",
 395                 .refresh        = 60,
 396                 .xres           = 1024,         /* 1024x600active pixels */
 397                 .yres           = 600,
 398                 .pixclock       = 15385,        /* 64MHz */
 399                 .left_margin    = 220,
 400                 .right_margin   = 40,
 401                 .upper_margin   = 21,
 402                 .lower_margin   = 7,
 403                 .hsync_len      = 60,
 404                 .vsync_len      = 10,
 405                 .sync           = FB_SYNC_EXT,
 406                 .vmode          = FB_VMODE_NONINTERLACED
 407 } }, {
 408         /* DLC800FIG-T-3 */
 409         .bus    = 0,
 410         .addr   = 0,
 411         .detect = NULL,
 412         .enable = enable_lvds,
 413         .pixfmt = IPU_PIX_FMT_LVDS666,
 414         .mode   = {
 415                 .name           = "DLC800FIGT3",
 416                 .refresh        = 60,
 417                 .xres           = 1024,         /* 1024x768 active pixels */
 418                 .yres           = 768,
 419                 .pixclock       = 15385,        /* 64MHz */
 420                 .left_margin    = 220,
 421                 .right_margin   = 40,
 422                 .upper_margin   = 21,
 423                 .lower_margin   = 7,
 424                 .hsync_len      = 60,
 425                 .vsync_len      = 10,
 426                 .sync           = FB_SYNC_EXT,
 427                 .vmode          = FB_VMODE_NONINTERLACED
 428 } } };
 429 size_t display_count = ARRAY_SIZE(displays);
 430
 431 static void setup_display(void)
 432 {
 433         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 434         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 435         int reg;
 436
 437         enable_ipu_clock();
 438         imx_setup_hdmi();
 439         /* Turn on LDB0,IPU,IPU DI0 clocks */
 440         reg = __raw_readl(&mxc_ccm->CCGR3);
 441         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 442         writel(reg, &mxc_ccm->CCGR3);
 443
 444         /* set LDB0, LDB1 clk select to 011/011 */
 445         reg = readl(&mxc_ccm->cs2cdr);
 446         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 447                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 448         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 449               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 450         writel(reg, &mxc_ccm->cs2cdr);
 451
 452         reg = readl(&mxc_ccm->cscmr2);
 453         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 454         writel(reg, &mxc_ccm->cscmr2);
 455
 456         reg = readl(&mxc_ccm->chsccdr);
 457         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 458                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 459         writel(reg, &mxc_ccm->chsccdr);
 460
 461         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 462              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 463              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 464              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 465              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 466              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 467              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 468              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 469              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 470         writel(reg, &iomux->gpr[2]);
 471
 472         reg = readl(&iomux->gpr[3]);
 473         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 474             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 475                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 476         writel(reg, &iomux->gpr[3]);
 477
 478         /* LVDS Backlight GPIO on LVDS connector - output low */
 479         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 480         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 481 }
 482 #endif /* CONFIG_VIDEO_IPUV3 */
 483
 484 /* setup board specific PMIC */
 485 int power_init_board(void)
 486 {
 487         setup_pmic();
 488         return 0;
 489 }
 490
 491 #if defined(CONFIG_CMD_PCI)
 492 int imx6_pcie_toggle_reset(void)
 493 {
 494         if (board_type < GW_UNKNOWN) {
 495                 uint pin = gpio_cfg[board_type].pcie_rst;
 496                 gpio_request(pin, "pci_rst#");
 497                 gpio_direction_output(pin, 0);
 498                 mdelay(50);
 499                 gpio_direction_output(pin, 1);
 500         }
 501         return 0;
 502 }
 503
 504 /*
 505  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 506  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 507  * properly and assert reset for 100ms.
 508  */
 509 #define MAX_PCI_DEVS    32
 510 struct pci_dev {
 511         pci_dev_t devfn;
 512         unsigned short vendor;
 513         unsigned short device;
 514         unsigned short class;
 515         unsigned short busno; /* subbordinate busno */
 516         struct pci_dev *ppar;
 517 };
 518 struct pci_dev pci_devs[MAX_PCI_DEVS];
 519 int pci_devno;
 520 int pci_bridgeno;
 521
 522 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 523                          unsigned short vendor, unsigned short device,
 524                          unsigned short class)
 525 {
 526         int i;
 527         u32 dw;
 528         struct pci_dev *pdev = &pci_devs[pci_devno++];
 529
 530         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 531               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 532
 533         /* store array of devs for later use in device-tree fixup */
 534         pdev->devfn = dev;
 535         pdev->vendor = vendor;
 536         pdev->device = device;
 537         pdev->class = class;
 538         pdev->ppar = NULL;
 539         if (class == PCI_CLASS_BRIDGE_PCI)
 540                 pdev->busno = ++pci_bridgeno;
 541         else
 542                 pdev->busno = 0;
 543
 544         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 545         if (PCI_BUS(dev) == 0)
 546                 pdev->devfn = 0;
 547
 548         /* find dev's parent */
 549         for (i = 0; i < pci_devno; i++) {
 550                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 551                         pdev->ppar = &pci_devs[i];
 552                         break;
 553                 }
 554         }
 555
 556         /* assert downstream PERST# */
 557         if (vendor == PCI_VENDOR_ID_PLX &&
 558             (device & 0xfff0) == 0x8600 &&
 559             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 560                 debug("configuring PLX 860X downstream PERST#\n");
 561                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 562                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 563                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 564
 565                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 566                 dw |= 0xfe;   /* GPIO1-7 output high */
 567                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 568
 569                 mdelay(100);
 570         }
 571 }
 572 #endif /* CONFIG_CMD_PCI */
 573
 574 #ifdef CONFIG_SERIAL_TAG
 575 /*
 576  * called when setting up ATAGS before booting kernel
 577  * populate serialnum from the following (in order of priority):
 578  *   serial# env var
 579  *   eeprom
 580  */
 581 void get_board_serial(struct tag_serialnr *serialnr)
 582 {
 583         char *serial = env_get("serial#");
 584
 585         if (serial) {
 586                 serialnr->high = 0;
 587                 serialnr->low = simple_strtoul(serial, NULL, 10);
 588         } else if (ventana_info.model[0]) {
 589                 serialnr->high = 0;
 590                 serialnr->low = ventana_info.serial;
 591         } else {
 592                 serialnr->high = 0;
 593                 serialnr->low = 0;
 594         }
 595 }
 596 #endif
 597
 598 /*
 599  * Board Support
 600  */
 601
 602 int board_early_init_f(void)
 603 {
 604         setup_iomux_uart();
 605
 606 #if defined(CONFIG_VIDEO_IPUV3)
 607         setup_display();
 608 #endif
 609         return 0;
 610 }
 611
 612 int dram_init(void)
 613 {
 614         gd->ram_size = imx_ddr_size();
 615         return 0;
 616 }
 617
 618 int board_init(void)
 619 {
 620         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 621
 622         clrsetbits_le32(&iomuxc_regs->gpr[1],
 623                         IOMUXC_GPR1_OTG_ID_MASK,
 624                         IOMUXC_GPR1_OTG_ID_GPIO1);
 625
 626         /* address of linux boot parameters */
 627         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 628
 629 #ifdef CONFIG_CMD_NAND
 630         setup_gpmi_nand();
 631 #endif
 632 #ifdef CONFIG_MXC_SPI
 633         setup_spi();
 634 #endif
 635         setup_ventana_i2c();
 636
 637 #ifdef CONFIG_SATA
 638         setup_sata();
 639 #endif
 640         /* read Gateworks EEPROM into global struct (used later) */
 641         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 642
 643         setup_iomux_gpio(board_type, &ventana_info);
 644
 645         return 0;
 646 }
 647
 648 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 649 /*
 650  * called during late init (after relocation and after board_init())
 651  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 652  * EEPROM read.
 653  */
 654 int checkboard(void)
 655 {
 656         struct ventana_board_info *info = &ventana_info;
 657         unsigned char buf[4];
 658         const char *p;
 659         int quiet; /* Quiet or minimal output mode */
 660
 661         quiet = 0;
 662         p = env_get("quiet");
 663         if (p)
 664                 quiet = simple_strtol(p, NULL, 10);
 665         else
 666                 env_set("quiet", "0");
 667
 668         puts("\nGateworks Corporation Copyright 2014\n");
 669         if (info->model[0]) {
 670                 printf("Model: %s\n", info->model);
 671                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 672                        info->mfgdate[0], info->mfgdate[1],
 673                        info->mfgdate[2], info->mfgdate[3]);
 674                 printf("Serial:%d\n", info->serial);
 675         } else {
 676                 puts("Invalid EEPROM - board will not function fully\n");
 677         }
 678         if (quiet)
 679                 return 0;
 680
 681         /* Display GSC firmware revision/CRC/status */
 682         gsc_info(0);
 683
 684         /* Display RTC */
 685         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 686                 printf("RTC:   %d\n",
 687                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 688         }
 689
 690         return 0;
 691 }
 692 #endif
 693
 694 #ifdef CONFIG_CMD_BMODE
 695 /*
 696  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 697  * see Table 8-11 and Table 5-9
 698  *  BOOT_CFG1[7] = 1 (boot from NAND)
 699  *  BOOT_CFG1[5] = 0 - raw NAND
 700  *  BOOT_CFG1[4] = 0 - default pad settings
 701  *  BOOT_CFG1[3:2] = 00 - devices = 1
 702  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 703  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 704  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 705  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 706  */
 707 static const struct boot_mode board_boot_modes[] = {
 708         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 709         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 710         { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
 711         { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
 712         { NULL, 0 },
 713 };
 714 #endif
 715
 716 /* late init */
 717 int misc_init_r(void)
 718 {
 719         struct ventana_board_info *info = &ventana_info;
 720         char buf[256];
 721         int i;
 722
 723         /* set env vars based on EEPROM data */
 724         if (ventana_info.model[0]) {
 725                 char str[16], fdt[36];
 726                 char *p;
 727                 const char *cputype = "";
 728
 729                 /*
 730                  * FDT name will be prefixed with CPU type.  Three versions
 731                  * will be created each increasingly generic and bootloader
 732                  * env scripts will try loading each from most specific to
 733                  * least.
 734                  */
 735                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 736                     is_cpu_type(MXC_CPU_MX6D))
 737                         cputype = "imx6q";
 738                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 739                          is_cpu_type(MXC_CPU_MX6SOLO))
 740                         cputype = "imx6dl";
 741                 env_set("soctype", cputype);
 742                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 743                         env_set("flash_layout", "large");
 744                 else
 745                         env_set("flash_layout", "normal");
 746                 memset(str, 0, sizeof(str));
 747                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 748                         str[i] = tolower(info->model[i]);
 749                 env_set("model", str);
 750                 if (!env_get("fdt_file")) {
 751                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 752                         env_set("fdt_file", fdt);
 753                 }
 754                 p = strchr(str, '-');
 755                 if (p) {
 756                         *p++ = 0;
 757
 758                         env_set("model_base", str);
 759                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 760                         env_set("fdt_file1", fdt);
 761                         if (board_type != GW551x &&
 762                             board_type != GW552x &&
 763                             board_type != GW553x &&
 764                             board_type != GW560x)
 765                                 str[4] = 'x';
 766                         str[5] = 'x';
 767                         str[6] = 0;
 768                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 769                         env_set("fdt_file2", fdt);
 770                 }
 771
 772                 /* initialize env from EEPROM */
 773                 if (test_bit(EECONFIG_ETH0, info->config) &&
 774                     !env_get("ethaddr")) {
 775                         eth_env_set_enetaddr("ethaddr", info->mac0);
 776                 }
 777                 if (test_bit(EECONFIG_ETH1, info->config) &&
 778                     !env_get("eth1addr")) {
 779                         eth_env_set_enetaddr("eth1addr", info->mac1);
 780                 }
 781
 782                 /* board serial-number */
 783                 sprintf(str, "%6d", info->serial);
 784                 env_set("serial#", str);
 785
 786                 /* memory MB */
 787                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 788                 env_set("mem_mb", str);
 789         }
 790
 791         /* Set a non-initialized hwconfig based on board configuration */
 792         if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
 793                 buf[0] = 0;
 794                 if (gpio_cfg[board_type].rs232_en)
 795                         strcat(buf, "rs232;");
 796                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 797                         char buf1[32];
 798                         sprintf(buf1, "dio%d:mode=gpio;", i);
 799                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 800                                 strcat(buf, buf1);
 801                 }
 802                 env_set("hwconfig", buf);
 803         }
 804
 805         /* setup baseboard specific GPIO based on board and env */
 806         setup_board_gpio(board_type, info);
 807
 808 #ifdef CONFIG_CMD_BMODE
 809         add_board_boot_modes(board_boot_modes);
 810 #endif
 811
 812         /* disable boot watchdog */
 813         gsc_boot_wd_disable();
 814
 815         return 0;
 816 }
 817
 818 #ifdef CONFIG_OF_BOARD_SETUP
 819
 820 static int ft_sethdmiinfmt(void *blob, char *mode)
 821 {
 822         int off;
 823
 824         if (!mode)
 825                 return -EINVAL;
 826
 827         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 828         if (off < 0)
 829                 return off;
 830
 831         if (0 == strcasecmp(mode, "yuv422bt656")) {
 832                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 833                              0x00, 0x00, 0x00 };
 834                 mode = "422_ccir";
 835                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 836                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 837                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 838                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 839                 printf("   set HDMI input mode to %s\n", mode);
 840         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 841                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 842                              0x82, 0x81, 0x00 };
 843                 mode = "422_smp";
 844                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 845                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 846                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 847                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 848                 printf("   set HDMI input mode to %s\n", mode);
 849         } else {
 850                 return -EINVAL;
 851         }
 852
 853         return 0;
 854 }
 855
 856 /* enable a property of a node if the node is found */
 857 static inline void ft_enable_path(void *blob, const char *path)
 858 {
 859         int i = fdt_path_offset(blob, path);
 860         if (i >= 0) {
 861                 debug("enabling %s\n", path);
 862                 fdt_status_okay(blob, i);
 863         }
 864 }
 865
 866 /* remove a property of a node if the node is found */
 867 static inline void ft_delprop_path(void *blob, const char *path,
 868                                    const char *name)
 869 {
 870         int i = fdt_path_offset(blob, path);
 871         if (i) {
 872                 debug("removing %s/%s\n", path, name);
 873                 fdt_delprop(blob, i, name);
 874         }
 875 }
 876
 877 #if defined(CONFIG_CMD_PCI)
 878 #define PCI_ID(x) ( \
 879         (PCI_BUS(x->devfn)<<16)| \
 880         (PCI_DEV(x->devfn)<<11)| \
 881         (PCI_FUNC(x->devfn)<<8) \
 882         )
 883 #define PCIE_PATH       "/soc/pcie@0x01000000"
 884 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 885 {
 886         uint32_t reg[5];
 887         char node[32];
 888         int np;
 889
 890         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 891                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 892
 893         np = fdt_subnode_offset(blob, par, node);
 894         if (np >= 0)
 895                 return np;
 896         np = fdt_add_subnode(blob, par, node);
 897         if (np < 0) {
 898                 printf("   %s failed: no space\n", __func__);
 899                 return np;
 900         }
 901
 902         memset(reg, 0, sizeof(reg));
 903         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 904         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 905
 906         return np;
 907 }
 908
 909 /* build a path of nested PCI devs for all bridges passed through */
 910 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 911 {
 912         struct pci_dev *bridges[MAX_PCI_DEVS];
 913         int k, np;
 914
 915         /* build list of parents */
 916         np = fdt_path_offset(blob, PCIE_PATH);
 917         if (np < 0)
 918                 return np;
 919
 920         k = 0;
 921         while (dev) {
 922                 bridges[k++] = dev;
 923                 dev = dev->ppar;
 924         };
 925
 926         /* now add them the to DT in reverse order */
 927         while (k--) {
 928                 np = fdt_add_pci_node(blob, np, bridges[k]);
 929                 if (np < 0)
 930                         break;
 931         }
 932
 933         return np;
 934 }
 935
 936 /*
 937  * The GW16082 has a hardware errata errata such that it's
 938  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 939  * of this normal PCI interrupt swizzling will not work so we will
 940  * provide an irq-map via device-tree.
 941  */
 942 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 943 {
 944         int len;
 945         int host;
 946         uint32_t imap_new[8*4*4];
 947         const uint32_t *imap;
 948         uint32_t irq[4];
 949         uint32_t reg[4];
 950         int i;
 951
 952         /* build irq-map based on host controllers map */
 953         host = fdt_path_offset(blob, PCIE_PATH);
 954         if (host < 0) {
 955                 printf("   %s failed: missing host\n", __func__);
 956                 return host;
 957         }
 958
 959         /* use interrupt data from root complex's node */
 960         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 961         if (!imap || len != 128) {
 962                 printf("   %s failed: invalid interrupt-map\n",
 963                        __func__);
 964                 return -FDT_ERR_NOTFOUND;
 965         }
 966
 967         /* obtain irq's of host controller in pin order */
 968         for (i = 0; i < 4; i++)
 969                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 970
 971         /*
 972          * determine number of swizzles necessary:
 973          *   For each bridge we pass through we need to swizzle
 974          *   the number of the slot we are on.
 975          */
 976         struct pci_dev *d;
 977         int b;
 978         b = 0;
 979         d = dev->ppar;
 980         while(d && d->ppar) {
 981                 b += PCI_DEV(d->devfn);
 982                 d = d->ppar;
 983         }
 984
 985         /* create new irq mappings for slots12-15
 986          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
 987          * J3    AD28    12     INTD      INTA
 988          * J4    AD29    13     INTC      INTD
 989          * J5    AD30    14     INTB      INTC
 990          * J2    AD31    15     INTA      INTB
 991          */
 992         for (i = 0; i < 4; i++) {
 993                 /* addr matches bus:dev:func */
 994                 u32 addr = dev->busno << 16 | (12+i) << 11;
 995
 996                 /* default cells from root complex */
 997                 memcpy(&imap_new[i*32], imap, 128);
 998                 /* first cell is PCI device address (BDF) */
 999                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1000                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1001                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1002                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1003                 /* third cell is pin */
1004                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1005                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1006                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1007                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1008                 /* sixth cell is relative interrupt */
1009                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1010                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1011                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1012                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1013         }
1014         fdt_setprop(blob, np, "interrupt-map", imap_new,
1015                     sizeof(imap_new));
1016         reg[0] = cpu_to_fdt32(0xfff00);
1017         reg[1] = 0;
1018         reg[2] = 0;
1019         reg[3] = cpu_to_fdt32(0x7);
1020         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1021         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1022         fdt_setprop_string(blob, np, "device_type", "pci");
1023         fdt_setprop_cell(blob, np, "#address-cells", 3);
1024         fdt_setprop_cell(blob, np, "#size-cells", 2);
1025         printf("   Added custom interrupt-map for GW16082\n");
1026
1027         return 0;
1028 }
1029
1030 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1031 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1032 {
1033         char *tmp, *end;
1034         char mac[16];
1035         unsigned char mac_addr[6];
1036         int j;
1037
1038         sprintf(mac, "eth1addr");
1039         tmp = env_get(mac);
1040         if (tmp) {
1041                 for (j = 0; j < 6; j++) {
1042                         mac_addr[j] = tmp ?
1043                                       simple_strtoul(tmp, &end,16) : 0;
1044                         if (tmp)
1045                                 tmp = (*end) ? end+1 : end;
1046                 }
1047                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1048                             sizeof(mac_addr));
1049                 printf("   Added mac addr for eth1\n");
1050                 return 0;
1051         }
1052
1053         return -1;
1054 }
1055
1056 /*
1057  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1058  * we will walk the PCI bus and add bridge nodes up to the device receiving
1059  * the fixup.
1060  */
1061 void ft_board_pci_fixup(void *blob, bd_t *bd)
1062 {
1063         int i, np;
1064         struct pci_dev *dev;
1065
1066         for (i = 0; i < pci_devno; i++) {
1067                 dev = &pci_devs[i];
1068
1069                 /*
1070                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1071                  * an EEPROM at i2c1-0x50.
1072                  */
1073                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1074                     (dev->device == 0x8240) &&
1075                     (i2c_set_bus_num(1) == 0) &&
1076                     (i2c_probe(0x50) == 0))
1077                 {
1078                         np = fdt_add_pci_path(blob, dev);
1079                         if (np > 0)
1080                                 fdt_fixup_gw16082(blob, np, dev);
1081                 }
1082
1083                 /* ethernet1 mac address */
1084                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1085                          (dev->device == 0x4380))
1086                 {
1087                         np = fdt_add_pci_path(blob, dev);
1088                         if (np > 0)
1089                                 fdt_fixup_sky2(blob, np, dev);
1090                 }
1091         }
1092 }
1093 #endif /* if defined(CONFIG_CMD_PCI) */
1094
1095 void ft_board_wdog_fixup(void *blob, const char *path)
1096 {
1097         ft_delprop_path(blob, path, "ext-reset-output");
1098         ft_delprop_path(blob, path, "fsl,ext-reset-output");
1099 }
1100
1101 /*
1102  * called prior to booting kernel or by 'fdt boardsetup' command
1103  *
1104  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1105  *  - mtd partitions based on mtdparts/mtdids env
1106  *  - system-serial (board serial num from EEPROM)
1107  *  - board (full model from EEPROM)
1108  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1109  */
1110 #define UART1_PATH      "/soc/aips-bus@02100000/serial@021ec000"
1111 #define WDOG1_PATH      "/soc/aips-bus@02000000/wdog@020bc000"
1112 #define WDOG2_PATH      "/soc/aips-bus@02000000/wdog@020c0000"
1113 #define GPIO3_PATH      "/soc/aips-bus@02000000/gpio@020a4000"
1114 int ft_board_setup(void *blob, bd_t *bd)
1115 {
1116         struct ventana_board_info *info = &ventana_info;
1117         struct ventana_eeprom_config *cfg;
1118         struct node_info nodes[] = {
1119                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1120                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1121         };
1122         const char *model = env_get("model");
1123         const char *display = env_get("display");
1124         int i;
1125         char rev = 0;
1126
1127         /* determine board revision */
1128         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1129                 if (ventana_info.model[i] >= 'A') {
1130                         rev = ventana_info.model[i];
1131                         break;
1132                 }
1133         }
1134
1135         if (env_get("fdt_noauto")) {
1136                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1137                 return 0;
1138         }
1139
1140         if (test_bit(EECONFIG_NAND, info->config)) {
1141                 /* Update partition nodes using info from mtdparts env var */
1142                 puts("   Updating MTD partitions...\n");
1143                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1144         }
1145
1146         /* Update display timings from display env var */
1147         if (display) {
1148                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1149                                       display) >= 0)
1150                         printf("   Set display timings for %s...\n", display);
1151         }
1152
1153         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1154
1155         /* board serial number */
1156         fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1157                     strlen(env_get("serial#")) + 1);
1158
1159         /* board (model contains model from device-tree) */
1160         fdt_setprop(blob, 0, "board", info->model,
1161                     strlen((const char *)info->model) + 1);
1162
1163         /* set desired digital video capture format */
1164         ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1165
1166         /*
1167          * Board model specific fixups
1168          */
1169         switch (board_type) {
1170         case GW51xx:
1171                 /*
1172                  * disable wdog node for GW51xx-A/B to work around
1173                  * errata causing wdog timer to be unreliable.
1174                  */
1175                 if (rev >= 'A' && rev < 'C') {
1176                         i = fdt_path_offset(blob, WDOG1_PATH);
1177                         if (i)
1178                                 fdt_status_disabled(blob, i);
1179                 }
1180
1181                 /* GW51xx-E adds WDOG1_B external reset */
1182                 if (rev < 'E')
1183                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1184                 break;
1185
1186         case GW52xx:
1187                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1188                 if (info->model[4] == '2') {
1189                         u32 handle = 0;
1190                         u32 *range = NULL;
1191
1192                         i = fdt_node_offset_by_compatible(blob, -1,
1193                                                           "fsl,imx6q-pcie");
1194                         if (i)
1195                                 range = (u32 *)fdt_getprop(blob, i,
1196                                                            "reset-gpio", NULL);
1197
1198                         if (range) {
1199                                 i = fdt_path_offset(blob, GPIO3_PATH);
1200                                 if (i)
1201                                         handle = fdt_get_phandle(blob, i);
1202                                 if (handle) {
1203                                         range[0] = cpu_to_fdt32(handle);
1204                                         range[1] = cpu_to_fdt32(23);
1205                                 }
1206                         }
1207
1208                         /* these have broken usd_vsel */
1209                         if (strstr((const char *)info->model, "SP318-B") ||
1210                             strstr((const char *)info->model, "SP331-B"))
1211                                 gpio_cfg[board_type].usd_vsel = 0;
1212
1213                         /* GW522x-B adds WDOG1_B external reset */
1214                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1215                 }
1216
1217                 /* GW520x-E adds WDOG1_B external reset */
1218                 else if (info->model[4] == '0' && rev < 'E')
1219                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1220                 break;
1221
1222         case GW53xx:
1223                 /* GW53xx-E adds WDOG1_B external reset */
1224                 if (rev < 'E')
1225                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1226                 break;
1227
1228         case GW54xx:
1229                 /*
1230                  * disable serial2 node for GW54xx for compatibility with older
1231                  * 3.10.x kernel that improperly had this node enabled in the DT
1232                  */
1233                 i = fdt_path_offset(blob, UART1_PATH);
1234                 if (i)
1235                         fdt_del_node(blob, i);
1236
1237                 /* GW54xx-E adds WDOG2_B external reset */
1238                 if (rev < 'E')
1239                         ft_board_wdog_fixup(blob, WDOG2_PATH);
1240                 break;
1241
1242         case GW551x:
1243                 /*
1244                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1245                  * causing non functional digital video in (it is not hooked up)
1246                  */
1247                 if (rev == 'A') {
1248                         u32 *range = NULL;
1249                         int len;
1250                         const u32 *handle = NULL;
1251
1252                         i = fdt_node_offset_by_compatible(blob, -1,
1253                                                 "fsl,imx-tda1997x-video");
1254                         if (i)
1255                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1256                                                      NULL);
1257                         if (handle)
1258                                 i = fdt_node_offset_by_phandle(blob,
1259                                                         fdt32_to_cpu(*handle));
1260                         if (i)
1261                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1262                                                            &len);
1263                         if (range) {
1264                                 len /= sizeof(u32);
1265                                 for (i = 0; i < len; i += 6) {
1266                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1267                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1268                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1269                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1270                                             mux_reg == 0x260 &&
1271                                             conf_reg == 0x630)
1272                                                 range[i+3] = cpu_to_fdt32(0x5);
1273                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1274                                                  mux_reg == 0x08c &&
1275                                                  conf_reg == 0x3a0)
1276                                                 range[i+3] = cpu_to_fdt32(0x5);
1277                                 }
1278                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1279                                                     len);
1280                         }
1281
1282                         /* set BT656 video format */
1283                         ft_sethdmiinfmt(blob, "yuv422bt656");
1284                 }
1285
1286                 /* GW551x-C adds WDOG1_B external reset */
1287                 if (rev < 'C')
1288                         ft_board_wdog_fixup(blob, WDOG1_PATH);
1289                 break;
1290         }
1291
1292         /* Configure DIO */
1293         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1294                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1295                 char arg[10];
1296
1297                 sprintf(arg, "dio%d", i);
1298                 if (!hwconfig(arg))
1299                         continue;
1300                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1301                 {
1302                         char path[48];
1303                         sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
1304                                 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
1305                         printf("   Enabling pwm%d for DIO%d\n",
1306                                cfg->pwm_param, i);
1307                         ft_enable_path(blob, path);
1308                 }
1309         }
1310
1311         /* remove no-1-8-v if UHS-I support is present */
1312         if (gpio_cfg[board_type].usd_vsel) {
1313                 debug("Enabling UHS-I support\n");
1314                 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
1315                                 "no-1-8-v");
1316         }
1317
1318 #if defined(CONFIG_CMD_PCI)
1319         if (!env_get("nopcifixup"))
1320                 ft_board_pci_fixup(blob, bd);
1321 #endif
1322
1323         /*
1324          * Peripheral Config:
1325          *  remove nodes by alias path if EEPROM config tells us the
1326          *  peripheral is not loaded on the board.
1327          */
1328         if (env_get("fdt_noconfig")) {
1329                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1330                 return 0;
1331         }
1332         cfg = econfig;
1333         while (cfg->name) {
1334                 if (!test_bit(cfg->bit, info->config)) {
1335                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1336                                                cfg->dtalias : cfg->name);
1337                 }
1338                 cfg++;
1339         }
1340
1341         return 0;
1342 }
1343 #endif /* CONFIG_OF_BOARD_SETUP */
1344
1345 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1346         .reg = (struct mxc_uart *)UART2_BASE,
1347 };
1348
1349 U_BOOT_DEVICE(ventana_serial) = {
1350         .name   = "serial_mxc",
1351         .platdata = &ventana_mxc_serial_plat,
1352 };