git.sur5r.net Git - u-boot/blob - board/hisilicon/poplar/poplar.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 Linaro
   4  * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
   5  */
   6
   7 #include <dm.h>
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <dm/platform_data/serial_pl01x.h>
  11 #include <asm/arch/hi3798cv200.h>
  12 #include <asm/arch/dwmmc.h>
  13 #include <asm/armv8/mmu.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 static struct mm_region poplar_mem_map[] = {
  18         {
  19                 .virt = 0x0UL,
  20                 .phys = 0x0UL,
  21                 .size = 0x80000000UL,
  22                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  23                          PTE_BLOCK_INNER_SHARE
  24         }, {
  25                 .virt = 0x80000000UL,
  26                 .phys = 0x80000000UL,
  27                 .size = 0x80000000UL,
  28                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  29                          PTE_BLOCK_NON_SHARE |
  30                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  31         }, {
  32                 0,
  33         }
  34 };
  35
  36 struct mm_region *mem_map = poplar_mem_map;
  37
  38 static const struct pl01x_serial_platdata serial_platdata = {
  39         .base = REG_BASE_UART0,
  40         .type = TYPE_PL010,
  41         .clock = 75000000,
  42 };
  43
  44 U_BOOT_DEVICE(poplar_serial) = {
  45         .name = "serial_pl01x",
  46         .platdata = &serial_platdata,
  47 };
  48
  49 int checkboard(void)
  50 {
  51         puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
  52
  53         return 0;
  54 }
  55
  56 void reset_cpu(ulong addr)
  57 {
  58         psci_system_reset();
  59 }
  60
  61 int dram_init(void)
  62 {
  63         gd->ram_size = get_ram_size(NULL, 0x80000000);
  64
  65         return 0;
  66 }
  67
  68 /*
  69  * Some linux kernel versions don't use memory before its load address, so to
  70  * be generic we just pretend it isn't there.  In previous uboot versions we
  71  * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
  72  * could persist in memory and be left alone by the kernel.
  73  *
  74  * That led to a problem when mapping memory in older kernels.  That PSCI code
  75  * now lies in memory below the kernel load offset; it therefore won't be
  76  * touched by the kernel, and by not specially reserving it we avoid the mapping
  77  * problem as well.
  78  *
  79  */
  80 #define KERNEL_TEXT_OFFSET      0x00080000
  81
  82 int dram_init_banksize(void)
  83 {
  84         gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
  85         gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
  86
  87         return 0;
  88 }
  89
  90 static void usb2_phy_config(void)
  91 {
  92         const u32 config[] = {
  93                 /* close EOP pre-emphasis. open data pre-emphasis */
  94                 0xa1001c,
  95                 /* Rcomp = 150mW, increase DC level */
  96                 0xa00607,
  97                 /* keep Rcomp working */
  98                 0xa10700,
  99                 /* Icomp = 212mW, increase current drive */
 100                 0xa00aab,
 101                 /* EMI fix: rx_active not stay 1 when error packets received */
 102                 0xa11140,
 103                 /* Comp mode select */
 104                 0xa11041,
 105                 /* adjust eye diagram */
 106                 0xa0098c,
 107                 /* adjust eye diagram */
 108                 0xa10a0a,
 109         };
 110         int i;
 111
 112         for (i = 0; i < ARRAY_SIZE(config); i++) {
 113                 writel(config[i], PERI_CTRL_USB0);
 114                 clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
 115                 udelay(20);
 116         }
 117 }
 118
 119 static void usb2_phy_init(void)
 120 {
 121         /* reset usb2 controller bus/utmi/roothub */
 122         setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
 123                         USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
 124         udelay(200);
 125
 126         /* reset usb2 phy por/utmi */
 127         setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
 128         udelay(200);
 129
 130         /* open usb2 ref clk */
 131         setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
 132         udelay(300);
 133
 134         /* cancel usb2 power on reset */
 135         clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
 136         udelay(500);
 137
 138         usb2_phy_config();
 139
 140         /* cancel usb2 port reset, wait comp circuit stable */
 141         clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
 142         mdelay(10);
 143
 144         /* open usb2 controller clk */
 145         setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
 146                         USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
 147                         USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
 148         udelay(200);
 149
 150         /* cancel usb2 control reset */
 151         clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
 152                         USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
 153         udelay(200);
 154 }
 155
 156 int board_mmc_init(bd_t *bis)
 157 {
 158         int ret;
 159
 160         ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8);
 161         if (ret)
 162                 printf("mmc init error (%d)\n", ret);
 163
 164         return ret;
 165 }
 166
 167 int board_init(void)
 168 {
 169         usb2_phy_init();
 170
 171         return 0;
 172 }
 173