1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mx6-ddr.h>
15 #include <asm/arch/sys_proto.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/spi.h>
24 #include <fsl_esdhc.h>
30 #include <dm/platform_data/serial_mxc.h>
31 #include <dm/platdata.h>
33 #ifndef CONFIG_MXC_SPI
34 #error "CONFIG_SPI must be set for this board"
35 #error "Please check your config file"
40 DECLARE_GLOBAL_DATA_PTR;
42 static bool hw_ids_valid;
43 static bool sw_ids_valid;
47 #define EM_PAD IMX_GPIO_NR(3, 29)
48 #define SW0 IMX_GPIO_NR(2, 4)
49 #define SW1 IMX_GPIO_NR(2, 5)
50 #define SW2 IMX_GPIO_NR(2, 6)
51 #define SW3 IMX_GPIO_NR(2, 7)
52 #define HW0 IMX_GPIO_NR(6, 7)
53 #define HW1 IMX_GPIO_NR(6, 9)
54 #define HW2 IMX_GPIO_NR(6, 10)
55 #define HW3 IMX_GPIO_NR(6, 11)
56 #define HW4 IMX_GPIO_NR(4, 7)
57 #define HW5 IMX_GPIO_NR(4, 11)
58 #define HW6 IMX_GPIO_NR(4, 13)
59 #define HW7 IMX_GPIO_NR(4, 15)
61 int gpio_table_sw_ids[] = {
65 const char *gpio_table_sw_ids_names[] = {
66 "sw0", "sw1", "sw2", "sw3"
69 int gpio_table_hw_ids[] = {
70 HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7
73 const char *gpio_table_hw_ids_names[] = {
74 "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
77 static int get_board_id(int *ids, const char **c, int size,
84 for (i = 0; i < size; i++) {
85 ret = gpio_request(ids[i], c[i]);
87 printf("Can't request SWx gpios\n");
92 for (i = 0; i < size; i++) {
93 ret = gpio_direction_input(ids[i]);
95 printf("Can't set SWx gpios direction\n");
100 for (i = 0; i < size; i++) {
101 val = gpio_get_value(ids[i]);
103 printf("Can't get SW%d ID\n", i);
116 gd->ram_size = imx_ddr_size();
121 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
123 struct i2c_pads_info i2c_pad_info0 = {
125 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
126 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
127 .gp = IMX_GPIO_NR(3, 21)
130 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
131 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
132 .gp = IMX_GPIO_NR(3, 28)
136 /* I2C2: TIVO TM4C123 */
137 struct i2c_pads_info i2c_pad_info1 = {
139 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
140 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
141 .gp = IMX_GPIO_NR(2, 30)
144 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
145 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
146 .gp = IMX_GPIO_NR(3, 16)
150 /* I2C3: PMIC PF0100, EEPROM AT24C256C */
151 struct i2c_pads_info i2c_pad_info2 = {
153 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
154 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
155 .gp = IMX_GPIO_NR(3, 17)
158 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
159 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
160 .gp = IMX_GPIO_NR(3, 18)
164 iomux_v3_cfg_t const misc_pads[] = {
165 /* Prod ID GPIO pins */
166 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
167 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
168 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
169 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
171 /* HW revision GPIO pins */
172 MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
173 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
174 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
175 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
177 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
178 MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
179 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
182 MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
184 /* Emergency recovery pin */
185 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
188 #ifdef CONFIG_FSL_ESDHC
189 struct fsl_esdhc_cfg usdhc_cfg[1] = {
190 { USDHC4_BASE_ADDR, 0, 8, },
193 int board_mmc_getcd(struct mmc *mmc)
198 int board_mmc_init(bd_t *bis)
200 displ5_set_iomux_usdhc();
202 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
204 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
206 #endif /* CONFIG_FSL_ESDHC */
208 static void displ5_setup_ecspi(void)
212 displ5_set_iomux_ecspi();
214 ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0");
216 gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
218 ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp");
220 gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
223 #ifdef CONFIG_FEC_MXC
224 iomux_v3_cfg_t const enet_pads[] = {
225 MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL),
226 MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
227 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
228 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
229 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
231 /* for old evalboard with R159 present and R160 not populated */
232 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
234 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
235 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
236 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
237 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
238 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
239 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
241 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
242 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
243 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
244 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
245 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
246 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
248 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
251 static void setup_iomux_enet(void)
253 SETUP_IOMUX_PADS(enet_pads);
254 gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
257 int board_eth_init(bd_t *bd)
259 struct phy_device *phydev;
265 iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
267 ret = enable_fec_anatop_clock(0, ENET_125MHZ);
271 bus = fec_get_miibus(IMX_FEC_BASE, -1);
276 * We use here the "rgmii-id" mode of operation and allow M88E1512
277 * PHY to use its internally callibrated RX/TX delays
279 phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
280 PHY_INTERFACE_MODE_RGMII_ID);
286 /* display5 due to PCB routing can only work with 100 Mbps */
287 phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
288 ADVERTISED_1000baseX_Full |
289 SUPPORTED_1000baseT_Half |
290 SUPPORTED_1000baseT_Full);
292 ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
301 mdio_unregister(bus);
305 #endif /* CONFIG_FEC_MXC */
308 * Do not overwrite the console
309 * Always use serial for U-Boot console
311 int overwrite_console(void)
316 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
317 int ft_board_setup(void *blob, bd_t *bd)
319 fdt_fixup_ethernet(blob);
326 debug("board init\n");
327 /* address of boot parameters */
328 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
330 /* Setup iomux for non console UARTS */
331 displ5_set_iomux_uart();
333 displ5_setup_ecspi();
335 SETUP_IOMUX_PADS(misc_pads);
337 get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
338 ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id);
339 debug("SWx unit_id 0x%x\n", unit_id);
341 get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0],
342 ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id);
343 debug("HWx cpu_id 0x%x\n", cpu_id);
345 if (hw_ids_valid && sw_ids_valid)
346 printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
350 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
351 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
352 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
357 #ifdef CONFIG_CMD_BMODE
358 static const struct boot_mode board_boot_modes[] = {
359 /* eMMC, USDHC-4, 8-bit bus width */
360 /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
361 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
362 {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
366 static void setup_boot_modes(void)
368 add_board_boot_modes(board_boot_modes);
371 static inline void setup_boot_modes(void) {}
374 int misc_init_r(void)
380 ret = gpio_request(EM_PAD, "Emergency_PAD");
382 printf("Can't request emergency PAD gpio\n");
386 ret = gpio_direction_input(EM_PAD);
388 printf("Can't set emergency PAD direction\n");
395 static struct mxc_serial_platdata mxc_serial_plat = {
396 .reg = (struct mxc_uart *)UART5_BASE,
399 U_BOOT_DEVICE(mxc_serial) = {
400 .name = "serial_mxc",
401 .platdata = &mxc_serial_plat,