git.sur5r.net Git - u-boot/blob - board/micronas/vct/ebi_onenand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <linux/mtd/mtd.h>
   9 #include <linux/mtd/onenand.h>
  10 #include "vct.h"
  11
  12 #define BURST_SIZE_WORDS                4
  13
  14 static u16 ebi_nand_read_word(void __iomem *addr)
  15 {
  16         reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr));
  17         ebi_wait();
  18
  19         return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16;
  20 }
  21
  22 static void ebi_nand_write_word(u16 data, void __iomem * addr)
  23 {
  24         ebi_wait();
  25         reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16));
  26         reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
  27                   EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr);
  28         ebi_wait();
  29 }
  30
  31 /*
  32  * EBI initialization for OneNAND FLASH access
  33  */
  34 int ebi_init_onenand(void)
  35 {
  36         reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
  37
  38         reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002);
  39         reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
  40
  41         reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002);
  42         reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */
  43
  44         reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000);
  45         reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000);
  46         reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223);
  47         reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220);
  48         reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000);
  49         reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000);
  50         reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000);
  51         reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200);
  52
  53         reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
  54         reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
  55
  56         reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000);
  57         reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
  58
  59         /* prepare DMA configuration for EBI */
  60         reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00);
  61
  62         /* READ only no byte order change, TAG 1 used */
  63         reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004);
  64
  65         reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */
  66         reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1);
  67         reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2);
  68         reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3);
  69
  70         return 0;
  71 }
  72
  73 static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len)
  74 {
  75         void *ret = dst;
  76         u16 *d = dst;
  77         u16 *s = (u16 *)src;
  78
  79         len >>= 1;
  80         while (len-- > 0)
  81                 *d++ = ebi_nand_read_word(s++);
  82
  83         return ret;
  84 }
  85
  86 static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len)
  87 {
  88         void *ret = dst;
  89         u32 *d = (u32 *)dst;
  90         u32 s = (u32)src;
  91         u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int);
  92         u32 n_blocks = len / bytes_per_block;
  93         u32 block = 0;
  94         u32 burst_word;
  95
  96         for (block = 0; block < n_blocks; block++) {
  97                 /* Trigger read channel 3 */
  98                 reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
  99                           (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block))));
 100                 /* Poll status to see whether read has finished */
 101                 ebi_wait();
 102
 103                 /* Squirrel the data away in a safe place */
 104                 for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++)
 105                         *d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
 106         }
 107
 108         return ret;
 109 }
 110
 111 static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len)
 112 {
 113         void *ret = dst;
 114         u16 *d = dst;
 115         u16 *s = (u16 *)src;
 116
 117         len >>= 1;
 118         while (len-- > 0)
 119                 ebi_nand_write_word(*s++, d++);
 120
 121         return ret;
 122 }
 123
 124 static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
 125 {
 126         struct onenand_chip *this = mtd->priv;
 127
 128         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 129                 if (area == ONENAND_DATARAM)
 130                         return mtd->writesize;
 131                 if (area == ONENAND_SPARERAM)
 132                         return mtd->oobsize;
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
 139                               unsigned char *buffer, int offset,
 140                               size_t count)
 141 {
 142         struct onenand_chip *this = mtd->priv;
 143         void __iomem *bufferram;
 144
 145         bufferram = this->base + area;
 146         bufferram += onenand_bufferram_offset(mtd, area);
 147
 148         if (count < 4)
 149                 memcpy_16_from_onenand(buffer, bufferram + offset, count);
 150         else
 151                 memcpy_32_from_onenand(buffer, bufferram + offset, count);
 152
 153         return 0;
 154 }
 155
 156 static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
 157                                const unsigned char *buffer, int offset,
 158                                size_t count)
 159 {
 160         struct onenand_chip *this = mtd->priv;
 161         void __iomem *bufferram;
 162
 163         bufferram = this->base + area;
 164         bufferram += onenand_bufferram_offset(mtd, area);
 165
 166         memcpy_16_to_onenand(bufferram + offset, buffer, count);
 167
 168         return 0;
 169 }
 170
 171 int onenand_board_init(struct mtd_info *mtd)
 172 {
 173         struct onenand_chip *chip = mtd->priv;
 174
 175         /*
 176          * Insert board specific OneNAND access functions
 177          */
 178         chip->read_word = ebi_nand_read_word;
 179         chip->write_word = ebi_nand_write_word;
 180
 181         chip->read_bufferram = ebi_read_bufferram;
 182         chip->write_bufferram = ebi_write_bufferram;
 183
 184         return 0;
 185 }