git.sur5r.net Git - u-boot/blob - board/renesas/rsk7264/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2011 Renesas Electronics Europe Ltd.
   3  * Copyright (C) 2008 Renesas Solutions Corp.
   4  * Copyright (C) 2008 Nobuhiro Iwamatsu
   5  *
   6  * Based on board/renesas/rsk7203/lowlevel_init.S
   7  *
   8  * This file is released under the terms of GPL v2 and any later version.
   9  * See the file COPYING in the root directory of the source tree for details.
  10  */
  11 #include <config.h>
  12 #include <version.h>
  13
  14 #include <asm/processor.h>
  15 #include <asm/macro.h>
  16
  17         .global lowlevel_init
  18
  19         .text
  20         .align  2
  21
  22 lowlevel_init:
  23         /* Cache setting */
  24         write32 CCR1_A ,CCR1_D
  25
  26         /* io_set_cpg */
  27         write8 STBCR3_A, STBCR3_D
  28         write8 STBCR4_A, STBCR4_D
  29         write8 STBCR5_A, STBCR5_D
  30         write8 STBCR6_A, STBCR6_D
  31         write8 STBCR7_A, STBCR7_D
  32         write8 STBCR8_A, STBCR8_D
  33
  34         /* ConfigurePortPins */
  35
  36         /* Leaving LED1 ON for sanity test */
  37         write16 PJCR1_A, PJCR1_D1
  38         write16 PJCR2_A, PJCR2_D
  39         write16 PJIOR0_A, PJIOR0_D1
  40         write16 PJDR0_A, PJDR0_D
  41         write16 PJPR0_A, PJPR0_D
  42
  43         /* Configure EN_PIN & RS_PIN */
  44         write16 PGCR2_A, PGCR2_D
  45         write16 PGIOR0_A, PGIOR0_D
  46
  47         /* Configure the port pins connected to UART */
  48         write16 PJCR1_A, PJCR1_D2
  49         write16 PJIOR0_A, PJIOR0_D2
  50
  51         /* Configure Operating Frequency */
  52         write16 WTCSR_A, WTCSR_D0
  53         write16 WTCSR_A, WTCSR_D1
  54         write16 WTCNT_A, WTCNT_D
  55
  56         /* Control of RESBANK */
  57         write16 IBNR_A, IBNR_D
  58         /* Enable SCIF3 module */
  59         write16 STBCR4_A, STBCR4_D
  60
  61         /* Set clock mode*/
  62         write16 FRQCR_A, FRQCR_D
  63
  64         /* Configure Bus And Memory */
  65 init_bsc_cs0:
  66
  67 pfc_settings:
  68         write16 PCCR2_A, PCCR2_D
  69         write16 PCCR1_A, PCCR1_D
  70         write16 PCCR0_A, PCCR0_D
  71
  72         write16 PBCR0_A, PBCR0_D
  73         write16 PBCR1_A, PBCR1_D
  74         write16 PBCR2_A, PBCR2_D
  75         write16 PBCR3_A, PBCR3_D
  76         write16 PBCR4_A, PBCR4_D
  77         write16 PBCR5_A, PBCR5_D
  78
  79         write16 PDCR0_A, PDCR0_D
  80         write16 PDCR1_A, PDCR1_D
  81         write16 PDCR2_A, PDCR2_D
  82         write16 PDCR3_A, PDCR3_D
  83
  84         write32 CS0WCR_A, CS0WCR_D
  85         write32 CS0BCR_A, CS0BCR_D
  86
  87 init_bsc_cs2:
  88         write16 PJCR0_A, PJCR0_D
  89         write32 CS2WCR_A, CS2WCR_D
  90
  91 init_sdram:
  92         write32 CS3BCR_A, CS3BCR_D
  93         write32 CS3WCR_A, CS3WCR_D
  94         write32 SDCR_A, SDCR_D
  95         write32 RTCOR_A, RTCOR_D
  96         write32 RTCSR_A, RTCSR_D
  97
  98         /* wait 200us */
  99         mov.l   REPEAT_D, r3
 100         mov     #0, r2
 101 repeat0:
 102         add     #1, r2
 103         cmp/hs  r3, r2
 104         bf      repeat0
 105         nop
 106
 107         mov.l   SDRAM_MODE, r1
 108         mov     #0, r0
 109         mov.l   r0, @r1
 110
 111         nop
 112         rts
 113
 114         .align 4
 115
 116 CCR1_A:         .long CCR1
 117 CCR1_D:         .long 0x0000090B
 118 FRQCR_A:        .long 0xFFFE0010
 119 FRQCR_D:        .word 0x1003
 120 .align 2
 121 STBCR3_A:       .long 0xFFFE0408
 122 STBCR3_D:       .long 0x00000002
 123 STBCR4_A:       .long 0xFFFE040C
 124 STBCR4_D:       .word 0x0000
 125 .align 2
 126 STBCR5_A:       .long 0xFFFE0410
 127 STBCR5_D:       .long 0x00000010
 128 STBCR6_A:       .long 0xFFFE0414
 129 STBCR6_D:       .long 0x00000002
 130 STBCR7_A:       .long 0xFFFE0418
 131 STBCR7_D:       .long 0x0000002A
 132 STBCR8_A:       .long 0xFFFE041C
 133 STBCR8_D:       .long 0x0000007E
 134 PJCR1_A:        .long 0xFFFE390C
 135 PJCR1_D1:       .word 0x0000
 136 PJCR1_D2:       .word 0x0022
 137 PJCR2_A:        .long 0xFFFE390A
 138 PJCR2_D:        .word 0x0000
 139 .align 2
 140 PJIOR0_A:       .long 0xFFFE3912
 141 PJIOR0_D1:      .word 0x0FC0
 142 PJIOR0_D2:      .word 0x0FE0
 143 PJDR0_A:        .long 0xFFFE3916
 144 PJDR0_D:        .word 0x0FBF
 145 .align 2
 146 PJPR0_A:        .long 0xFFFE391A
 147 PJPR0_D:        .long 0x00000FBF
 148 PGCR2_A:        .long 0xFFFE38CA
 149 PGCR2_D:        .word 0x0000
 150 .align 2
 151 PGIOR0_A:       .long 0xFFFE38D2
 152 PGIOR0_D:       .word 0x03F0
 153 .align 2
 154 WTCSR_A:        .long 0xFFFE0000
 155 WTCSR_D0:       .word 0x0000
 156 WTCSR_D1:       .word 0x0000
 157 WTCNT_A:        .long 0xFFFE0002
 158 WTCNT_D:        .word 0x0000
 159 .align 2
 160 PCCR0_A:        .long 0xFFFE384E
 161 PDCR0_A:        .long 0xFFFE386E
 162 PDCR1_A:        .long 0xFFFE386C
 163 PDCR2_A:        .long 0xFFFE386A
 164 PDCR3_A:        .long 0xFFFE3868
 165 PBCR0_A:        .long 0xFFFE382E
 166 PBCR1_A:        .long 0xFFFE382C
 167 PBCR2_A:        .long 0xFFFE382A
 168 PBCR3_A:        .long 0xFFFE3828
 169 PBCR4_A:        .long 0xFFFE3826
 170 PBCR5_A:        .long 0xFFFE3824
 171 PCCR0_D:        .word 0x1111
 172 PDCR0_D:        .word 0x1111
 173 PDCR1_D:        .word 0x1111
 174 PDCR2_D:        .word 0x1111
 175 PDCR3_D:        .word 0x1111
 176 PBCR0_D:        .word 0x1110
 177 PBCR1_D:        .word 0x1111
 178 PBCR2_D:        .word 0x1111
 179 PBCR3_D:        .word 0x1111
 180 PBCR4_D:        .word 0x1111
 181 PBCR5_D:        .word 0x0111
 182 .align 2
 183 CS0WCR_A:       .long 0xFFFC0028
 184 CS0WCR_D:       .long 0x00000B41
 185 CS0BCR_A:       .long 0xFFFC0004
 186 CS0BCR_D:       .long 0x10000400
 187 PJCR0_A:        .long 0xFFFE390E
 188 PJCR0_D:        .word 0x3300
 189 .align 2
 190 CS2WCR_A:       .long 0xFFFC0030
 191 CS2WCR_D:       .long 0x00000B01
 192 PCCR2_A:        .long 0xFFFE384A
 193 PCCR2_D:        .word 0x0001
 194 .align 2
 195 PCCR1_A:        .long 0xFFFE384C
 196 PCCR1_D:        .word 0x1111
 197 .align 2
 198 CS3BCR_A:       .long 0xFFFC0010
 199 CS3BCR_D:       .long 0x00004400
 200 CS3WCR_A:       .long 0xFFFC0034
 201 CS3WCR_D:       .long 0x0000288A
 202 SDCR_A:         .long 0xFFFC004C
 203 SDCR_D:         .long 0x00000812
 204 RTCOR_A:        .long 0xFFFC0058
 205 RTCOR_D:        .long 0xA55A0046
 206 RTCSR_A:        .long 0xFFFC0050
 207 RTCSR_D:        .long 0xA55A0010
 208 IBNR_A:         .long 0xFFFE080E
 209 IBNR_D: .word 0x0000
 210 .align 2
 211 SDRAM_MODE:     .long 0xFFFC5040
 212 REPEAT_D:       .long 0x00000085