git.sur5r.net Git - u-boot/blob - board/socrates/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2008
   4  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   5  *
   6  * Copyright 2008 Freescale Semiconductor, Inc.
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  */
  11
  12 #include <common.h>
  13 #include <asm/mmu.h>
  14
  15 struct fsl_e_tlb_entry tlb_table[] = {
  16         /* TLB 0 - for temp stack in cache */
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  18                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  24                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25                       0, 0, BOOKE_PAGESZ_4K, 0),
  26         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  27                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  28                       0, 0, BOOKE_PAGESZ_4K, 0),
  29
  30
  31         /*
  32          * TLB 1:       64M     Non-cacheable, guarded
  33          * 0xfc000000   64M     FLASH
  34          * Out of reset this entry is only 4K.
  35          */
  36         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  37                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38                       0, 1, BOOKE_PAGESZ_64M, 1),
  39
  40         /*
  41          * TLB 2:       256M    Non-cacheable, guarded
  42          * 0x80000000   256M    PCI1 MEM First half
  43          */
  44         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  45                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  46                       0, 2, BOOKE_PAGESZ_256M, 1),
  47
  48         /*
  49          * TLB 3:       256M    Non-cacheable, guarded
  50          * 0x90000000   256M    PCI1 MEM Second half
  51          */
  52         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  53                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                       0, 3, BOOKE_PAGESZ_256M, 1),
  55
  56 #if defined(CONFIG_SYS_FPGA_BASE)
  57         /*
  58          * TLB 4:       1M      Non-cacheable, guarded
  59          * 0xc0000000   1M      FPGA and NAND
  60          */
  61         SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
  62                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  63                       0, 4, BOOKE_PAGESZ_1M, 1),
  64 #endif
  65
  66         /*
  67          * TLB 5:       64M     Non-cacheable, guarded
  68          * 0xc8000000   16M     LIME GDC framebuffer
  69          * 0xc9fc0000   256K    LIME GDC MMIO
  70          * (0xcbfc0000  256K    LIME GDC MMIO)
  71          * MMIO is relocatable and could be at 0xcbfc0000
  72          */
  73         SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
  74                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  75                       0, 5, BOOKE_PAGESZ_64M, 1),
  76
  77         /*
  78          * TLB 6:       64M     Non-cacheable, guarded
  79          * 0xe000_0000  1M      CCSRBAR
  80          * 0xe200_0000  16M     PCI1 IO
  81          */
  82         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  83                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  84                       0, 6, BOOKE_PAGESZ_64M, 1),
  85
  86 #if !defined(CONFIG_SPD_EEPROM)
  87         /*
  88          * TLB 7+8:     512M    DDR, cache disabled (needed for memory test)
  89          * 0x00000000  512M     DDR System memory
  90          * Without SPD EEPROM configured DDR, this must be setup manually.
  91          * Make sure the TLB count at the top of this table is correct.
  92          * Likely it needs to be increased by two for these entries.
  93          */
  94         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  95                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  96                       0, 7, BOOKE_PAGESZ_256M, 1),
  97
  98         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
  99                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 100                       0, 8, BOOKE_PAGESZ_256M, 1),
 101 #endif
 102 };
 103
 104 int num_tlb_entries = ARRAY_SIZE(tlb_table);