4 default " Allwinner Technology"
6 # FIXME: Should not redefine these Kconfig symbols
7 config PRE_CONSOLE_BUFFER
10 config SPL_GPIO_SUPPORT
13 config SPL_LIBCOMMON_SUPPORT
16 config SPL_LIBDISK_SUPPORT
19 config SPL_LIBGENERIC_SUPPORT
22 config SPL_MMC_SUPPORT
23 depends on SPL && GENERIC_MMC
26 config SPL_POWER_SUPPORT
29 config SPL_SERIAL_SUPPORT
32 config SUNXI_HIGH_SRAM
36 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
37 with the first SRAM region being located at address 0.
38 Some newer SoCs map the boot ROM at address 0 instead and move the
39 SRAM to 64KB, just behind the mask ROM.
40 Chips using the latter setup are supposed to select this option to
41 adjust the addresses accordingly.
43 # Note only one of these may be selected at a time! But hidden choices are
44 # not supported by Kconfig
45 config SUNXI_GEN_SUN4I
48 Select this for sunxi SoCs which have resets and clocks set up
49 as the original A10 (mach-sun4i).
51 config SUNXI_GEN_SUN6I
54 Select this for sunxi SoCs which have sun6i like periphery, like
55 separate ahb reset control registers, custom pmic bus, new style
59 config MACH_SUNXI_H3_H5
61 select SUNXI_GEN_SUN6I
65 prompt "Sunxi SoC Variant"
69 bool "sun4i (Allwinner A10)"
71 select ARM_CORTEX_CPU_IS_UP
72 select SUNXI_GEN_SUN4I
76 bool "sun5i (Allwinner A13)"
78 select ARM_CORTEX_CPU_IS_UP
79 select SUNXI_GEN_SUN4I
83 bool "sun6i (Allwinner A31)"
85 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
87 select ARCH_SUPPORT_PSCI
88 select SUNXI_GEN_SUN6I
90 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
93 bool "sun7i (Allwinner A20)"
95 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
97 select ARCH_SUPPORT_PSCI
98 select SUNXI_GEN_SUN4I
100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
102 config MACH_SUN8I_A23
103 bool "sun8i (Allwinner A23)"
105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
107 select ARCH_SUPPORT_PSCI
108 select SUNXI_GEN_SUN6I
110 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
112 config MACH_SUN8I_A33
113 bool "sun8i (Allwinner A33)"
115 select CPU_V7_HAS_NONSEC
116 select CPU_V7_HAS_VIRT
117 select ARCH_SUPPORT_PSCI
118 select SUNXI_GEN_SUN6I
120 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
122 config MACH_SUN8I_A83T
123 bool "sun8i (Allwinner A83T)"
125 select SUNXI_GEN_SUN6I
129 bool "sun8i (Allwinner H3)"
131 select CPU_V7_HAS_NONSEC
132 select CPU_V7_HAS_VIRT
133 select ARCH_SUPPORT_PSCI
134 select MACH_SUNXI_H3_H5
135 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
137 config MACH_SUN8I_R40
138 bool "sun8i (Allwinner R40)"
140 select SUNXI_GEN_SUN6I
144 bool "sun9i (Allwinner A80)"
146 select SUNXI_HIGH_SRAM
147 select SUNXI_GEN_SUN6I
151 bool "sun50i (Allwinner A64)"
153 select SUNXI_GEN_SUN6I
154 select SUNXI_HIGH_SRAM
157 config MACH_SUN50I_H5
158 bool "sun50i (Allwinner H5)"
160 select MACH_SUNXI_H3_H5
161 select SUNXI_HIGH_SRAM
165 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
168 default y if MACH_SUN8I_A23
169 default y if MACH_SUN8I_A33
170 default y if MACH_SUN8I_A83T
171 default y if MACH_SUNXI_H3_H5
172 default y if MACH_SUN8I_R40
174 config RESERVE_ALLWINNER_BOOT0_HEADER
175 bool "reserve space for Allwinner boot0 header"
176 select ENABLE_ARM_SOC_BOOT0_HOOK
178 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
179 filled with magic values post build. The Allwinner provided boot0
180 blob relies on this information to load and execute U-Boot.
181 Only needed on 64-bit Allwinner boards so far when using boot0.
183 config ARM_BOOT_HOOK_RMR
187 select ENABLE_ARM_SOC_BOOT0_HOOK
189 Insert some ARM32 code at the very beginning of the U-Boot binary
190 which uses an RMR register write to bring the core into AArch64 mode.
191 The very first instruction acts as a switch, since it's carefully
192 chosen to be a NOP in one mode and a branch in the other, so the
193 code would only be executed if not already in AArch64.
194 This allows both the SPL and the U-Boot proper to be entered in
195 either mode and switch to AArch64 if needed.
198 int "sunxi dram type"
199 depends on MACH_SUN8I_A83T
202 Set the dram type, 3: DDR3, 7: LPDDR3
205 int "sunxi dram clock speed"
206 default 792 if MACH_SUN9I
207 default 648 if MACH_SUN8I_R40
208 default 312 if MACH_SUN6I || MACH_SUN8I
209 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
210 default 672 if MACH_SUN50I
212 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
213 must be a multiple of 24. For the sun9i (A80), the tested values
214 (for DDR3-1600) are 312 to 792.
216 if MACH_SUN5I || MACH_SUN7I
218 int "sunxi mbus clock speed"
221 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
226 int "sunxi dram zq value"
227 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
228 default 127 if MACH_SUN7I
229 default 3881979 if MACH_SUN8I_R40
230 default 4145117 if MACH_SUN9I
231 default 3881915 if MACH_SUN50I
233 Set the dram zq value.
236 bool "sunxi dram odt enable"
237 default n if !MACH_SUN8I_A23
238 default y if MACH_SUN8I_A23
239 default y if MACH_SUN8I_R40
240 default y if MACH_SUN50I
242 Select this to enable dram odt (on die termination).
244 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
246 int "sunxi dram emr1 value"
247 default 0 if MACH_SUN4I
248 default 4 if MACH_SUN5I || MACH_SUN7I
250 Set the dram controller emr1 value.
253 hex "sunxi dram tpr3 value"
256 Set the dram controller tpr3 parameter. This parameter configures
257 the delay on the command lane and also phase shifts, which are
258 applied for sampling incoming read data. The default value 0
259 means that no phase/delay adjustments are necessary. Properly
260 configuring this parameter increases reliability at high DRAM
263 config DRAM_DQS_GATING_DELAY
264 hex "sunxi dram dqs_gating_delay value"
267 Set the dram controller dqs_gating_delay parmeter. Each byte
268 encodes the DQS gating delay for each byte lane. The delay
269 granularity is 1/4 cycle. For example, the value 0x05060606
270 means that the delay is 5 quarter-cycles for one lane (1.25
271 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
272 The default value 0 means autodetection. The results of hardware
273 autodetection are not very reliable and depend on the chip
274 temperature (sometimes producing different results on cold start
275 and warm reboot). But the accuracy of hardware autodetection
276 is usually good enough, unless running at really high DRAM
277 clocks speeds (up to 600MHz). If unsure, keep as 0.
280 prompt "sunxi dram timings"
281 default DRAM_TIMINGS_VENDOR_MAGIC
283 Select the timings of the DDR3 chips.
285 config DRAM_TIMINGS_VENDOR_MAGIC
286 bool "Magic vendor timings from Android"
288 The same DRAM timings as in the Allwinner boot0 bootloader.
290 config DRAM_TIMINGS_DDR3_1066F_1333H
291 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
293 Use the timings of the standard JEDEC DDR3-1066F speed bin for
294 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
295 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
296 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
297 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
298 that down binning to DDR3-1066F is supported (because DDR3-1066F
299 uses a bit faster timings than DDR3-1333H).
301 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
302 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
304 Use the timings of the slowest possible JEDEC speed bin for the
305 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
306 DDR3-800E, DDR3-1066G or DDR3-1333J.
313 config DRAM_ODT_CORRECTION
314 int "sunxi dram odt correction value"
317 Set the dram odt correction value (range -255 - 255). In allwinner
318 fex files, this option is found in bits 8-15 of the u32 odt_en variable
319 in the [dram] section. When bit 31 of the odt_en variable is set
320 then the correction is negative. Usually the value for this is 0.
324 default 1008000000 if MACH_SUN4I
325 default 1008000000 if MACH_SUN5I
326 default 1008000000 if MACH_SUN6I
327 default 912000000 if MACH_SUN7I
328 default 1008000000 if MACH_SUN8I
329 default 1008000000 if MACH_SUN9I
330 default 816000000 if MACH_SUN50I
332 config SYS_CONFIG_NAME
333 default "sun4i" if MACH_SUN4I
334 default "sun5i" if MACH_SUN5I
335 default "sun6i" if MACH_SUN6I
336 default "sun7i" if MACH_SUN7I
337 default "sun8i" if MACH_SUN8I
338 default "sun9i" if MACH_SUN9I
339 default "sun50i" if MACH_SUN50I
348 bool "UART0 on MicroSD breakout board"
351 Repurpose the SD card slot for getting access to the UART0 serial
352 console. Primarily useful only for low level u-boot debugging on
353 tablets, where normal UART0 is difficult to access and requires
354 device disassembly and/or soldering. As the SD card can't be used
355 at the same time, the system can be only booted in the FEL mode.
356 Only enable this if you really know what you are doing.
358 config OLD_SUNXI_KERNEL_COMPAT
359 bool "Enable workarounds for booting old kernels"
362 Set this to enable various workarounds for old kernels, this results in
363 sub-optimal settings for newer kernels, only enable if needed.
366 string "MAC power pin"
369 Set the pin used to power the MAC. This takes a string in the format
370 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
373 string "Card detect pin for mmc0"
374 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
377 Set the card detect pin for mmc0, leave empty to not use cd. This
378 takes a string in the format understood by sunxi_name_to_gpio, e.g.
379 PH1 for pin 1 of port H.
382 string "Card detect pin for mmc1"
385 See MMC0_CD_PIN help text.
388 string "Card detect pin for mmc2"
391 See MMC0_CD_PIN help text.
394 string "Card detect pin for mmc3"
397 See MMC0_CD_PIN help text.
400 string "Pins for mmc1"
403 Set the pins used for mmc1, when applicable. This takes a string in the
404 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
407 string "Pins for mmc2"
410 See MMC1_PINS help text.
413 string "Pins for mmc3"
416 See MMC1_PINS help text.
418 config MMC_SUNXI_SLOT_EXTRA
419 int "mmc extra slot number"
422 sunxi builds always enable mmc0, some boards also have a second sdcard
423 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
426 config INITIAL_USB_SCAN_DELAY
427 int "delay initial usb scan by x ms to allow builtin devices to init"
430 Some boards have on board usb devices which need longer than the
431 USB spec's 1 second to connect from board powerup. Set this config
432 option to a non 0 value to add an extra delay before the first usb
436 string "Vbus enable pin for usb0 (otg)"
439 Set the Vbus enable pin for usb0 (otg). This takes a string in the
440 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
443 string "Vbus detect pin for usb0 (otg)"
446 Set the Vbus detect pin for usb0 (otg). This takes a string in the
447 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
450 string "ID detect pin for usb0 (otg)"
453 Set the ID detect pin for usb0 (otg). This takes a string in the
454 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
457 string "Vbus enable pin for usb1 (ehci0)"
458 default "PH6" if MACH_SUN4I || MACH_SUN7I
459 default "PH27" if MACH_SUN6I
461 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
462 a string in the format understood by sunxi_name_to_gpio, e.g.
463 PH1 for pin 1 of port H.
466 string "Vbus enable pin for usb2 (ehci1)"
467 default "PH3" if MACH_SUN4I || MACH_SUN7I
468 default "PH24" if MACH_SUN6I
470 See USB1_VBUS_PIN help text.
473 string "Vbus enable pin for usb3 (ehci2)"
476 See USB1_VBUS_PIN help text.
479 bool "Enable I2C/TWI controller 0"
480 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
481 default n if MACH_SUN6I || MACH_SUN8I
484 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
485 its clock and setting up the bus. This is especially useful on devices
486 with slaves connected to the bus or with pins exposed through e.g. an
487 expansion port/header.
490 bool "Enable I2C/TWI controller 1"
494 See I2C0_ENABLE help text.
497 bool "Enable I2C/TWI controller 2"
501 See I2C0_ENABLE help text.
503 if MACH_SUN6I || MACH_SUN7I
505 bool "Enable I2C/TWI controller 3"
509 See I2C0_ENABLE help text.
514 bool "Enable the PRCM I2C/TWI controller"
515 # This is used for the pmic on H3
516 default y if SY8106A_POWER
519 Set this to y to enable the I2C controller which is part of the PRCM.
524 bool "Enable I2C/TWI controller 4"
528 See I2C0_ENABLE help text.
532 bool "Enable support for gpio-s on axp PMICs"
535 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
538 bool "Enable graphical uboot console on HDMI, LCD or VGA"
539 depends on !MACH_SUN8I_A83T
540 depends on !MACH_SUNXI_H3_H5
541 depends on !MACH_SUN8I_R40
542 depends on !MACH_SUN9I
543 depends on !MACH_SUN50I
546 Say Y here to add support for using a cfb console on the HDMI, LCD
547 or VGA output found on most sunxi devices. See doc/README.video for
548 info on how to select the video output and mode.
551 bool "HDMI output support"
552 depends on VIDEO && !MACH_SUN8I
555 Say Y here to add support for outputting video over HDMI.
558 bool "VGA output support"
559 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
562 Say Y here to add support for outputting video over VGA.
564 config VIDEO_VGA_VIA_LCD
565 bool "VGA via LCD controller support"
566 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
569 Say Y here to add support for external DACs connected to the parallel
570 LCD interface driving a VGA connector, such as found on the
573 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
574 bool "Force sync active high for VGA via LCD controller support"
575 depends on VIDEO_VGA_VIA_LCD
578 Say Y here if you've a board which uses opendrain drivers for the vga
579 hsync and vsync signals. Opendrain drivers cannot generate steep enough
580 positive edges for a stable video output, so on boards with opendrain
581 drivers the sync signals must always be active high.
583 config VIDEO_VGA_EXTERNAL_DAC_EN
584 string "LCD panel power enable pin"
585 depends on VIDEO_VGA_VIA_LCD
588 Set the enable pin for the external VGA DAC. This takes a string in the
589 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
591 config VIDEO_COMPOSITE
592 bool "Composite video output support"
593 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
596 Say Y here to add support for outputting composite video.
598 config VIDEO_LCD_MODE
599 string "LCD panel timing details"
603 LCD panel timing details string, leave empty if there is no LCD panel.
604 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
605 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
606 Also see: http://linux-sunxi.org/LCD
608 config VIDEO_LCD_DCLK_PHASE
609 int "LCD panel display clock phase"
613 Select LCD panel display clock phase shift, range 0-3.
615 config VIDEO_LCD_POWER
616 string "LCD panel power enable pin"
620 Set the power enable pin for the LCD panel. This takes a string in the
621 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
623 config VIDEO_LCD_RESET
624 string "LCD panel reset pin"
628 Set the reset pin for the LCD panel. This takes a string in the format
629 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
631 config VIDEO_LCD_BL_EN
632 string "LCD panel backlight enable pin"
636 Set the backlight enable pin for the LCD panel. This takes a string in the
637 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
640 config VIDEO_LCD_BL_PWM
641 string "LCD panel backlight pwm pin"
645 Set the backlight pwm pin for the LCD panel. This takes a string in the
646 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
648 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
649 bool "LCD panel backlight pwm is inverted"
653 Set this if the backlight pwm output is active low.
655 config VIDEO_LCD_PANEL_I2C
656 bool "LCD panel needs to be configured via i2c"
661 Say y here if the LCD panel needs to be configured via i2c. This
662 will add a bitbang i2c controller using gpios to talk to the LCD.
664 config VIDEO_LCD_PANEL_I2C_SDA
665 string "LCD panel i2c interface SDA pin"
666 depends on VIDEO_LCD_PANEL_I2C
669 Set the SDA pin for the LCD i2c interface. This takes a string in the
670 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
672 config VIDEO_LCD_PANEL_I2C_SCL
673 string "LCD panel i2c interface SCL pin"
674 depends on VIDEO_LCD_PANEL_I2C
677 Set the SCL pin for the LCD i2c interface. This takes a string in the
678 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
681 # Note only one of these may be selected at a time! But hidden choices are
682 # not supported by Kconfig
683 config VIDEO_LCD_IF_PARALLEL
686 config VIDEO_LCD_IF_LVDS
691 prompt "LCD panel support"
694 Select which type of LCD panel to support.
696 config VIDEO_LCD_PANEL_PARALLEL
697 bool "Generic parallel interface LCD panel"
698 select VIDEO_LCD_IF_PARALLEL
700 config VIDEO_LCD_PANEL_LVDS
701 bool "Generic lvds interface LCD panel"
702 select VIDEO_LCD_IF_LVDS
704 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
705 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
706 select VIDEO_LCD_SSD2828
707 select VIDEO_LCD_IF_PARALLEL
709 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
711 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
712 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
713 select VIDEO_LCD_ANX9804
714 select VIDEO_LCD_IF_PARALLEL
715 select VIDEO_LCD_PANEL_I2C
717 Select this for eDP LCD panels with 4 lanes running at 1.62G,
718 connected via an ANX9804 bridge chip.
720 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
721 bool "Hitachi tx18d42vm LCD panel"
722 select VIDEO_LCD_HITACHI_TX18D42VM
723 select VIDEO_LCD_IF_LVDS
725 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
727 config VIDEO_LCD_TL059WV5C0
728 bool "tl059wv5c0 LCD panel"
729 select VIDEO_LCD_PANEL_I2C
730 select VIDEO_LCD_IF_PARALLEL
732 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
733 Aigo M60/M608/M606 tablets.
738 string "SATA power pin"
741 Set the pins used to power the SATA. This takes a string in the
742 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
746 int "GMAC Transmit Clock Delay Chain"
749 Set the GMAC Transmit Clock Delay Chain value.
751 config SPL_STACK_R_ADDR
752 default 0x4fe00000 if MACH_SUN4I
753 default 0x4fe00000 if MACH_SUN5I
754 default 0x4fe00000 if MACH_SUN6I
755 default 0x4fe00000 if MACH_SUN7I
756 default 0x4fe00000 if MACH_SUN8I
757 default 0x2fe00000 if MACH_SUN9I
758 default 0x4fe00000 if MACH_SUN50I