git.sur5r.net Git - u-boot/blob - board/tcl/sl50/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TCL SL50 board
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mem.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <i2c.h>
  27 #include <miiphy.h>
  28 #include <cpsw.h>
  29 #include <power/tps65217.h>
  30 #include <power/tps65910.h>
  31 #include <environment.h>
  32 #include <watchdog.h>
  33 #include <environment.h>
  34 #include "board.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39
  40 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  41
  42 static const struct ddr_data ddr3_sl50_data = {
  43         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  44         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  45         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  46         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  47 };
  48
  49 static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
  50         .cmd0csratio = MT41K256M16HA125E_RATIO,
  51         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  52
  53         .cmd1csratio = MT41K256M16HA125E_RATIO,
  54         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  55
  56         .cmd2csratio = MT41K256M16HA125E_RATIO,
  57         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  58 };
  59
  60 static struct emif_regs ddr3_sl50_emif_reg_data = {
  61         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  62         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  63         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  64         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  65         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  66         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  67         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  68 };
  69
  70 #ifdef CONFIG_SPL_OS_BOOT
  71 int spl_start_uboot(void)
  72 {
  73         /* break into full u-boot on 'c' */
  74         if (serial_tstc() && serial_getc() == 'c')
  75                 return 1;
  76
  77 #ifdef CONFIG_SPL_ENV_SUPPORT
  78         env_init();
  79         env_load();
  80         if (getenv_yesno("boot_os") != 1)
  81                 return 1;
  82 #endif
  83
  84         return 0;
  85 }
  86 #endif
  87
  88 #define OSC     (V_OSCK/1000000)
  89 const struct dpll_params dpll_ddr_sl50 = {
  90                 400, OSC-1, 1, -1, -1, -1, -1};
  91
  92 void am33xx_spl_board_init(void)
  93 {
  94         int mpu_vdd;
  95
  96         /* Get the frequency */
  97         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  98
  99         /* BeagleBone PMIC Code */
 100         int usb_cur_lim;
 101
 102         if (i2c_probe(TPS65217_CHIP_PM))
 103                 return;
 104
 105         /*
 106          * Increase USB current limit to 1300mA or 1800mA and set
 107          * the MPU voltage controller as needed.
 108          */
 109         if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 110                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 111                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 112         } else {
 113                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 114                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 115         }
 116
 117         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 118                                TPS65217_POWER_PATH,
 119                                usb_cur_lim,
 120                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 121                 puts("tps65217_reg_write failure\n");
 122
 123         /* Set DCDC3 (CORE) voltage to 1.125V */
 124         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 125                                     TPS65217_DCDC_VOLT_SEL_1125MV)) {
 126                 puts("tps65217_voltage_update failure\n");
 127                 return;
 128         }
 129
 130         /* Set CORE Frequencies to OPP100 */
 131         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 132
 133         /* Set DCDC2 (MPU) voltage */
 134         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 135                 puts("tps65217_voltage_update failure\n");
 136                 return;
 137         }
 138
 139         /*
 140          * Set LDO3 to 1.8V and LDO4 to 3.3V
 141          */
 142         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 143                                TPS65217_DEFLS1,
 144                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 145                                TPS65217_LDO_MASK))
 146                 puts("tps65217_reg_write failure\n");
 147
 148         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 149                                TPS65217_DEFLS2,
 150                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 151                                TPS65217_LDO_MASK))
 152                 puts("tps65217_reg_write failure\n");
 153
 154         /* Set MPU Frequency to what we detected now that voltages are set */
 155         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 156 }
 157
 158 const struct dpll_params *get_dpll_ddr_params(void)
 159 {
 160         enable_i2c0_pin_mux();
 161         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 162
 163         return &dpll_ddr_sl50;
 164 }
 165
 166 void set_uart_mux_conf(void)
 167 {
 168 #if CONFIG_CONS_INDEX == 1
 169         enable_uart0_pin_mux();
 170 #elif CONFIG_CONS_INDEX == 2
 171         enable_uart1_pin_mux();
 172 #elif CONFIG_CONS_INDEX == 3
 173         enable_uart2_pin_mux();
 174 #elif CONFIG_CONS_INDEX == 4
 175         enable_uart3_pin_mux();
 176 #elif CONFIG_CONS_INDEX == 5
 177         enable_uart4_pin_mux();
 178 #elif CONFIG_CONS_INDEX == 6
 179         enable_uart5_pin_mux();
 180 #endif
 181 }
 182
 183 void set_mux_conf_regs(void)
 184 {
 185         enable_board_pin_mux();
 186 }
 187
 188 const struct ctrl_ioregs ioregs_evmsk = {
 189         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 190         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 191         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 192         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 193         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 194 };
 195
 196 const struct ctrl_ioregs ioregs_bonelt = {
 197         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 198         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 199         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 200         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 201         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 202 };
 203
 204 const struct ctrl_ioregs ioregs_evm15 = {
 205         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 206         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 207         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 208         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 209         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 210 };
 211
 212 const struct ctrl_ioregs ioregs = {
 213         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 214         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 215         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 216         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 217         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 218 };
 219
 220 void sdram_init(void)
 221 {
 222         config_ddr(400, &ioregs_bonelt,
 223                    &ddr3_sl50_data,
 224                    &ddr3_sl50_cmd_ctrl_data,
 225                    &ddr3_sl50_emif_reg_data, 0);
 226 }
 227 #endif
 228
 229 /*
 230  * Basic board specific setup.  Pinmux has been handled already.
 231  */
 232 int board_init(void)
 233 {
 234 #if defined(CONFIG_HW_WATCHDOG)
 235         hw_watchdog_init();
 236 #endif
 237
 238         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 239         return 0;
 240 }
 241
 242 #ifdef CONFIG_BOARD_LATE_INIT
 243 int board_late_init(void)
 244 {
 245         return 0;
 246 }
 247 #endif
 248
 249 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 250         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 251 static void cpsw_control(int enabled)
 252 {
 253         /* VTP can be added here */
 254
 255         return;
 256 }
 257
 258 static struct cpsw_slave_data cpsw_slaves[] = {
 259         {
 260                 .slave_reg_ofs  = 0x208,
 261                 .sliver_reg_ofs = 0xd80,
 262                 .phy_addr       = 0,
 263         },
 264         {
 265                 .slave_reg_ofs  = 0x308,
 266                 .sliver_reg_ofs = 0xdc0,
 267                 .phy_addr       = 1,
 268         },
 269 };
 270
 271 static struct cpsw_platform_data cpsw_data = {
 272         .mdio_base              = CPSW_MDIO_BASE,
 273         .cpsw_base              = CPSW_BASE,
 274         .mdio_div               = 0xff,
 275         .channels               = 8,
 276         .cpdma_reg_ofs          = 0x800,
 277         .slaves                 = 1,
 278         .slave_data             = cpsw_slaves,
 279         .ale_reg_ofs            = 0xd00,
 280         .ale_entries            = 1024,
 281         .host_port_reg_ofs      = 0x108,
 282         .hw_stats_reg_ofs       = 0x900,
 283         .bd_ram_ofs             = 0x2000,
 284         .mac_control            = (1 << 5),
 285         .control                = cpsw_control,
 286         .host_port_num          = 0,
 287         .version                = CPSW_CTRL_VERSION_2,
 288 };
 289 #endif
 290
 291 /*
 292  * This function will:
 293  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 294  * in the environment
 295  * Perform fixups to the PHY present on certain boards.  We only need this
 296  * function in:
 297  * - SPL with either CPSW or USB ethernet support
 298  * - Full U-Boot, with either CPSW or USB ethernet
 299  * Build in only these cases to avoid warnings about unused variables
 300  * when we build an SPL that has neither option but full U-Boot will.
 301  */
 302 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
 303                 && defined(CONFIG_SPL_BUILD)) || \
 304         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 305           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 306          !defined(CONFIG_SPL_BUILD))
 307 int board_eth_init(bd_t *bis)
 308 {
 309         int rv, n = 0;
 310         uint8_t mac_addr[6];
 311         uint32_t mac_hi, mac_lo;
 312
 313         /* try reading mac address from efuse */
 314         mac_lo = readl(&cdev->macid0l);
 315         mac_hi = readl(&cdev->macid0h);
 316         mac_addr[0] = mac_hi & 0xFF;
 317         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 318         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 319         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 320         mac_addr[4] = mac_lo & 0xFF;
 321         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 322
 323 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 324         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 325         if (!env_get("ethaddr")) {
 326                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 327
 328                 if (is_valid_ethaddr(mac_addr))
 329                         eth_env_set_enetaddr("ethaddr", mac_addr);
 330         }
 331
 332 #ifdef CONFIG_DRIVER_TI_CPSW
 333
 334         mac_lo = readl(&cdev->macid1l);
 335         mac_hi = readl(&cdev->macid1h);
 336         mac_addr[0] = mac_hi & 0xFF;
 337         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 338         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 339         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 340         mac_addr[4] = mac_lo & 0xFF;
 341         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 342
 343         if (!env_get("eth1addr")) {
 344                 if (is_valid_ethaddr(mac_addr))
 345                         eth_env_set_enetaddr("eth1addr", mac_addr);
 346         }
 347
 348
 349         writel(MII_MODE_ENABLE, &cdev->miisel);
 350         cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 351                                 PHY_INTERFACE_MODE_MII;
 352
 353         rv = cpsw_register(&cpsw_data);
 354         if (rv < 0)
 355                 printf("Error %d registering CPSW switch\n", rv);
 356         else
 357                 n += rv;
 358 #endif
 359
 360         /*
 361          *
 362          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 363          * operating points.  So we must set the TX clock delay feature
 364          * in the AR8051 PHY.  Since we only support a single ethernet
 365          * device in U-Boot, we only do this for the first instance.
 366          */
 367 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 368 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 369 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 370 #define AR8051_RGMII_TX_CLK_DLY         0x100
 371
 372 #endif
 373 #if defined(CONFIG_USB_ETHER) && \
 374         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 375         if (is_valid_ether_addr(mac_addr))
 376                 eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
 377
 378         rv = usb_eth_initialize(bis);
 379         if (rv < 0)
 380                 printf("Error %d registering USB_ETHER\n", rv);
 381         else
 382                 n += rv;
 383 #endif
 384         return n;
 385 }
 386 #endif