git.sur5r.net Git - u-boot/blob - board/toradex/colibri_pxa270/colibri_pxa270.c

   1 /*
   2  * Toradex Colibri PXA270 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/regs-mmc.h>
  12 #include <asm/arch/pxa.h>
  13 #include <netdev.h>
  14 #include <asm/io.h>
  15 #include <serial.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 int board_init(void)
  20 {
  21         /* We have RAM, disable cache */
  22         dcache_disable();
  23         icache_disable();
  24
  25         /* arch number of vpac270 */
  26         gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
  27
  28         /* adress of boot parameters */
  29         gd->bd->bi_boot_params = 0xa0000100;
  30
  31         return 0;
  32 }
  33
  34 int dram_init(void)
  35 {
  36         pxa2xx_dram_init();
  37         gd->ram_size = PHYS_SDRAM_1_SIZE;
  38         return 0;
  39 }
  40
  41 #ifdef  CONFIG_CMD_USB
  42 int usb_board_init(void)
  43 {
  44         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  45                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  46                 UHCHR);
  47
  48         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  49
  50         while (UHCHR & UHCHR_FSBIR)
  51                 ;
  52
  53         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  54         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  55
  56         /* Clear any OTG Pin Hold */
  57         if (readl(PSSR) & PSSR_OTGPH)
  58                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  59
  60         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  61         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  62
  63         /* Set port power control mask bits, only 3 ports. */
  64         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  65
  66         /* enable port 2 */
  67         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  68                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  69
  70         return 0;
  71 }
  72
  73 void usb_board_init_fail(void)
  74 {
  75         return;
  76 }
  77
  78 void usb_board_stop(void)
  79 {
  80         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
  81         udelay(11);
  82         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
  83
  84         writel(readl(UHCCOMS) | 1, UHCCOMS);
  85         udelay(10);
  86
  87         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
  88
  89         return;
  90 }
  91 #endif
  92
  93 #ifdef CONFIG_DRIVER_DM9000
  94 int board_eth_init(bd_t *bis)
  95 {
  96         return dm9000_initialize(bis);
  97 }
  98 #endif
  99
 100 #ifdef  CONFIG_CMD_MMC
 101 int board_mmc_init(bd_t *bis)
 102 {
 103         pxa_mmc_register(0);
 104         return 0;
 105 }
 106 #endif