2 * Copyright 2005 DENX Software Engineering
3 * Copyright 2004 Freescale Semiconductor.
4 * (C) Copyright 2002,2003, Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
7 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
35 #if defined(CONFIG_DDR_ECC)
36 extern void ddr_enable_ecc (unsigned int dram_size);
39 extern long int spd_sdram (void);
41 void local_bus_init (void);
42 long int fixed_sdram (void);
45 int board_early_init_f (void)
52 puts ("Board: TQM8540\n");
55 printf ("PCI1: 32 bit, %d MHz (compiled)\n",
56 CONFIG_SYS_CLK_FREQ / 1000000);
58 printf ("PCI1: disabled\n");
61 * Initialize local bus.
69 long int initdram (int board_type)
72 extern long spd_sdram (void);
73 volatile immap_t *immap = (immap_t *) CFG_IMMR;
75 #if defined(CONFIG_DDR_DLL)
77 volatile ccsr_gur_t *gur = &immap->im_gur;
81 * Work around to stabilize DDR DLL
83 temp_ddrdll = gur->ddrdllcr;
84 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
85 asm ("sync;isync;msync");
89 #if defined(CONFIG_SPD_EEPROM)
90 dram_size = spd_sdram ();
92 dram_size = fixed_sdram ();
95 #if defined(CONFIG_DDR_ECC)
97 * Initialize and enable DDR ECC.
99 ddr_enable_ecc (dram_size);
107 * Initialize Local Bus
110 void local_bus_init (void)
112 volatile immap_t *immap = (immap_t *) CFG_IMMR;
113 volatile ccsr_gur_t *gur = &immap->im_gur;
114 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
122 * Fix Local Bus clock glitch when DLL is enabled.
124 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
125 * If localbus freq is > 133Mhz, DLL can be safely enabled.
126 * Between 66 and 133, the DLL is enabled with an override workaround.
129 get_sys_info (&sysinfo);
130 clkdiv = lbc->lcrr & 0x0f;
131 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
134 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
135 lbc->ltedr = 0xa4c80000; /* DK: !!! */
137 } else if (lbc_hz >= 133) {
138 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
142 * On REV1 boards, need to change CLKDIV before enable DLL.
143 * Default CLKDIV is 8, change it to 4 temporarily.
145 uint pvr = get_pvr ();
146 uint temp_lbcdll = 0;
148 if (pvr == PVR_85xx_REV1) {
149 /* FIXME: Justify the high bit here. */
150 lbc->lcrr = 0x10000004;
153 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
157 * Sample LBC DLL ctrl reg, upshift it to set the
160 temp_lbcdll = gur->lbcdllcr;
161 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
162 asm ("sync;isync;msync");
167 #if defined(CFG_DRAM_TEST)
170 uint *pstart = (uint *) CFG_MEMTEST_START;
171 uint *pend = (uint *) CFG_MEMTEST_END;
174 printf ("SDRAM test phase 1:\n");
175 for (p = pstart; p < pend; p++)
178 for (p = pstart; p < pend; p++) {
179 if (*p != 0xaaaaaaaa) {
180 printf ("SDRAM test fails at: %08x\n", (uint) p);
185 printf ("SDRAM test phase 2:\n");
186 for (p = pstart; p < pend; p++)
189 for (p = pstart; p < pend; p++) {
190 if (*p != 0x55555555) {
191 printf ("SDRAM test fails at: %08x\n", (uint) p);
196 printf ("SDRAM test passed.\n");
202 #if !defined(CONFIG_SPD_EEPROM)
203 /*************************************************************************
204 * fixed sdram init -- doesn't use serial presence detect.
205 ************************************************************************/
206 long int fixed_sdram (void)
209 volatile immap_t *immap = (immap_t *) CFG_IMMR;
210 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
212 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
213 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
214 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
215 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
216 ddr->sdram_mode = CFG_DDR_MODE;
217 ddr->sdram_interval = CFG_DDR_INTERVAL;
218 ddr->err_disable = 0x0000000D;
219 #if defined (CONFIG_DDR_ECC)
220 ddr->err_disable = 0x0000000D;
221 ddr->err_sbe = 0x00ff0000;
223 asm ("sync;isync;msync");
225 #if defined (CONFIG_DDR_ECC)
226 /* Enable ECC checking */
227 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
229 ddr->sdram_cfg = CFG_DDR_CONTROL;
231 asm ("sync; isync; msync");
234 return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
236 #endif /* !defined(CONFIG_SPD_EEPROM) */
239 #if defined(CONFIG_PCI)
241 * Initialize PCI Devices, report devices found.
244 #ifndef CONFIG_PCI_PNP
245 static struct pci_config_table pci_mpc85xxads_config_table[] = {
246 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
247 PCI_IDSEL_NUMBER, PCI_ANY_ID,
248 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
251 PCI_COMMAND_MASTER}},
257 static struct pci_controller hose = {
258 #ifndef CONFIG_PCI_PNP
259 config_table:pci_mpc85xxads_config_table,
263 #endif /* CONFIG_PCI */
266 void pci_init_board (void)
269 extern void pci_mpc85xx_init (struct pci_controller *hose);
271 pci_mpc85xx_init (&hose);
272 #endif /* CONFIG_PCI */