git.sur5r.net Git - u-boot/blob - board/varisys/cyrus/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Author: Adrian Cox
   4  * Based on corenet_ds tlb code
   5  */
   6
   7 #include <common.h>
   8 #include <asm/mmu.h>
   9
  10 struct fsl_e_tlb_entry tlb_table[] = {
  11         /* TLB 0 - for temp stack in cache */
  12         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  13                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  14                       MAS3_SW|MAS3_SR, 0,
  15                       0, 0, BOOKE_PAGESZ_4K, 0),
  16         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  17                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  18                       MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  22                       MAS3_SW|MAS3_SR, 0,
  23                       0, 0, BOOKE_PAGESZ_4K, 0),
  24         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  26                       MAS3_SW|MAS3_SR, 0,
  27                       0, 0, BOOKE_PAGESZ_4K, 0),
  28
  29         /* TLB 1 */
  30         /* *I*** - Covers boot page */
  31 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  32         /*
  33          * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  34          * SRAM is at 0xfff00000, it covered the 0xfffff000.
  35          */
  36         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  37                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38                         0, 0, BOOKE_PAGESZ_1M, 1),
  39 #else
  40         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  41                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  42                       0, 0, BOOKE_PAGESZ_4K, 1),
  43 #endif
  44
  45         /* *I*G* - CCSRBAR */
  46         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  47                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48                       0, 1, BOOKE_PAGESZ_16M, 1),
  49
  50         /* Local Bus */
  51         SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS,
  52                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  53                       0, 2, BOOKE_PAGESZ_64K, 1),
  54         SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS,
  55                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56                       0, 3, BOOKE_PAGESZ_4K, 1),
  57
  58         /* *I*G* - PCI */
  59         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  60                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61                       0, 4, BOOKE_PAGESZ_1G, 1),
  62
  63         /* *I*G* - PCI */
  64         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  65                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  66                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  67                       0, 5, BOOKE_PAGESZ_256M, 1),
  68
  69         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  70                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  71                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  72                       0, 6, BOOKE_PAGESZ_256M, 1),
  73
  74         /* *I*G* - PCI I/O */
  75         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  76                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77                       0, 7, BOOKE_PAGESZ_256K, 1),
  78
  79         /* Bman/Qman */
  80 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  81         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  82                       MAS3_SW|MAS3_SR, 0,
  83                       0, 9, BOOKE_PAGESZ_1M, 1),
  84         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
  85                       CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
  86                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87                       0, 10, BOOKE_PAGESZ_1M, 1),
  88 #endif
  89 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  90         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  91                       MAS3_SW|MAS3_SR, 0,
  92                       0, 11, BOOKE_PAGESZ_1M, 1),
  93         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
  94                       CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
  95                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  96                       0, 12, BOOKE_PAGESZ_1M, 1),
  97 #endif
  98 #ifdef CONFIG_SYS_DCSRBAR_PHYS
  99         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 100                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 101                       0, 13, BOOKE_PAGESZ_4M, 1),
 102 #endif
 103 };
 104
 105 int num_tlb_entries = ARRAY_SIZE(tlb_table);