git.sur5r.net Git - u-boot/blob - board/xilinx/zynqmp/zynqmp.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <sata.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <malloc.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/io.h>
  17 #include <usb.h>
  18 #include <dwc3-uboot.h>
  19 #include <zynqmppl.h>
  20 #include <i2c.h>
  21 #include <g_dnl.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  26     !defined(CONFIG_SPL_BUILD)
  27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  28
  29 static const struct {
  30         uint32_t id;
  31         char *name;
  32 } zynqmp_devices[] = {
  33         {
  34                 .id = 0x10,
  35                 .name = "3eg",
  36         },
  37         {
  38                 .id = 0x11,
  39                 .name = "2eg",
  40         },
  41         {
  42                 .id = 0x20,
  43                 .name = "5ev",
  44         },
  45         {
  46                 .id = 0x21,
  47                 .name = "4ev",
  48         },
  49         {
  50                 .id = 0x30,
  51                 .name = "7ev",
  52         },
  53         {
  54                 .id = 0x38,
  55                 .name = "9eg",
  56         },
  57         {
  58                 .id = 0x39,
  59                 .name = "6eg",
  60         },
  61         {
  62                 .id = 0x40,
  63                 .name = "11eg",
  64         },
  65         {
  66                 .id = 0x50,
  67                 .name = "15eg",
  68         },
  69         {
  70                 .id = 0x58,
  71                 .name = "19eg",
  72         },
  73         {
  74                 .id = 0x59,
  75                 .name = "17eg",
  76         },
  77 };
  78
  79 static int chip_id(unsigned char id)
  80 {
  81         struct pt_regs regs;
  82         regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
  83         regs.regs[1] = 0;
  84         regs.regs[2] = 0;
  85         regs.regs[3] = 0;
  86         int val = -EINVAL;
  87
  88         smc_call(&regs);
  89
  90         /*
  91          * SMC returns:
  92          * regs[0][31:0]  = status of the operation
  93          * regs[0][63:32] = CSU.IDCODE register
  94          * regs[1][31:0]  = CSU.version register
  95          */
  96         switch (id) {
  97         case IDCODE:
  98                 regs.regs[0] = upper_32_bits(regs.regs[0]);
  99                 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 100                                 ZYNQMP_CSU_IDCODE_SVD_MASK;
 101                 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 102                 val = regs.regs[0];
 103                 break;
 104         case VERSION:
 105                 regs.regs[1] = lower_32_bits(regs.regs[1]);
 106                 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 107                 val = regs.regs[1];
 108                 break;
 109         default:
 110                 printf("%s, Invalid Req:0x%x\n", __func__, id);
 111         }
 112
 113         return val;
 114 }
 115
 116 static char *zynqmp_get_silicon_idcode_name(void)
 117 {
 118         uint32_t i, id;
 119
 120         id = chip_id(IDCODE);
 121         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 122                 if (zynqmp_devices[i].id == id)
 123                         return zynqmp_devices[i].name;
 124         }
 125         return "unknown";
 126 }
 127 #endif
 128
 129 int board_early_init_f(void)
 130 {
 131 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 132         zynqmp_pmufw_version();
 133 #endif
 134
 135 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 136         psu_init();
 137 #endif
 138
 139         return 0;
 140 }
 141
 142 #define ZYNQMP_VERSION_SIZE     9
 143
 144 int board_init(void)
 145 {
 146         printf("EL Level:\tEL%d\n", current_el());
 147
 148 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 149     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 150     defined(CONFIG_SPL_BUILD))
 151         if (current_el() != 3) {
 152                 static char version[ZYNQMP_VERSION_SIZE];
 153
 154                 strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
 155                 zynqmppl.name = strncat(version,
 156                                         zynqmp_get_silicon_idcode_name(),
 157                                         ZYNQMP_VERSION_SIZE);
 158                 printf("Chip ID:\t%s\n", zynqmppl.name);
 159                 fpga_init();
 160                 fpga_add(fpga_xilinx, &zynqmppl);
 161         }
 162 #endif
 163
 164         return 0;
 165 }
 166
 167 int board_early_init_r(void)
 168 {
 169         u32 val;
 170
 171         val = readl(&crlapb_base->timestamp_ref_ctrl);
 172         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 173
 174         if (current_el() == 3 && !val) {
 175                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 176                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 177                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 178
 179                 /* Program freq register in System counter */
 180                 writel(zynqmp_get_system_timer_freq(),
 181                        &iou_scntr_secure->base_frequency_id_register);
 182                 /* And enable system counter */
 183                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 184                        &iou_scntr_secure->counter_control_register);
 185         }
 186         return 0;
 187 }
 188
 189 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 190 {
 191 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 192     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 193     defined(CONFIG_ZYNQ_EEPROM_BUS)
 194         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 195
 196         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 197                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 198                         ethaddr, 6))
 199                 printf("I2C EEPROM MAC address read failed\n");
 200 #endif
 201
 202         return 0;
 203 }
 204
 205 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 206 int dram_init_banksize(void)
 207 {
 208         fdtdec_setup_memory_banksize();
 209
 210         return 0;
 211 }
 212
 213 int dram_init(void)
 214 {
 215         if (fdtdec_setup_memory_size() != 0)
 216                 return -EINVAL;
 217
 218         return 0;
 219 }
 220 #else
 221 int dram_init(void)
 222 {
 223         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 224
 225         return 0;
 226 }
 227 #endif
 228
 229 void reset_cpu(ulong addr)
 230 {
 231 }
 232
 233 int board_late_init(void)
 234 {
 235         u32 reg = 0;
 236         u8 bootmode;
 237         const char *mode;
 238         char *new_targets;
 239
 240         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 241                 debug("Saved variables - Skipping\n");
 242                 return 0;
 243         }
 244
 245         reg = readl(&crlapb_base->boot_mode);
 246         if (reg >> BOOT_MODE_ALT_SHIFT)
 247                 reg >>= BOOT_MODE_ALT_SHIFT;
 248
 249         bootmode = reg & BOOT_MODES_MASK;
 250
 251         puts("Bootmode: ");
 252         switch (bootmode) {
 253         case USB_MODE:
 254                 puts("USB_MODE\n");
 255                 mode = "usb";
 256                 break;
 257         case JTAG_MODE:
 258                 puts("JTAG_MODE\n");
 259                 mode = "pxe dhcp";
 260                 break;
 261         case QSPI_MODE_24BIT:
 262         case QSPI_MODE_32BIT:
 263                 mode = "qspi0";
 264                 puts("QSPI_MODE\n");
 265                 break;
 266         case EMMC_MODE:
 267                 puts("EMMC_MODE\n");
 268                 mode = "mmc0";
 269                 break;
 270         case SD_MODE:
 271                 puts("SD_MODE\n");
 272                 mode = "mmc0";
 273                 break;
 274         case SD1_LSHFT_MODE:
 275                 puts("LVL_SHFT_");
 276                 /* fall through */
 277         case SD_MODE1:
 278                 puts("SD_MODE1\n");
 279 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
 280                 mode = "mmc1";
 281 #else
 282                 mode = "mmc0";
 283 #endif
 284                 break;
 285         case NAND_MODE:
 286                 puts("NAND_MODE\n");
 287                 mode = "nand0";
 288                 break;
 289         default:
 290                 mode = "";
 291                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 292                 break;
 293         }
 294
 295         /*
 296          * One terminating char + one byte for space between mode
 297          * and default boot_targets
 298          */
 299         new_targets = calloc(1, strlen(mode) +
 300                                 strlen(getenv("boot_targets")) + 2);
 301
 302         sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
 303         setenv("boot_targets", new_targets);
 304
 305         return 0;
 306 }
 307
 308 int checkboard(void)
 309 {
 310         puts("Board: Xilinx ZynqMP\n");
 311         return 0;
 312 }
 313
 314 #ifdef CONFIG_USB_DWC3
 315 static struct dwc3_device dwc3_device_data0 = {
 316         .maximum_speed = USB_SPEED_HIGH,
 317         .base = ZYNQMP_USB0_XHCI_BASEADDR,
 318         .dr_mode = USB_DR_MODE_PERIPHERAL,
 319         .index = 0,
 320 };
 321
 322 static struct dwc3_device dwc3_device_data1 = {
 323         .maximum_speed = USB_SPEED_HIGH,
 324         .base = ZYNQMP_USB1_XHCI_BASEADDR,
 325         .dr_mode = USB_DR_MODE_PERIPHERAL,
 326         .index = 1,
 327 };
 328
 329 int usb_gadget_handle_interrupts(int index)
 330 {
 331         dwc3_uboot_handle_interrupt(index);
 332         return 0;
 333 }
 334
 335 int board_usb_init(int index, enum usb_init_type init)
 336 {
 337         debug("%s: index %x\n", __func__, index);
 338
 339 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
 340         g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
 341 #endif
 342
 343         switch (index) {
 344         case 0:
 345                 return dwc3_uboot_init(&dwc3_device_data0);
 346         case 1:
 347                 return dwc3_uboot_init(&dwc3_device_data1);
 348         };
 349
 350         return -1;
 351 }
 352
 353 int board_usb_cleanup(int index, enum usb_init_type init)
 354 {
 355         dwc3_uboot_exit(index);
 356         return 0;
 357 }
 358 #endif