git.sur5r.net Git - u-boot/blob - configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig

   1 CONFIG_PPC=y
   2 CONFIG_SYS_TEXT_BASE=0x11000000
   3 CONFIG_SECURE_BOOT=y
   4 CONFIG_MPC85xx=y
   5 CONFIG_TARGET_C29XPCIE=y
   6 # CONFIG_SYS_MALLOC_F is not set
   7 CONFIG_FIT=y
   8 CONFIG_FIT_VERBOSE=y
   9 CONFIG_OF_BOARD_SETUP=y
  10 CONFIG_OF_STDOUT_VIA_ALIAS=y
  11 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
  12 CONFIG_BOOTDELAY=-1
  13 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  14 CONFIG_BOARD_EARLY_INIT_R=y
  15 CONFIG_HUSH_PARSER=y
  16 CONFIG_CMD_IMLS=y
  17 CONFIG_CMD_EEPROM=y
  18 CONFIG_CMD_I2C=y
  19 CONFIG_CMD_SF=y
  20 CONFIG_CMD_MII=y
  21 CONFIG_CMD_PING=y
  22 CONFIG_DOS_PARTITION=y
  23 CONFIG_DM=y
  24 # CONFIG_MMC is not set
  25 CONFIG_MTD_NOR_FLASH=y
  26 CONFIG_SPI_FLASH=y
  27 CONFIG_SPI_FLASH_EON=y
  28 CONFIG_SPI_FLASH_SPANSION=y
  29 CONFIG_PHY_MARVELL=y
  30 CONFIG_NETDEVICES=y
  31 CONFIG_PHY_GIGE=y
  32 CONFIG_E1000=y
  33 CONFIG_TSEC_ENET=y
  34 CONFIG_SYS_NS16550=y
  35 CONFIG_SPI=y
  36 CONFIG_FSL_ESPI=y
  37 CONFIG_RSA=y
  38 CONFIG_SPL_RSA=y
  39 CONFIG_RSA_SOFTWARE_EXP=y
  40 CONFIG_OF_LIBFDT=y