git.sur5r.net Git - u-boot/blob - configs/socfpga_is1_defconfig

   1 CONFIG_ARM=y
   2 CONFIG_ARCH_SOCFPGA=y
   3 CONFIG_SYS_TEXT_BASE=0x01000040
   4 CONFIG_SYS_MALLOC_F_LEN=0x2000
   5 CONFIG_TARGET_SOCFPGA_IS1=y
   6 CONFIG_SPL=y
   7 CONFIG_SPL_STACK_R_ADDR=0x00800000
   8 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
   9 CONFIG_DISTRO_DEFAULTS=y
  10 CONFIG_FIT=y
  11 CONFIG_USE_BOOTARGS=y
  12 CONFIG_BOOTARGS="console=ttyS0,115200"
  13 # CONFIG_USE_BOOTCOMMAND is not set
  14 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  15 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
  16 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
  17 CONFIG_VERSION_VARIABLE=y
  18 # CONFIG_DISPLAY_BOARDINFO is not set
  19 CONFIG_DISPLAY_BOARDINFO_LATE=y
  20 CONFIG_SPL_STACK_R=y
  21 CONFIG_SPL_SPI_LOAD=y
  22 CONFIG_CMD_ASKENV=y
  23 CONFIG_CMD_GREPENV=y
  24 # CONFIG_CMD_FLASH is not set
  25 CONFIG_CMD_GPIO=y
  26 CONFIG_CMD_I2C=y
  27 CONFIG_CMD_SF=y
  28 CONFIG_CMD_SPI=y
  29 CONFIG_CMD_CACHE=y
  30 CONFIG_CMD_TIME=y
  31 CONFIG_CMD_EXT4_WRITE=y
  32 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
  33 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
  34 CONFIG_CMD_UBI=y
  35 # CONFIG_ISO_PARTITION is not set
  36 # CONFIG_EFI_PARTITION is not set
  37 CONFIG_ENV_IS_IN_SPI_FLASH=y
  38 CONFIG_SPL_DM=y
  39 CONFIG_SPL_DM_SEQ_ALIAS=y
  40 CONFIG_BOOTCOUNT_LIMIT=y
  41 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
  42 CONFIG_FPGA_SOCFPGA=y
  43 CONFIG_DM_GPIO=y
  44 CONFIG_DWAPB_GPIO=y
  45 CONFIG_DM_I2C=y
  46 CONFIG_SYS_I2C_DW=y
  47 # CONFIG_MMC is not set
  48 CONFIG_SPI_FLASH=y
  49 CONFIG_SPI_FLASH_BAR=y
  50 CONFIG_SPI_FLASH_STMICRO=y
  51 CONFIG_PHY_MICREL=y
  52 CONFIG_PHY_MICREL_KSZ90X1=y
  53 CONFIG_DM_ETH=y
  54 CONFIG_ETH_DESIGNWARE=y
  55 CONFIG_DM_RESET=y
  56 CONFIG_SPI=y
  57 CONFIG_CADENCE_QSPI=y