git.sur5r.net Git - u-boot/blob - configs/xilinx_zynqmp_zc1275_revB_defconfig

   1 CONFIG_ARM=y
   2 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1275_revB"
   3 CONFIG_ARCH_ZYNQMP=y
   4 CONFIG_SYS_TEXT_BASE=0x8000000
   5 CONFIG_SYS_MALLOC_F_LEN=0x8000
   6 # CONFIG_SPL_LIBDISK_SUPPORT is not set
   7 CONFIG_SPL=y
   8 CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1275 revB"
   9 # CONFIG_SPL_FAT_SUPPORT is not set
  10 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB"
  11 CONFIG_DEBUG_UART=y
  12 CONFIG_DISTRO_DEFAULTS=y
  13 CONFIG_FIT=y
  14 CONFIG_FIT_VERBOSE=y
  15 CONFIG_SPL_LOAD_FIT=y
  16 # CONFIG_DISPLAY_CPUINFO is not set
  17 # CONFIG_DISPLAY_BOARDINFO is not set
  18 CONFIG_SPL_OS_BOOT=y
  19 CONFIG_SPL_RAM_SUPPORT=y
  20 CONFIG_SPL_RAM_DEVICE=y
  21 CONFIG_SPL_ATF=y
  22 CONFIG_SYS_PROMPT="ZynqMP> "
  23 CONFIG_CMD_MEMTEST=y
  24 CONFIG_CMD_CLK=y
  25 # CONFIG_CMD_FLASH is not set
  26 CONFIG_CMD_FPGA_LOADBP=y
  27 CONFIG_CMD_FPGA_LOADP=y
  28 CONFIG_CMD_MMC=y
  29 # CONFIG_CMD_NET is not set
  30 CONFIG_CMD_TIME=y
  31 CONFIG_CMD_TIMER=y
  32 CONFIG_SPL_OF_CONTROL=y
  33 CONFIG_OF_EMBED=y
  34 CONFIG_SPL_DM=y
  35 CONFIG_CLK_ZYNQMP=y
  36 CONFIG_FPGA_XILINX=y
  37 CONFIG_FPGA_ZYNQMPPL=y
  38 CONFIG_MISC=y
  39 CONFIG_DM_MMC=y
  40 CONFIG_MMC_SDHCI=y
  41 CONFIG_MMC_SDHCI_ZYNQ=y
  42 CONFIG_SPI_FLASH=y
  43 CONFIG_SPI_FLASH_BAR=y
  44 CONFIG_SF_DUAL_FLASH=y
  45 CONFIG_SPI_FLASH_MACRONIX=y
  46 CONFIG_SPI_FLASH_SPANSION=y
  47 CONFIG_SPI_FLASH_STMICRO=y
  48 CONFIG_SPI_FLASH_WINBOND=y
  49 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  50 CONFIG_DEBUG_UART_ZYNQ=y
  51 CONFIG_DEBUG_UART_BASE=0xff000000
  52 CONFIG_DEBUG_UART_CLOCK=100000000
  53 CONFIG_DEBUG_UART_ANNOUNCE=y
  54 CONFIG_ZYNQ_SERIAL=y
  55 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y