git.sur5r.net Git - u-boot/blob - configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig

   1 CONFIG_ARM=y
   2 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
   3 CONFIG_ARCH_ZYNQMP=y
   4 CONFIG_SYS_TEXT_BASE=0x8000000
   5 CONFIG_SYS_MALLOC_F_LEN=0x8000
   6 CONFIG_SPL=y
   7 CONFIG_DEBUG_UART_BASE=0xff000000
   8 CONFIG_DEBUG_UART_CLOCK=100000000
   9 CONFIG_DEFINE_TCM_OCM_MMAP=y
  10 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
  11 CONFIG_DEBUG_UART=y
  12 CONFIG_DISTRO_DEFAULTS=y
  13 CONFIG_FIT=y
  14 CONFIG_FIT_VERBOSE=y
  15 CONFIG_SPL_LOAD_FIT=y
  16 # CONFIG_DISPLAY_CPUINFO is not set
  17 CONFIG_BOARD_EARLY_INIT_R=y
  18 CONFIG_SPL_OS_BOOT=y
  19 CONFIG_SPL_RAM_SUPPORT=y
  20 CONFIG_SPL_RAM_DEVICE=y
  21 CONFIG_SPL_ATF=y
  22 CONFIG_SYS_PROMPT="ZynqMP> "
  23 CONFIG_CMD_MEMTEST=y
  24 CONFIG_SYS_ALT_MEMTEST=y
  25 CONFIG_CMD_CLK=y
  26 # CONFIG_CMD_FLASH is not set
  27 CONFIG_CMD_FPGA_LOADBP=y
  28 CONFIG_CMD_FPGA_LOADP=y
  29 CONFIG_CMD_I2C=y
  30 CONFIG_CMD_MMC=y
  31 CONFIG_CMD_TFTPPUT=y
  32 CONFIG_CMD_TIME=y
  33 CONFIG_MP=y
  34 CONFIG_CMD_TIMER=y
  35 CONFIG_CMD_EXT4_WRITE=y
  36 CONFIG_SPL_OF_CONTROL=y
  37 CONFIG_OF_EMBED=y
  38 CONFIG_ENV_IS_IN_FAT=y
  39 CONFIG_NET_RANDOM_ETHADDR=y
  40 CONFIG_SPL_DM=y
  41 CONFIG_SPL_DM_SEQ_ALIAS=y
  42 CONFIG_CLK_ZYNQMP=y
  43 CONFIG_FPGA_XILINX=y
  44 CONFIG_FPGA_ZYNQMPPL=y
  45 CONFIG_DM_GPIO=y
  46 CONFIG_DM_I2C=y
  47 CONFIG_SYS_I2C_CADENCE=y
  48 CONFIG_MISC=y
  49 CONFIG_DM_MMC=y
  50 CONFIG_MMC_SDHCI=y
  51 CONFIG_MMC_SDHCI_ZYNQ=y
  52 CONFIG_PHY_MARVELL=y
  53 CONFIG_PHY_NATSEMI=y
  54 CONFIG_PHY_REALTEK=y
  55 CONFIG_PHY_TI=y
  56 CONFIG_PHY_VITESSE=y
  57 CONFIG_PHY_FIXED=y
  58 CONFIG_DM_ETH=y
  59 CONFIG_PHY_GIGE=y
  60 CONFIG_ZYNQ_GEM=y
  61 CONFIG_DEBUG_UART_ZYNQ=y
  62 CONFIG_DEBUG_UART_ANNOUNCE=y
  63 CONFIG_ZYNQ_SERIAL=y
  64 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y