git.sur5r.net Git - u-boot/blob - configs/zynq_minized_defconfig

   1 CONFIG_ARM=y
   2 CONFIG_ARCH_ZYNQ=y
   3 CONFIG_SYS_TEXT_BASE=0x4000000
   4 CONFIG_SPL=y
   5 CONFIG_DEBUG_UART_BASE=0xe0001000
   6 CONFIG_DEBUG_UART_CLOCK=50000000
   7 CONFIG_SPL_STACK_R_ADDR=0x200000
   8 CONFIG_DEFAULT_DEVICE_TREE="zynq-minized"
   9 CONFIG_DEBUG_UART=y
  10 CONFIG_DISTRO_DEFAULTS=y
  11 CONFIG_FIT=y
  12 CONFIG_FIT_SIGNATURE=y
  13 CONFIG_FIT_VERBOSE=y
  14 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
  15 CONFIG_SPL_STACK_R=y
  16 CONFIG_SPL_OS_BOOT=y
  17 CONFIG_SYS_PROMPT="Zynq> "
  18 CONFIG_CMD_THOR_DOWNLOAD=y
  19 CONFIG_CMD_DFU=y
  20 # CONFIG_CMD_FLASH is not set
  21 CONFIG_CMD_FPGA_LOADBP=y
  22 CONFIG_CMD_FPGA_LOADFS=y
  23 CONFIG_CMD_FPGA_LOADMK=y
  24 CONFIG_CMD_FPGA_LOADP=y
  25 CONFIG_CMD_GPIO=y
  26 CONFIG_CMD_MMC=y
  27 CONFIG_CMD_SF=y
  28 CONFIG_CMD_USB=y
  29 # CONFIG_CMD_SETEXPR is not set
  30 CONFIG_CMD_TFTPPUT=y
  31 CONFIG_CMD_CACHE=y
  32 CONFIG_CMD_EXT4_WRITE=y
  33 CONFIG_ENV_IS_IN_SPI_FLASH=y
  34 CONFIG_NET_RANDOM_ETHADDR=y
  35 CONFIG_SPL_DM_SEQ_ALIAS=y
  36 CONFIG_DFU_MMC=y
  37 CONFIG_DFU_RAM=y
  38 CONFIG_FPGA_XILINX=y
  39 CONFIG_FPGA_ZYNQPL=y
  40 CONFIG_DM_GPIO=y
  41 CONFIG_MMC_SDHCI=y
  42 CONFIG_MMC_SDHCI_ZYNQ=y
  43 CONFIG_SPI_FLASH=y
  44 CONFIG_SPI_FLASH_BAR=y
  45 CONFIG_SPI_FLASH_SPANSION=y
  46 CONFIG_SPI_FLASH_STMICRO=y
  47 CONFIG_SPI_FLASH_WINBOND=y
  48 CONFIG_PHY_MARVELL=y
  49 CONFIG_PHY_REALTEK=y
  50 CONFIG_PHY_XILINX=y
  51 CONFIG_ZYNQ_GEM=y
  52 CONFIG_DEBUG_UART_ZYNQ=y
  53 CONFIG_ZYNQ_SERIAL=y
  54 CONFIG_ZYNQ_QSPI=y
  55 CONFIG_USB=y
  56 CONFIG_USB_EHCI_HCD=y
  57 CONFIG_USB_ULPI_VIEWPORT=y
  58 CONFIG_USB_ULPI=y
  59 CONFIG_USB_STORAGE=y
  60 CONFIG_USB_GADGET=y
  61 CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
  62 CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
  63 CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
  64 CONFIG_CI_UDC=y
  65 CONFIG_USB_GADGET_DOWNLOAD=y
  66 CONFIG_USB_FUNCTION_THOR=y