git.sur5r.net Git - u-boot/blob - cpu/mpc83xx/cpu_init.c

   1 /*
   2  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <mpc83xx.h>
  25 #include <ioports.h>
  26 #include <asm/io.h>
  27 #ifdef CONFIG_USB_EHCI_FSL
  28 #include <usb/ehci-fsl.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #ifdef CONFIG_QE
  34 extern qe_iop_conf_t qe_iop_conf_tab[];
  35 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  36                          int open_drain, int assign);
  37 extern void qe_init(uint qe_base);
  38 extern void qe_reset(void);
  39
  40 static void config_qe_ioports(void)
  41 {
  42         u8      port, pin;
  43         int     dir, open_drain, assign;
  44         int     i;
  45
  46         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  47                 port            = qe_iop_conf_tab[i].port;
  48                 pin             = qe_iop_conf_tab[i].pin;
  49                 dir             = qe_iop_conf_tab[i].dir;
  50                 open_drain      = qe_iop_conf_tab[i].open_drain;
  51                 assign          = qe_iop_conf_tab[i].assign;
  52                 qe_config_iopin(port, pin, dir, open_drain, assign);
  53         }
  54 }
  55 #endif
  56
  57 /*
  58  * Breathe some life into the CPU...
  59  *
  60  * Set up the memory map,
  61  * initialize a bunch of registers,
  62  * initialize the UPM's
  63  */
  64 void cpu_init_f (volatile immap_t * im)
  65 {
  66         __be32 acr_mask =
  67 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  68                 (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  69 #endif
  70 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  71                 (ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  72 #endif
  73                 0;
  74         __be32 acr_val =
  75 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  76                 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  77 #endif
  78 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  79                 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  80 #endif
  81                 0;
  82         __be32 spcr_mask =
  83 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
  84                 (SPCR_OPT << SPCR_OPT_SHIFT) |
  85 #endif
  86 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  87                 (SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
  88 #endif
  89 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
  90                 (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
  91 #endif
  92 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
  93                 (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
  94 #endif
  95                 0;
  96         __be32 spcr_val =
  97 #ifdef CONFIG_SYS_SPCR_OPT
  98                 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
  99 #endif
 100 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
 101                 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
 102 #endif
 103 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
 104                 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
 105 #endif
 106 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
 107                 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
 108 #endif
 109                 0;
 110         __be32 sccr_mask =
 111 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 112                 (SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 113 #endif
 114 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 115                 (SCCR_PCICM << SCCR_PCICM_SHIFT) |
 116 #endif
 117 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 118                 (SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 119 #endif
 120 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 121                 (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 122 #endif
 123 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 124                 (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 125 #endif
 126 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 127                 (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 128 #endif
 129 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 130                 (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 131 #endif
 132 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 133                 (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 134 #endif
 135 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 136                 (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 137 #endif
 138 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 139                 (SCCR_SATACM << SCCR_SATACM_SHIFT) |
 140 #endif
 141                 0;
 142         __be32 sccr_val =
 143 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 144                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 145 #endif
 146 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 147                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 148 #endif
 149 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 150                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 151 #endif
 152 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 153                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 154 #endif
 155 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 156                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 157 #endif
 158 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 159                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 160 #endif
 161 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 162                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 163 #endif
 164 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 165                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 166 #endif
 167 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 168                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 169 #endif
 170 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 171                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 172 #endif
 173                 0;
 174
 175         /* Pointer is writable since we allocated a register for it */
 176         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 177
 178         /* Clear initial global data */
 179         memset ((void *) gd, 0, sizeof (gd_t));
 180
 181         /* system performance tweaking */
 182         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 183
 184         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 185
 186         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 187
 188         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 189         gd->reset_status = __raw_readl(&im->reset.rsr);
 190         __raw_writel(~(RSR_RES), &im->reset.rsr);
 191
 192         /* AER - Arbiter Event Register - store status */
 193         gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 194         gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 195
 196         /*
 197          * RMR - Reset Mode Register
 198          * contains checkstop reset enable (4.6.1.4)
 199          */
 200         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 201
 202         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 203         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 204
 205         /* System General Purpose Register */
 206 #ifdef CONFIG_SYS_SICRH
 207 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
 208         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 209         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 210                      &im->sysconf.sicrh);
 211 #else
 212         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 213 #endif
 214 #endif
 215 #ifdef CONFIG_SYS_SICRL
 216         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 217 #endif
 218 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 219         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 220 #endif
 221 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 222         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 223 #endif
 224
 225 #ifdef CONFIG_QE
 226         /* Config QE ioports */
 227         config_qe_ioports();
 228 #endif
 229
 230         /*
 231          * Memory Controller:
 232          */
 233
 234         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 235          * addresses - these have to be modified later when FLASH size
 236          * has been determined
 237          */
 238
 239 #if defined(CONFIG_SYS_BR0_PRELIM)  \
 240         && defined(CONFIG_SYS_OR0_PRELIM) \
 241         && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
 242         && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 243         im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
 244         im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
 245         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 246         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 247 #else
 248 #error  CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 249 #endif
 250
 251 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 252         im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
 253         im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
 254 #endif
 255 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 256         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 257         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 258 #endif
 259 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 260         im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
 261         im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
 262 #endif
 263 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 264         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 265         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 266 #endif
 267 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 268         im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
 269         im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
 270 #endif
 271 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 272         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 273         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 274 #endif
 275 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 276         im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
 277         im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
 278 #endif
 279 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 280         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 281         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 282 #endif
 283 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 284         im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
 285         im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
 286 #endif
 287 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 288         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 289         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 290 #endif
 291 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 292         im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
 293         im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
 294 #endif
 295 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 296         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 297         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 298 #endif
 299 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 300         im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
 301         im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
 302 #endif
 303 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 304         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 305         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 306 #endif
 307 #ifdef CONFIG_SYS_GPIO1_PRELIM
 308         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 309         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 310 #endif
 311 #ifdef CONFIG_SYS_GPIO2_PRELIM
 312         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 313         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 314 #endif
 315 #ifdef CONFIG_USB_EHCI_FSL
 316 #ifndef CONFIG_MPC834x
 317         uint32_t temp;
 318         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
 319
 320         /* Configure interface. */
 321         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 322
 323         /* Wait for clock to stabilize */
 324         do {
 325                 temp = __raw_readl(&ehci->control);
 326                 udelay(1000);
 327         } while (!(temp & PHY_CLK_VALID));
 328 #endif
 329 #endif
 330 }
 331
 332 int cpu_init_r (void)
 333 {
 334         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 335 #ifdef CONFIG_QE
 336         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 337 #endif
 338         __be32 lcrr_mask =
 339 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 340                 LCRR_DBYP |
 341 #endif
 342 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
 343                 LCRR_EADC |
 344 #endif
 345 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 346                 LCRR_CLKDIV |
 347 #endif
 348                 0;
 349         __be32 lcrr_val =
 350 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 351                 CONFIG_SYS_LCRR_DBYP |
 352 #endif
 353 #ifdef CONFIG_SYS_LCRR_EADC
 354                 CONFIG_SYS_LCRR_EADC |
 355 #endif
 356 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 357                 CONFIG_SYS_LCRR_CLKDIV |
 358 #endif
 359                 0;
 360
 361         /* LCRR - Clock Ratio Register (10.3.1.16)
 362          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 363          */
 364         clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
 365         __raw_readl(&im->lbus.lcrr);
 366         isync();
 367
 368 #ifdef CONFIG_QE
 369         qe_init(qe_base);
 370         qe_reset();
 371 #endif
 372         return 0;
 373 }
 374
 375 /*
 376  * Print out the bus arbiter event
 377  */
 378 #if defined(CONFIG_DISPLAY_AER_FULL)
 379 static int print_83xx_arb_event(int force)
 380 {
 381         static char* event[] = {
 382                 "Address Time Out",
 383                 "Data Time Out",
 384                 "Address Only Transfer Type",
 385                 "External Control Word Transfer Type",
 386                 "Reserved Transfer Type",
 387                 "Transfer Error",
 388                 "reserved",
 389                 "reserved"
 390         };
 391         static char* master[] = {
 392                 "e300 Core Data Transaction",
 393                 "reserved",
 394                 "e300 Core Instruction Fetch",
 395                 "reserved",
 396                 "TSEC1",
 397                 "TSEC2",
 398                 "USB MPH",
 399                 "USB DR",
 400                 "Encryption Core",
 401                 "I2C Boot Sequencer",
 402                 "JTAG",
 403                 "reserved",
 404                 "eSDHC",
 405                 "PCI1",
 406                 "PCI2",
 407                 "DMA",
 408                 "QUICC Engine 00",
 409                 "QUICC Engine 01",
 410                 "QUICC Engine 10",
 411                 "QUICC Engine 11",
 412                 "reserved",
 413                 "reserved",
 414                 "reserved",
 415                 "reserved",
 416                 "SATA1",
 417                 "SATA2",
 418                 "SATA3",
 419                 "SATA4",
 420                 "reserved",
 421                 "PCI Express 1",
 422                 "PCI Express 2",
 423                 "TDM-DMAC"
 424         };
 425         static char *transfer[] = {
 426                 "Address-only, Clean Block",
 427                 "Address-only, lwarx reservation set",
 428                 "Single-beat or Burst write",
 429                 "reserved",
 430                 "Address-only, Flush Block",
 431                 "reserved",
 432                 "Burst write",
 433                 "reserved",
 434                 "Address-only, sync",
 435                 "Address-only, tlbsync",
 436                 "Single-beat or Burst read",
 437                 "Single-beat or Burst read",
 438                 "Address-only, Kill Block",
 439                 "Address-only, icbi",
 440                 "Burst read",
 441                 "reserved",
 442                 "Address-only, eieio",
 443                 "reserved",
 444                 "Single-beat write",
 445                 "reserved",
 446                 "ecowx - Illegal single-beat write",
 447                 "reserved",
 448                 "reserved",
 449                 "reserved",
 450                 "Address-only, TLB Invalidate",
 451                 "reserved",
 452                 "Single-beat or Burst read",
 453                 "reserved",
 454                 "eciwx - Illegal single-beat read",
 455                 "reserved",
 456                 "Burst read",
 457                 "reserved"
 458         };
 459
 460         int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
 461                     >> AEATR_EVENT_SHIFT;
 462         int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
 463                       >> AEATR_MSTR_ID_SHIFT;
 464         int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
 465                    >> AEATR_TBST_SHIFT;
 466         int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
 467                     >> AEATR_TSIZE_SHIFT;
 468         int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
 469                     >> AEATR_TTYPE_SHIFT;
 470
 471         if (!force && !gd->arbiter_event_address)
 472                 return 0;
 473
 474         puts("Arbiter Event Status:\n");
 475         printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
 476         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 477         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 478         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 479                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 480         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 481
 482         return gd->arbiter_event_address;
 483 }
 484
 485 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 486
 487 static int print_83xx_arb_event(int force)
 488 {
 489         if (!force && !gd->arbiter_event_address)
 490                 return 0;
 491
 492         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 493                 gd->arbiter_event_attributes, gd->arbiter_event_address);
 494
 495         return gd->arbiter_event_address;
 496 }
 497 #endif /* CONFIG_DISPLAY_AER_xxxx */
 498
 499 /*
 500  * Figure out the cause of the reset
 501  */
 502 int prt_83xx_rsr(void)
 503 {
 504         static struct {
 505                 ulong mask;
 506                 char *desc;
 507         } bits[] = {
 508                 {
 509                 RSR_SWSR, "Software Soft"}, {
 510                 RSR_SWHR, "Software Hard"}, {
 511                 RSR_JSRS, "JTAG Soft"}, {
 512                 RSR_CSHR, "Check Stop"}, {
 513                 RSR_SWRS, "Software Watchdog"}, {
 514                 RSR_BMRS, "Bus Monitor"}, {
 515                 RSR_SRS,  "External/Internal Soft"}, {
 516                 RSR_HRS,  "External/Internal Hard"}
 517         };
 518         static int n = sizeof bits / sizeof bits[0];
 519         ulong rsr = gd->reset_status;
 520         int i;
 521         char *sep;
 522
 523         puts("Reset Status:");
 524
 525         sep = " ";
 526         for (i = 0; i < n; i++)
 527                 if (rsr & bits[i].mask) {
 528                         printf("%s%s", sep, bits[i].desc);
 529                         sep = ", ";
 530                 }
 531         puts("\n");
 532
 533 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 534         print_83xx_arb_event(rsr & RSR_BMRS);
 535 #endif
 536         puts("\n");
 537
 538         return 0;
 539 }