git.sur5r.net Git - u-boot/blob - cpu/ppc4xx/spd_sdram.c

   1 /*
   2  * (C) Copyright 2001
   3  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   4  *
   5  * Based on code by:
   6  *
   7  * Kenneth Johansson ,Ericsson AB.
   8  * kenneth.johansson@etx.ericsson.se
   9  *
  10  * hacked up by bill hunter. fixed so we could run before
  11  * serial_init and console_init. previous version avoided this by
  12  * running out of cache memory during serial/console init, then running
  13  * this code later.
  14  *
  15  * (C) Copyright 2002
  16  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  17  * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
  18  *
  19  * See file CREDITS for list of people who contributed to this
  20  * project.
  21  *
  22  * This program is free software; you can redistribute it and/or
  23  * modify it under the terms of the GNU General Public License as
  24  * published by the Free Software Foundation; either version 2 of
  25  * the License, or (at your option) any later version.
  26  *
  27  * This program is distributed in the hope that it will be useful,
  28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30  * GNU General Public License for more details.
  31  *
  32  * You should have received a copy of the GNU General Public License
  33  * along with this program; if not, write to the Free Software
  34  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  35  * MA 02111-1307 USA
  36  */
  37
  38 #include <common.h>
  39 #include <asm/processor.h>
  40 #include <i2c.h>
  41 #include <ppc4xx.h>
  42
  43 #ifdef CONFIG_SPD_EEPROM
  44
  45 /*
  46  * Set default values
  47  */
  48 #ifndef CFG_I2C_SPEED
  49 #define CFG_I2C_SPEED   50000
  50 #endif
  51
  52 #ifndef CFG_I2C_SLAVE
  53 #define CFG_I2C_SLAVE   0xFE
  54 #endif
  55
  56 #ifndef  CONFIG_440              /* for 405 WALNUT board */
  57
  58 #define  SDRAM0_CFG_DCE          0x80000000
  59 #define  SDRAM0_CFG_SRE          0x40000000
  60 #define  SDRAM0_CFG_PME          0x20000000
  61 #define  SDRAM0_CFG_MEMCHK       0x10000000
  62 #define  SDRAM0_CFG_REGEN        0x08000000
  63 #define  SDRAM0_CFG_ECCDD        0x00400000
  64 #define  SDRAM0_CFG_EMDULR       0x00200000
  65 #define  SDRAM0_CFG_DRW_SHIFT    (31-6)
  66 #define  SDRAM0_CFG_BRPF_SHIFT   (31-8)
  67
  68 #define  SDRAM0_TR_CASL_SHIFT    (31-8)
  69 #define  SDRAM0_TR_PTA_SHIFT     (31-13)
  70 #define  SDRAM0_TR_CTP_SHIFT     (31-15)
  71 #define  SDRAM0_TR_LDF_SHIFT     (31-17)
  72 #define  SDRAM0_TR_RFTA_SHIFT    (31-29)
  73 #define  SDRAM0_TR_RCD_SHIFT     (31-31)
  74
  75 #define  SDRAM0_RTR_SHIFT        (31-15)
  76 #define  SDRAM0_ECCCFG_SHIFT     (31-11)
  77
  78 /* SDRAM0_CFG enable macro  */
  79 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
  80
  81 #define SDRAM0_BXCR_SZ_MASK  0x000e0000
  82 #define SDRAM0_BXCR_AM_MASK  0x0000e000
  83
  84 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
  85 #define SDRAM0_BXCR_AM_SHIFT (31-18)
  86
  87 #define SDRAM0_BXCR_SZ(x)  ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
  88 #define SDRAM0_BXCR_AM(x)  ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
  89
  90 #ifdef CONFIG_SPDDRAM_SILENT
  91 # define SPD_ERR(x) do { return 0; } while (0)
  92 #else
  93 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
  94 #endif
  95
  96 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
  97
  98 /* function prototypes */
  99 int spd_read(uint addr);
 100
 101
 102 /*
 103  * This function is reading data from the DIMM module EEPROM over the SPD bus
 104  * and uses that to program the sdram controller.
 105  *
 106  * This works on boards that has the same schematics that the IBM walnut has.
 107  *
 108  * Input: null for default I2C spd functions or a pointer to a custom function
 109  * returning spd_data.
 110  */
 111
 112 long int spd_sdram(int(read_spd)(uint addr))
 113 {
 114         int bus_period,tmp,row,col;
 115         int total_size,bank_size,bank_code;
 116         int ecc_on;
 117         int mode;
 118         int bank_cnt;
 119
 120         int sdram0_pmit=0x07c00000;
 121 #ifndef CONFIG_405EP /* not on PPC405EP */
 122         int sdram0_besr0=-1;
 123         int sdram0_besr1=-1;
 124         int sdram0_eccesr=-1;
 125 #endif
 126         int sdram0_ecccfg;
 127
 128         int sdram0_rtr=0;
 129         int sdram0_tr=0;
 130
 131         int sdram0_b0cr;
 132         int sdram0_b1cr;
 133         int sdram0_b2cr;
 134         int sdram0_b3cr;
 135
 136         int sdram0_cfg=0;
 137
 138         int t_rp;
 139         int t_rcd;
 140         int t_ras;
 141         int t_rc;
 142         int min_cas;
 143
 144         if(read_spd == 0){
 145                 read_spd=spd_read;
 146         /*
 147          * Make sure I2C controller is initialized
 148          * before continuing.
 149          */
 150                 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 151         }
 152
 153
 154         /*
 155          * Calculate the bus period, we do it this
 156          * way to minimize stack utilization.
 157          */
 158 #ifndef CONFIG_405EP
 159         tmp = (mfdcr(pllmd) >> (31-6)) & 0xf;   /* get FBDV bits */
 160         tmp = CONFIG_SYS_CLK_FREQ * tmp;        /* get plb freq */
 161 #else
 162         {
 163                 unsigned long freqCPU;
 164                 unsigned long pllmr0;
 165                 unsigned long pllmr1;
 166                 unsigned long pllFbkDiv;
 167                 unsigned long pllPlbDiv;
 168                 unsigned long pllmr0_ccdv;
 169
 170                 /*
 171                  * Read PLL Mode registers
 172                  */
 173                 pllmr0 = mfdcr (cpc0_pllmr0);
 174                 pllmr1 = mfdcr (cpc0_pllmr1);
 175
 176                 pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
 177                 if (pllFbkDiv == 0) {
 178                         pllFbkDiv = 16;
 179                 }
 180                 pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
 181
 182                 /*
 183                  * Determine CPU clock frequency
 184                  */
 185                 pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
 186                 if (pllmr1 & PLLMR1_SSCS_MASK) {
 187                         freqCPU = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / pllmr0_ccdv;
 188                 } else {
 189                         freqCPU = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
 190                 }
 191
 192                 /*
 193                  * Determine PLB clock frequency
 194                  */
 195                 tmp = freqCPU / pllPlbDiv;
 196         }
 197 #endif
 198         bus_period = sdram_HZ_to_ns(tmp);       /* get sdram speed */
 199
 200         /* Make shure we are using SDRAM */
 201         if (read_spd(2) != 0x04){
 202           SPD_ERR("SDRAM - non SDRAM memory module found\n");
 203           }
 204
 205 /*------------------------------------------------------------------
 206   configure memory timing register
 207
 208   data from DIMM:
 209   27    IN Row Precharge Time ( t RP)
 210   29    MIN RAS to CAS Delay ( t RCD)
 211   127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
 212   -------------------------------------------------------------------*/
 213
 214      /*
 215       * first figure out which cas latency mode to use
 216       * use the min supported mode
 217       */
 218
 219         tmp = read_spd(127) & 0x6;
 220      if(tmp == 0x02){              /* only cas = 2 supported */
 221           min_cas = 2;
 222 /*        t_ck = read_spd(9); */
 223 /*        t_ac = read_spd(10); */
 224           }
 225      else if (tmp == 0x04){         /* only cas = 3 supported */
 226           min_cas = 3;
 227 /*        t_ck = read_spd(9); */
 228 /*        t_ac = read_spd(10); */
 229           }
 230      else if (tmp == 0x06){         /* 2,3 supported, so use 2 */
 231           min_cas = 2;
 232 /*        t_ck = read_spd(23); */
 233 /*        t_ac = read_spd(24); */
 234           }
 235      else {
 236              SPD_ERR("SDRAM - unsupported CAS latency \n");
 237         }
 238
 239      /* get some timing values, t_rp,t_rcd,t_ras,t_rc
 240      */
 241      t_rp = read_spd(27);
 242      t_rcd = read_spd(29);
 243      t_ras = read_spd(30);
 244      t_rc = t_ras + t_rp;
 245
 246      /* The following timing calcs subtract 1 before deviding.
 247       * this has effect of using ceiling instead of floor rounding,
 248       * and also subtracting 1 to convert number to reg value
 249       */
 250      /* set up CASL */
 251      sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
 252      /* set up PTA */
 253      sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
 254      /* set up CTP */
 255      tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
 256      if(tmp<1) tmp=1;
 257      sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
 258      /* set LDF = 2 cycles, reg value = 1 */
 259      sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
 260      /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
 261         tmp = ( (t_rc - 1) / bus_period)-3;
 262         if(tmp<0)tmp=0;
 263         if(tmp>6)tmp=6;
 264         sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
 265      /* set RCD = t_rcd/bus_period*/
 266      sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;
 267
 268
 269 /*------------------------------------------------------------------
 270   configure RTR register
 271   -------------------------------------------------------------------*/
 272      row = read_spd(3);
 273      col = read_spd(4);
 274      tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
 275      switch(tmp){
 276         case 0x00:
 277           tmp=15625;
 278           break;
 279         case 0x01:
 280           tmp=15625/4;
 281           break;
 282         case 0x02:
 283           tmp=15625/2;
 284           break;
 285         case 0x03:
 286           tmp=15625*2;
 287           break;
 288         case 0x04:
 289           tmp=15625*4;
 290           break;
 291         case 0x05:
 292           tmp=15625*8;
 293           break;
 294         default:
 295           SPD_ERR("SDRAM - Bad refresh period \n");
 296         }
 297         /* convert from nsec to bus cycles */
 298         tmp = tmp/bus_period;
 299         sdram0_rtr = (tmp & 0x3ff8)<<  SDRAM0_RTR_SHIFT;
 300
 301 /*------------------------------------------------------------------
 302   determine the number of banks used
 303   -------------------------------------------------------------------*/
 304         /* byte 7:6 is module data width */
 305         if(read_spd(7) != 0)
 306             SPD_ERR("SDRAM - unsupported module width\n");
 307         tmp = read_spd(6);
 308         if (tmp < 32)
 309             SPD_ERR("SDRAM - unsupported module width\n");
 310         else if (tmp < 64)
 311             bank_cnt=1;         /* one bank per sdram side */
 312         else if (tmp < 73)
 313             bank_cnt=2; /* need two banks per side */
 314         else if (tmp < 161)
 315             bank_cnt=4; /* need four banks per side */
 316         else
 317             SPD_ERR("SDRAM - unsupported module width\n");
 318
 319         /* byte 5 is the module row count (refered to as dimm "sides") */
 320         tmp = read_spd(5);
 321         if(tmp==1);
 322         else if(tmp==2) bank_cnt *=2;
 323         else if(tmp==4) bank_cnt *=4;
 324         else bank_cnt = 8;              /* 8 is an error code */
 325
 326         if(bank_cnt > 4)        /* we only have 4 banks to work with */
 327             SPD_ERR("SDRAM - unsupported module rows for this width\n");
 328
 329         /* now check for ECC ability of module. We only support ECC
 330          *   on 32 bit wide devices with 8 bit ECC.
 331          */
 332         if ( (read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) ){
 333            sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
 334            ecc_on = 1;
 335         }
 336         else{
 337            sdram0_ecccfg=0;
 338            ecc_on = 0;
 339         }
 340
 341 /*------------------------------------------------------------------
 342         calculate total size
 343   -------------------------------------------------------------------*/
 344         /* calculate total size and do sanity check */
 345         tmp = read_spd(31);
 346         total_size=1<<22;       /* total_size = 4MB */
 347         /* now multiply 4M by the smallest device row density */
 348         /* note that we don't support asymetric rows */
 349         while (((tmp & 0x0001) == 0) && (tmp != 0)){
 350             total_size= total_size<<1;
 351             tmp = tmp>>1;
 352             }
 353         total_size *= read_spd(5);      /* mult by module rows (dimm sides) */
 354
 355 /*------------------------------------------------------------------
 356         map  rows * cols * banks to a mode
 357  -------------------------------------------------------------------*/
 358
 359         switch( row )
 360         {
 361         case 11:
 362                 switch ( col )
 363                 {
 364                 case 8:
 365                         mode=4; /* mode 5 */
 366                         break;
 367                 case 9:
 368                 case 10:
 369                         mode=0; /* mode 1 */
 370                         break;
 371                 default:
 372                 SPD_ERR("SDRAM - unsupported mode\n");
 373                 }
 374                 break;
 375         case 12:
 376                 switch ( col )
 377                 {
 378                 case 8:
 379                         mode=3; /* mode 4 */
 380                         break;
 381                 case 9:
 382                 case 10:
 383                         mode=1; /* mode 2 */
 384                         break;
 385                 default:
 386                 SPD_ERR("SDRAM - unsupported mode\n");
 387                 }
 388                 break;
 389         case 13:
 390                 switch ( col )
 391                 {
 392                 case 8:
 393                         mode=5; /* mode 6 */
 394                         break;
 395                 case 9:
 396                 case 10:
 397                         if (read_spd(17) ==2 )
 398                                 mode=6; /* mode 7 */
 399                         else
 400                                 mode=2; /* mode 3 */
 401                         break;
 402                 case 11:
 403                         mode=2; /* mode 3 */
 404                         break;
 405                 default:
 406                 SPD_ERR("SDRAM - unsupported mode\n");
 407                 }
 408                 break;
 409         default:
 410              SPD_ERR("SDRAM - unsupported mode\n");
 411         }
 412
 413 /*------------------------------------------------------------------
 414         using the calculated values, compute the bank
 415         config register values.
 416  -------------------------------------------------------------------*/
 417         sdram0_b1cr = 0;
 418         sdram0_b2cr = 0;
 419         sdram0_b3cr = 0;
 420
 421         /* compute the size of each bank */
 422         bank_size = total_size / bank_cnt;
 423         /* convert bank size to bank size code for ppc4xx
 424                 by takeing log2(bank_size) - 22 */
 425         tmp=bank_size;          /* start with tmp = bank_size */
 426         bank_code=0;                    /* and bank_code = 0 */
 427         while (tmp>1){          /* this takes log2 of tmp */
 428                 bank_code++;            /* and stores result in bank_code */
 429                 tmp=tmp>>1;
 430                 }                               /* bank_code is now log2(bank_size) */
 431         bank_code-=22;                          /* subtract 22 to get the code */
 432
 433         tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
 434         sdram0_b0cr = (bank_size) * 0 | tmp;
 435         if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
 436         if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
 437         if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
 438
 439
 440         /*
 441          *   enable sdram controller DCE=1
 442          *  enable burst read prefetch to 32 bytes BRPF=2
 443          *  leave other functions off
 444          */
 445
 446 /*------------------------------------------------------------------
 447         now that we've done our calculations, we are ready to
 448         program all the registers.
 449  -------------------------------------------------------------------*/
 450
 451
 452 #define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
 453         /* disable memcontroller so updates work */
 454         sdram0_cfg = 0;
 455         mtsdram0( mem_mcopt1, sdram0_cfg );
 456
 457 #ifndef CONFIG_405EP /* not on PPC405EP */
 458         mtsdram0( mem_besra , sdram0_besr0 );
 459         mtsdram0( mem_besrb , sdram0_besr1 );
 460         mtsdram0( mem_ecccf , sdram0_ecccfg );
 461         mtsdram0( mem_eccerr, sdram0_eccesr );
 462 #endif
 463         mtsdram0( mem_rtr   , sdram0_rtr );
 464         mtsdram0( mem_pmit  , sdram0_pmit );
 465         mtsdram0( mem_mb0cf , sdram0_b0cr );
 466         mtsdram0( mem_mb1cf , sdram0_b1cr );
 467         mtsdram0( mem_mb2cf , sdram0_b2cr );
 468         mtsdram0( mem_mb3cf , sdram0_b3cr );
 469         mtsdram0( mem_sdtr1 , sdram0_tr );
 470
 471         /* SDRAM have a power on delay,  500 micro should do */
 472         udelay(500);
 473         sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 474         if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
 475         mtsdram0( mem_mcopt1, sdram0_cfg );
 476
 477
 478         /* kernel 2.4.2 from mvista has a bug with memory over 128MB */
 479 #ifdef MVISTA_MEM_BUG
 480         if (total_size > 128*1024*1024 )
 481                 total_size=128*1024*1024;
 482 #endif
 483         return (total_size);
 484 }
 485
 486 int spd_read(uint addr)
 487 {
 488         char data[2];
 489
 490         if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 491                 return (int)data[0];
 492         else
 493                 return 0;
 494 }
 495
 496 #else                             /* CONFIG_440 */
 497
 498 /*-----------------------------------------------------------------------------
 499 |  Memory Controller Options 0
 500 +-----------------------------------------------------------------------------*/
 501 #define SDRAM_CFG0_DCEN           0x80000000  /* SDRAM Controller Enable      */
 502 #define SDRAM_CFG0_MCHK_MASK      0x30000000  /* Memory data errchecking mask */
 503 #define SDRAM_CFG0_MCHK_NON       0x00000000  /* No ECC generation            */
 504 #define SDRAM_CFG0_MCHK_GEN       0x20000000  /* ECC generation               */
 505 #define SDRAM_CFG0_MCHK_CHK       0x30000000  /* ECC generation and checking  */
 506 #define SDRAM_CFG0_RDEN           0x08000000  /* Registered DIMM enable       */
 507 #define SDRAM_CFG0_PMUD           0x04000000  /* Page management unit         */
 508 #define SDRAM_CFG0_DMWD_MASK      0x02000000  /* DRAM width mask              */
 509 #define SDRAM_CFG0_DMWD_32        0x00000000  /* 32 bits                      */
 510 #define SDRAM_CFG0_DMWD_64        0x02000000  /* 64 bits                      */
 511 #define SDRAM_CFG0_UIOS_MASK      0x00C00000  /* Unused IO State              */
 512 #define SDRAM_CFG0_PDP            0x00200000  /* Page deallocation policy     */
 513
 514 /*-----------------------------------------------------------------------------
 515 |  Memory Controller Options 1
 516 +-----------------------------------------------------------------------------*/
 517 #define SDRAM_CFG1_SRE            0x80000000  /* Self-Refresh Entry           */
 518 #define SDRAM_CFG1_PMEN           0x40000000  /* Power Management Enable      */
 519
 520 /*-----------------------------------------------------------------------------+
 521 |  SDRAM DEVPOT Options
 522 +-----------------------------------------------------------------------------*/
 523 #define SDRAM_DEVOPT_DLL          0x80000000
 524 #define SDRAM_DEVOPT_DS           0x40000000
 525
 526 /*-----------------------------------------------------------------------------+
 527 |  SDRAM MCSTS Options
 528 +-----------------------------------------------------------------------------*/
 529 #define SDRAM_MCSTS_MRSC          0x80000000
 530 #define SDRAM_MCSTS_SRMS          0x40000000
 531 #define SDRAM_MCSTS_CIS           0x20000000
 532
 533 /*-----------------------------------------------------------------------------
 534 |  SDRAM Refresh Timer Register
 535 +-----------------------------------------------------------------------------*/
 536 #define SDRAM_RTR_RINT_MASK       0xFFFF0000
 537 #define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
 538 #define sdram_HZ_to_ns(hertz)     (1000000000/(hertz))
 539
 540 /*-----------------------------------------------------------------------------+
 541 |  SDRAM UABus Base Address Reg
 542 +-----------------------------------------------------------------------------*/
 543 #define SDRAM_UABBA_UBBA_MASK     0x0000000F
 544
 545 /*-----------------------------------------------------------------------------+
 546 |  Memory Bank 0-7 configuration
 547 +-----------------------------------------------------------------------------*/
 548 #define SDRAM_BXCR_SDBA_MASK      0xff800000      /* Base address             */
 549 #define SDRAM_BXCR_SDSZ_MASK      0x000e0000      /* Size                     */
 550 #define SDRAM_BXCR_SDSZ_8         0x00020000      /*   8M                     */
 551 #define SDRAM_BXCR_SDSZ_16        0x00040000      /*  16M                     */
 552 #define SDRAM_BXCR_SDSZ_32        0x00060000      /*  32M                     */
 553 #define SDRAM_BXCR_SDSZ_64        0x00080000      /*  64M                     */
 554 #define SDRAM_BXCR_SDSZ_128       0x000a0000      /* 128M                     */
 555 #define SDRAM_BXCR_SDSZ_256       0x000c0000      /* 256M                     */
 556 #define SDRAM_BXCR_SDSZ_512       0x000e0000      /* 512M                     */
 557 #define SDRAM_BXCR_SDAM_MASK      0x0000e000      /* Addressing mode          */
 558 #define SDRAM_BXCR_SDAM_1         0x00000000      /*   Mode 1                 */
 559 #define SDRAM_BXCR_SDAM_2         0x00002000      /*   Mode 2                 */
 560 #define SDRAM_BXCR_SDAM_3         0x00004000      /*   Mode 3                 */
 561 #define SDRAM_BXCR_SDAM_4         0x00006000      /*   Mode 4                 */
 562 #define SDRAM_BXCR_SDBE           0x00000001      /* Memory Bank Enable       */
 563
 564 /*-----------------------------------------------------------------------------+
 565 |  SDRAM TR0 Options
 566 +-----------------------------------------------------------------------------*/
 567 #define SDRAM_TR0_SDWR_MASK       0x80000000
 568 #define   SDRAM_TR0_SDWR_2_CLK    0x00000000
 569 #define   SDRAM_TR0_SDWR_3_CLK    0x80000000
 570 #define SDRAM_TR0_SDWD_MASK       0x40000000
 571 #define   SDRAM_TR0_SDWD_0_CLK    0x00000000
 572 #define   SDRAM_TR0_SDWD_1_CLK    0x40000000
 573 #define SDRAM_TR0_SDCL_MASK       0x01800000
 574 #define   SDRAM_TR0_SDCL_2_0_CLK  0x00800000
 575 #define   SDRAM_TR0_SDCL_2_5_CLK  0x01000000
 576 #define   SDRAM_TR0_SDCL_3_0_CLK  0x01800000
 577 #define SDRAM_TR0_SDPA_MASK       0x000C0000
 578 #define   SDRAM_TR0_SDPA_2_CLK    0x00040000
 579 #define   SDRAM_TR0_SDPA_3_CLK    0x00080000
 580 #define   SDRAM_TR0_SDPA_4_CLK    0x000C0000
 581 #define SDRAM_TR0_SDCP_MASK       0x00030000
 582 #define   SDRAM_TR0_SDCP_2_CLK    0x00000000
 583 #define   SDRAM_TR0_SDCP_3_CLK    0x00010000
 584 #define   SDRAM_TR0_SDCP_4_CLK    0x00020000
 585 #define   SDRAM_TR0_SDCP_5_CLK    0x00030000
 586 #define SDRAM_TR0_SDLD_MASK       0x0000C000
 587 #define   SDRAM_TR0_SDLD_1_CLK    0x00000000
 588 #define   SDRAM_TR0_SDLD_2_CLK    0x00004000
 589 #define SDRAM_TR0_SDRA_MASK       0x0000001C
 590 #define   SDRAM_TR0_SDRA_6_CLK    0x00000000
 591 #define   SDRAM_TR0_SDRA_7_CLK    0x00000004
 592 #define   SDRAM_TR0_SDRA_8_CLK    0x00000008
 593 #define   SDRAM_TR0_SDRA_9_CLK    0x0000000C
 594 #define   SDRAM_TR0_SDRA_10_CLK   0x00000010
 595 #define   SDRAM_TR0_SDRA_11_CLK   0x00000014
 596 #define   SDRAM_TR0_SDRA_12_CLK   0x00000018
 597 #define   SDRAM_TR0_SDRA_13_CLK   0x0000001C
 598 #define SDRAM_TR0_SDRD_MASK       0x00000003
 599 #define   SDRAM_TR0_SDRD_2_CLK    0x00000001
 600 #define   SDRAM_TR0_SDRD_3_CLK    0x00000002
 601 #define   SDRAM_TR0_SDRD_4_CLK    0x00000003
 602
 603 /*-----------------------------------------------------------------------------+
 604 |  SDRAM TR1 Options
 605 +-----------------------------------------------------------------------------*/
 606 #define SDRAM_TR1_RDSS_MASK         0xC0000000
 607 #define   SDRAM_TR1_RDSS_TR0        0x00000000
 608 #define   SDRAM_TR1_RDSS_TR1        0x40000000
 609 #define   SDRAM_TR1_RDSS_TR2        0x80000000
 610 #define   SDRAM_TR1_RDSS_TR3        0xC0000000
 611 #define SDRAM_TR1_RDSL_MASK         0x00C00000
 612 #define   SDRAM_TR1_RDSL_STAGE1     0x00000000
 613 #define   SDRAM_TR1_RDSL_STAGE2     0x00400000
 614 #define   SDRAM_TR1_RDSL_STAGE3     0x00800000
 615 #define SDRAM_TR1_RDCD_MASK         0x00000800
 616 #define   SDRAM_TR1_RDCD_RCD_0_0    0x00000000
 617 #define   SDRAM_TR1_RDCD_RCD_1_2    0x00000800
 618 #define SDRAM_TR1_RDCT_MASK         0x000001FF
 619 #define   SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
 620 #define   SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
 621 #define   SDRAM_TR1_RDCT_MIN        0x00000000
 622 #define   SDRAM_TR1_RDCT_MAX        0x000001FF
 623
 624 /*-----------------------------------------------------------------------------+
 625 |  SDRAM WDDCTR Options
 626 +-----------------------------------------------------------------------------*/
 627 #define SDRAM_WDDCTR_WRCP_MASK       0xC0000000
 628 #define   SDRAM_WDDCTR_WRCP_0DEG     0x00000000
 629 #define   SDRAM_WDDCTR_WRCP_90DEG    0x40000000
 630 #define   SDRAM_WDDCTR_WRCP_180DEG   0x80000000
 631 #define SDRAM_WDDCTR_DCD_MASK        0x000001FF
 632
 633 /*-----------------------------------------------------------------------------+
 634 |  SDRAM CLKTR Options
 635 +-----------------------------------------------------------------------------*/
 636 #define SDRAM_CLKTR_CLKP_MASK       0xC0000000
 637 #define   SDRAM_CLKTR_CLKP_0DEG     0x00000000
 638 #define   SDRAM_CLKTR_CLKP_90DEG    0x40000000
 639 #define   SDRAM_CLKTR_CLKP_180DEG   0x80000000
 640 #define SDRAM_CLKTR_DCDT_MASK       0x000001FF
 641
 642 /*-----------------------------------------------------------------------------+
 643 |  SDRAM DLYCAL Options
 644 +-----------------------------------------------------------------------------*/
 645 #define SDRAM_DLYCAL_DLCV_MASK      0x000003FC
 646 #define   SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 647 #define   SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 648
 649 /*-----------------------------------------------------------------------------+
 650 |  General Definition
 651 +-----------------------------------------------------------------------------*/
 652 #define DEFAULT_SPD_ADDR1   0x53
 653 #define DEFAULT_SPD_ADDR2   0x52
 654 #define ONE_BILLION         1000000000
 655 #define MAXBANKS            4               /* at most 4 dimm banks */
 656 #define MAX_SPD_BYTES       256
 657 #define NUMHALFCYCLES       4
 658 #define NUMMEMTESTS         8
 659 #define NUMMEMWORDS         8
 660 #define MAXBXCR             4
 661 #define TRUE                1
 662 #define FALSE               0
 663
 664 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 665     {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 666      0xFFFFFFFF, 0xFFFFFFFF},
 667     {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 668      0x00000000, 0x00000000},
 669     {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 670      0x55555555, 0x55555555},
 671     {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 672      0xAAAAAAAA, 0xAAAAAAAA},
 673     {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 674      0x5A5A5A5A, 0x5A5A5A5A},
 675     {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 676      0xA5A5A5A5, 0xA5A5A5A5},
 677     {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 678      0x55AA55AA, 0x55AA55AA},
 679     {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 680      0xAA55AA55, 0xAA55AA55}
 681 };
 682
 683
 684 unsigned char spd_read(uchar chip, uint addr);
 685
 686 void get_spd_info(unsigned long* dimm_populated,
 687                   unsigned char* iic0_dimm_addr,
 688                   unsigned long  num_dimm_banks);
 689
 690 void check_mem_type
 691                  (unsigned long* dimm_populated,
 692                   unsigned char* iic0_dimm_addr,
 693                   unsigned long  num_dimm_banks);
 694
 695 void check_volt_type
 696                  (unsigned long* dimm_populated,
 697                   unsigned char* iic0_dimm_addr,
 698                   unsigned long  num_dimm_banks);
 699
 700 void program_cfg0(unsigned long* dimm_populated,
 701                   unsigned char* iic0_dimm_addr,
 702                   unsigned long  num_dimm_banks);
 703
 704 void program_cfg1(unsigned long* dimm_populated,
 705                   unsigned char* iic0_dimm_addr,
 706                   unsigned long  num_dimm_banks);
 707
 708 void program_rtr (unsigned long* dimm_populated,
 709                   unsigned char* iic0_dimm_addr,
 710                   unsigned long  num_dimm_banks);
 711
 712 void program_tr0 (unsigned long* dimm_populated,
 713                   unsigned char* iic0_dimm_addr,
 714                   unsigned long  num_dimm_banks);
 715
 716 void program_tr1 (void);
 717
 718 void program_ecc (unsigned long  num_bytes);
 719
 720 unsigned
 721 long  program_bxcr(unsigned long* dimm_populated,
 722                    unsigned char* iic0_dimm_addr,
 723                    unsigned long  num_dimm_banks);
 724
 725 /*
 726  * This function is reading data from the DIMM module EEPROM over the SPD bus
 727  * and uses that to program the sdram controller.
 728  *
 729  * This works on boards that has the same schematics that the IBM walnut has.
 730  *
 731  * BUG: Don't handle ECC memory
 732  * BUG: A few values in the TR register is currently hardcoded
 733  */
 734
 735 long int spd_sdram(void) {
 736     unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 737     unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 738     unsigned long total_size;
 739     unsigned long cfg0;
 740     unsigned long mcsts;
 741     unsigned long num_dimm_banks;               /* on board dimm banks */
 742
 743     num_dimm_banks = sizeof(iic0_dimm_addr);
 744
 745         /*
 746          * Make sure I2C controller is initialized
 747          * before continuing.
 748          */
 749         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 750
 751     /*
 752      * Read the SPD information using I2C interface. Check to see if the
 753      * DIMM slots are populated.
 754      */
 755     get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 756
 757     /*
 758      * Check the memory type for the dimms plugged.
 759      */
 760     check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 761
 762     /*
 763      * Check the voltage type for the dimms plugged.
 764      */
 765     check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 766
 767     /*
 768      * program 440GP SDRAM controller options (SDRAM0_CFG0)
 769      */
 770     program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 771
 772     /*
 773      * program 440GP SDRAM controller options (SDRAM0_CFG1)
 774      */
 775     program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 776
 777     /*
 778      * program SDRAM refresh register (SDRAM0_RTR)
 779      */
 780     program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 781
 782     /*
 783      * program SDRAM Timing Register 0 (SDRAM0_TR0)
 784      */
 785     program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 786
 787     /*
 788      * program the BxCR registers to find out total sdram installed
 789      */
 790     total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 791         num_dimm_banks);
 792
 793     /*
 794      * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 795      */
 796     mtsdram(mem_clktr, 0x40000000);
 797
 798     /*
 799      * delay to ensure 200 usec has elapsed
 800      */
 801     udelay(400);
 802
 803     /*
 804      * enable the memory controller
 805      */
 806     mfsdram(mem_cfg0, cfg0);
 807     mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
 808
 809     /*
 810      * wait for SDRAM_CFG0_DC_EN to complete
 811      */
 812     while(1) {
 813         mfsdram(mem_mcsts, mcsts);
 814         if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
 815             break;
 816         }
 817     }
 818
 819     /*
 820      * program SDRAM Timing Register 1, adding some delays
 821      */
 822     program_tr1();
 823
 824     /*
 825      * if ECC is enabled, initialize parity bits
 826      */
 827
 828         return total_size;
 829 }
 830
 831 unsigned char spd_read(uchar chip, uint addr) {
 832         unsigned char data[2];
 833
 834         if (i2c_read(chip, addr, 1, data, 1) == 0)
 835                 return data[0];
 836         else
 837                 return 0;
 838 }
 839
 840 void get_spd_info(unsigned long*   dimm_populated,
 841                   unsigned char*   iic0_dimm_addr,
 842                   unsigned long    num_dimm_banks)
 843 {
 844     unsigned long dimm_num;
 845     unsigned long dimm_found;
 846     unsigned char num_of_bytes;
 847     unsigned char total_size;
 848
 849     dimm_found = FALSE;
 850     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 851         num_of_bytes = 0;
 852         total_size = 0;
 853
 854         num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 855         total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 856
 857         if ((num_of_bytes != 0) && (total_size != 0)) {
 858             dimm_populated[dimm_num] = TRUE;
 859             dimm_found = TRUE;
 860 #if 0
 861             printf("DIMM slot %lu: populated\n", dimm_num);
 862 #endif
 863         }
 864         else {
 865             dimm_populated[dimm_num] = FALSE;
 866 #if 0
 867             printf("DIMM slot %lu: Not populated\n", dimm_num);
 868 #endif
 869         }
 870     }
 871
 872     if (dimm_found == FALSE) {
 873         printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 874         hang();
 875     }
 876 }
 877
 878 void check_mem_type(unsigned long*   dimm_populated,
 879                     unsigned char*   iic0_dimm_addr,
 880                     unsigned long    num_dimm_banks)
 881 {
 882     unsigned long dimm_num;
 883     unsigned char dimm_type;
 884
 885     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 886         if (dimm_populated[dimm_num] == TRUE) {
 887             dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 888             switch (dimm_type) {
 889             case 7:
 890 #if 0
 891                 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 892 #endif
 893                 break;
 894             default:
 895                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 896                     dimm_num);
 897                 printf("Only DDR SDRAM DIMMs are supported.\n");
 898                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 899                 hang();
 900                 break;
 901             }
 902         }
 903     }
 904 }
 905
 906
 907 void check_volt_type(unsigned long*   dimm_populated,
 908                      unsigned char*   iic0_dimm_addr,
 909                      unsigned long    num_dimm_banks)
 910 {
 911     unsigned long dimm_num;
 912     unsigned long voltage_type;
 913
 914     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 915         if (dimm_populated[dimm_num] == TRUE) {
 916             voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 917             if (voltage_type != 0x04) {
 918                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 919                     dimm_num);
 920                 hang();
 921             }
 922             else {
 923 #if 0
 924                 printf("DIMM %lu voltage level supported.\n", dimm_num);
 925 #endif
 926             }
 927             break;
 928         }
 929     }
 930 }
 931
 932 void program_cfg0(unsigned long* dimm_populated,
 933                   unsigned char* iic0_dimm_addr,
 934                   unsigned long  num_dimm_banks)
 935 {
 936     unsigned long dimm_num;
 937     unsigned long cfg0;
 938     unsigned long ecc_enabled;
 939     unsigned char ecc;
 940     unsigned char attributes;
 941     unsigned long data_width;
 942     unsigned long dimm_32bit;
 943     unsigned long dimm_64bit;
 944
 945     /*
 946      * get Memory Controller Options 0 data
 947      */
 948     mfsdram(mem_cfg0, cfg0);
 949
 950     /*
 951      * clear bits
 952      */
 953     cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 954               SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 955               SDRAM_CFG0_DMWD_MASK |
 956               SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 957
 958
 959     /*
 960      * FIXME: assume the DDR SDRAMs in both banks are the same
 961      */
 962     ecc_enabled = TRUE;
 963     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 964         if (dimm_populated[dimm_num] == TRUE) {
 965             ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 966             if (ecc != 0x02) {
 967                 ecc_enabled = FALSE;
 968             }
 969
 970             /*
 971              * program Registered DIMM Enable
 972              */
 973             attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 974             if ((attributes & 0x02) != 0x00) {
 975                 cfg0 |= SDRAM_CFG0_RDEN;
 976             }
 977
 978             /*
 979              * program DDR SDRAM Data Width
 980              */
 981             data_width =
 982                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 983                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 984             if (data_width == 64 || data_width == 72) {
 985                 dimm_64bit = TRUE;
 986                 cfg0 |= SDRAM_CFG0_DMWD_64;
 987             }
 988             else if (data_width == 32 || data_width == 40) {
 989                 dimm_32bit = TRUE;
 990                 cfg0 |= SDRAM_CFG0_DMWD_32;
 991             }
 992             else {
 993                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 994                     data_width);
 995                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 996                 hang();
 997             }
 998             break;
 999         }
1000     }
1001
1002     /*
1003      * program Memory Data Error Checking
1004      */
1005     if (ecc_enabled == TRUE) {
1006         cfg0 |= SDRAM_CFG0_MCHK_GEN;
1007     }
1008     else {
1009         cfg0 |= SDRAM_CFG0_MCHK_NON;
1010     }
1011
1012     /*
1013      * program Page Management Unit
1014      */
1015     cfg0 |= SDRAM_CFG0_PMUD;
1016
1017     /*
1018      * program Memory Controller Options 0
1019      * Note: DCEN must be enabled after all DDR SDRAM controller
1020      * configuration registers get initialized.
1021      */
1022     mtsdram(mem_cfg0, cfg0);
1023 }
1024
1025 void program_cfg1(unsigned long* dimm_populated,
1026                   unsigned char* iic0_dimm_addr,
1027                   unsigned long  num_dimm_banks)
1028 {
1029     unsigned long cfg1;
1030     mfsdram(mem_cfg1, cfg1);
1031
1032     /*
1033      * Self-refresh exit, disable PM
1034      */
1035     cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
1036
1037     /*
1038      * program Memory Controller Options 1
1039      */
1040     mtsdram(mem_cfg1, cfg1);
1041 }
1042
1043 void program_rtr (unsigned long* dimm_populated,
1044                   unsigned char* iic0_dimm_addr,
1045                   unsigned long  num_dimm_banks)
1046 {
1047     unsigned long dimm_num;
1048     unsigned long bus_period_x_10;
1049     unsigned long refresh_rate = 0;
1050     unsigned char refresh_rate_type;
1051     unsigned long refresh_interval;
1052     unsigned long sdram_rtr;
1053     PPC440_SYS_INFO sys_info;
1054
1055     /*
1056      * get the board info
1057      */
1058     get_sys_info(&sys_info);
1059     bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1060
1061
1062     for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
1063         if (dimm_populated[dimm_num] == TRUE) {
1064             refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1065             switch (refresh_rate_type) {
1066             case 0x00:
1067                 refresh_rate = 15625;
1068                 break;
1069             case 0x011:
1070                 refresh_rate = 15625/4;
1071                 break;
1072             case 0x02:
1073                 refresh_rate = 15625/2;
1074                 break;
1075             case 0x03:
1076                 refresh_rate = 15626*2;
1077                 break;
1078             case 0x04:
1079                 refresh_rate = 15625*4;
1080                 break;
1081             case 0x05:
1082                 refresh_rate = 15625*8;
1083                 break;
1084             default:
1085                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1086                     dimm_num);
1087                 printf("Replace the DIMM module with a supported DIMM.\n");
1088                 break;
1089             }
1090
1091             break;
1092         }
1093     }
1094
1095     refresh_interval = refresh_rate * 10 / bus_period_x_10;
1096     sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
1097
1098     /*
1099      * program Refresh Timer Register (SDRAM0_RTR)
1100      */
1101     mtsdram(mem_rtr, sdram_rtr);
1102 }
1103
1104 void program_tr0 (unsigned long* dimm_populated,
1105                   unsigned char* iic0_dimm_addr,
1106                   unsigned long  num_dimm_banks)
1107 {
1108     unsigned long dimm_num;
1109     unsigned long tr0;
1110     unsigned char wcsbc;
1111     unsigned char t_rp_ns;
1112     unsigned char t_rcd_ns;
1113     unsigned char t_ras_ns;
1114     unsigned long t_rp_clk;
1115     unsigned long t_ras_rcd_clk;
1116     unsigned long t_rcd_clk;
1117     unsigned long t_rfc_clk;
1118     unsigned long plb_check;
1119     unsigned char cas_bit;
1120     unsigned long cas_index;
1121     unsigned char cas_2_0_available;
1122     unsigned char cas_2_5_available;
1123     unsigned char cas_3_0_available;
1124     unsigned long cycle_time_ns_x_10[3];
1125     unsigned long tcyc_3_0_ns_x_10;
1126     unsigned long tcyc_2_5_ns_x_10;
1127     unsigned long tcyc_2_0_ns_x_10;
1128     unsigned long tcyc_reg;
1129     unsigned long bus_period_x_10;
1130     PPC440_SYS_INFO sys_info;
1131     unsigned long residue;
1132
1133     /*
1134      * get the board info
1135      */
1136     get_sys_info(&sys_info);
1137     bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1138
1139     /*
1140      * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1141      */
1142     mfsdram(mem_tr0, tr0);
1143     tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1144              SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1145              SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1146              SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
1147
1148     /*
1149      * initialization
1150      */
1151     wcsbc = 0;
1152     t_rp_ns = 0;
1153     t_rcd_ns = 0;
1154     t_ras_ns = 0;
1155     cas_2_0_available = TRUE;
1156     cas_2_5_available = TRUE;
1157     cas_3_0_available = TRUE;
1158     tcyc_2_0_ns_x_10 = 0;
1159     tcyc_2_5_ns_x_10 = 0;
1160     tcyc_3_0_ns_x_10 = 0;
1161
1162     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1163         if (dimm_populated[dimm_num] == TRUE) {
1164             wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1165             t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1166             t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1167             t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1168             cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1169
1170             for (cas_index = 0; cas_index < 3; cas_index++) {
1171                 switch (cas_index) {
1172                 case 0:
1173                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1174                     break;
1175                 case 1:
1176                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1177                     break;
1178                 default:
1179                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1180                     break;
1181                 }
1182
1183                 if ((tcyc_reg & 0x0F) >= 10) {
1184                     printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1185                         dimm_num);
1186                     hang();
1187                 }
1188
1189                 cycle_time_ns_x_10[cas_index] =
1190                     (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1191             }
1192
1193             cas_index = 0;
1194
1195             if ((cas_bit & 0x80) != 0) {
1196                 cas_index += 3;
1197             }
1198             else if ((cas_bit & 0x40) != 0) {
1199                 cas_index += 2;
1200             }
1201             else if ((cas_bit & 0x20) != 0) {
1202                 cas_index += 1;
1203             }
1204
1205             if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1206                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1207                 cas_index++;
1208             }
1209             else {
1210                 if (cas_index != 0) {
1211                     cas_index++;
1212                 }
1213                 cas_3_0_available = FALSE;
1214             }
1215
1216             if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1217                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1218                 cas_index++;
1219             }
1220             else {
1221                 if (cas_index != 0) {
1222                     cas_index++;
1223                 }
1224                 cas_2_5_available = FALSE;
1225             }
1226
1227             if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1228                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1229                 cas_index++;
1230             }
1231             else {
1232                 if (cas_index != 0) {
1233                     cas_index++;
1234                 }
1235                 cas_2_0_available = FALSE;
1236             }
1237
1238             break;
1239         }
1240     }
1241
1242     /*
1243      * Program SD_WR and SD_WCSBC fields
1244      */
1245     tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
1246     switch (wcsbc) {
1247     case 0:
1248         tr0 |= SDRAM_TR0_SDWD_0_CLK;
1249         break;
1250     default:
1251         tr0 |= SDRAM_TR0_SDWD_1_CLK;
1252         break;
1253     }
1254
1255     /*
1256      * Program SD_CASL field
1257      */
1258     if ((cas_2_0_available == TRUE) &&
1259         (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1260         tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1261     }
1262     else if((cas_2_5_available == TRUE) &&
1263         (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1264         tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1265     }
1266     else if((cas_3_0_available == TRUE) &&
1267         (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1268         tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1269     }
1270     else {
1271         printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1272         printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1273         printf("Make sure the PLB speed is within the supported range.\n");
1274         hang();
1275     }
1276
1277     /*
1278      * Calculate Trp in clock cycles and round up if necessary
1279      * Program SD_PTA field
1280      */
1281     t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1282     plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1283     if (sys_info.freqPLB != plb_check) {
1284         t_rp_clk++;
1285     }
1286     switch ((unsigned long)t_rp_clk) {
1287     case 0:
1288     case 1:
1289     case 2:
1290         tr0 |= SDRAM_TR0_SDPA_2_CLK;
1291         break;
1292     case 3:
1293         tr0 |= SDRAM_TR0_SDPA_3_CLK;
1294         break;
1295     default:
1296         tr0 |= SDRAM_TR0_SDPA_4_CLK;
1297         break;
1298     }
1299
1300     /*
1301      * Program SD_CTP field
1302      */
1303     t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1304     plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1305     if (sys_info.freqPLB != plb_check) {
1306         t_ras_rcd_clk++;
1307     }
1308     switch (t_ras_rcd_clk) {
1309     case 0:
1310     case 1:
1311     case 2:
1312       tr0 |= SDRAM_TR0_SDCP_2_CLK;
1313       break;
1314     case 3:
1315       tr0 |= SDRAM_TR0_SDCP_3_CLK;
1316       break;
1317     case 4:
1318       tr0 |= SDRAM_TR0_SDCP_4_CLK;
1319       break;
1320     default:
1321       tr0 |= SDRAM_TR0_SDCP_5_CLK;
1322       break;
1323     }
1324
1325     /*
1326      * Program SD_LDF field
1327      */
1328     tr0 |= SDRAM_TR0_SDLD_2_CLK;
1329
1330     /*
1331      * Program SD_RFTA field
1332      * FIXME tRFC hardcoded as 75 nanoseconds
1333      */
1334     t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1335     residue = sys_info.freqPLB % (ONE_BILLION / 75);
1336     if (residue >= (ONE_BILLION / 150)) {
1337         t_rfc_clk++;
1338     }
1339     switch (t_rfc_clk) {
1340     case 0:
1341     case 1:
1342     case 2:
1343     case 3:
1344     case 4:
1345     case 5:
1346     case 6:
1347         tr0 |= SDRAM_TR0_SDRA_6_CLK;
1348         break;
1349     case 7:
1350         tr0 |= SDRAM_TR0_SDRA_7_CLK;
1351         break;
1352     case 8:
1353         tr0 |= SDRAM_TR0_SDRA_8_CLK;
1354         break;
1355     case 9:
1356         tr0 |= SDRAM_TR0_SDRA_9_CLK;
1357         break;
1358     case 10:
1359         tr0 |= SDRAM_TR0_SDRA_10_CLK;
1360         break;
1361     case 11:
1362         tr0 |= SDRAM_TR0_SDRA_11_CLK;
1363         break;
1364     case 12:
1365         tr0 |= SDRAM_TR0_SDRA_12_CLK;
1366         break;
1367     default:
1368         tr0 |= SDRAM_TR0_SDRA_13_CLK;
1369         break;
1370     }
1371
1372     /*
1373      * Program SD_RCD field
1374      */
1375     t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1376     plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1377     if (sys_info.freqPLB != plb_check) {
1378         t_rcd_clk++;
1379     }
1380     switch (t_rcd_clk) {
1381     case 0:
1382     case 1:
1383     case 2:
1384         tr0 |= SDRAM_TR0_SDRD_2_CLK;
1385         break;
1386     case 3:
1387         tr0 |= SDRAM_TR0_SDRD_3_CLK;
1388         break;
1389     default:
1390         tr0 |= SDRAM_TR0_SDRD_4_CLK;
1391         break;
1392     }
1393
1394 #if 0
1395     printf("tr0: %x\n", tr0);
1396 #endif
1397     mtsdram(mem_tr0, tr0);
1398 }
1399
1400 void program_tr1 (void)
1401 {
1402     unsigned long tr0;
1403     unsigned long tr1;
1404     unsigned long cfg0;
1405     unsigned long ecc_temp;
1406     unsigned long dlycal;
1407     unsigned long dly_val;
1408     unsigned long i, j, k;
1409     unsigned long bxcr_num;
1410     unsigned long max_pass_length;
1411     unsigned long current_pass_length;
1412     unsigned long current_fail_length;
1413     unsigned long current_start;
1414     unsigned long rdclt;
1415     unsigned long rdclt_offset;
1416     long max_start;
1417     long max_end;
1418     long rdclt_average;
1419     unsigned char window_found;
1420     unsigned char fail_found;
1421     unsigned char pass_found;
1422     unsigned long * membase;
1423     PPC440_SYS_INFO sys_info;
1424
1425     /*
1426      * get the board info
1427      */
1428     get_sys_info(&sys_info);
1429
1430     /*
1431      * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1432      */
1433     mfsdram(mem_tr1, tr1);
1434     tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1435              SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1436
1437     mfsdram(mem_tr0, tr0);
1438     if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1439        (sys_info.freqPLB > 100000000)) {
1440         tr1 |= SDRAM_TR1_RDSS_TR2;
1441         tr1 |= SDRAM_TR1_RDSL_STAGE3;
1442         tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1443     }
1444     else {
1445         tr1 |= SDRAM_TR1_RDSS_TR1;
1446         tr1 |= SDRAM_TR1_RDSL_STAGE2;
1447         tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1448     }
1449
1450     /*
1451      * save CFG0 ECC setting to a temporary variable and turn ECC off
1452      */
1453     mfsdram(mem_cfg0, cfg0);
1454     ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1455     mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1456
1457     /*
1458      * get the delay line calibration register value
1459      */
1460     mfsdram(mem_dlycal, dlycal);
1461     dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1462
1463     max_pass_length = 0;
1464     max_start = 0;
1465     max_end = 0;
1466     current_pass_length = 0;
1467     current_fail_length = 0;
1468     current_start = 0;
1469     rdclt_offset = 0;
1470     window_found = FALSE;
1471     fail_found = FALSE;
1472     pass_found = FALSE;
1473 #ifdef DEBUG
1474     printf("Starting memory test ");
1475 #endif
1476     for (k = 0; k < NUMHALFCYCLES; k++) {
1477         for (rdclt = 0; rdclt < dly_val; rdclt++)  {
1478             /*
1479              * Set the timing reg for the test.
1480              */
1481             mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1482
1483             for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1484                 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1485                 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1486                     /* Bank is enabled */
1487                     membase = (unsigned long*)
1488                         (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1489
1490                     /*
1491                      * Run the short memory test
1492                      */
1493                     for (i = 0; i < NUMMEMTESTS; i++) {
1494                         for (j = 0; j < NUMMEMWORDS; j++) {
1495                             membase[j] = test[i][j];
1496                             ppcDcbf((unsigned long)&(membase[j]));
1497                         }
1498
1499                         for (j = 0; j < NUMMEMWORDS; j++) {
1500                             if (membase[j] != test[i][j]) {
1501                                 ppcDcbf((unsigned long)&(membase[j]));
1502                                 break;
1503                             }
1504                             ppcDcbf((unsigned long)&(membase[j]));
1505                         }
1506
1507                         if (j < NUMMEMWORDS) {
1508                             break;
1509                         }
1510                     }
1511
1512                     /*
1513                      * see if the rdclt value passed
1514                      */
1515                     if (i < NUMMEMTESTS) {
1516                         break;
1517                     }
1518                 }
1519             }
1520
1521             if (bxcr_num == MAXBXCR) {
1522                 if (fail_found == TRUE) {
1523                     pass_found = TRUE;
1524                     if (current_pass_length == 0) {
1525                         current_start = rdclt_offset + rdclt;
1526                     }
1527
1528                     current_fail_length = 0;
1529                     current_pass_length++;
1530
1531                     if (current_pass_length > max_pass_length) {
1532                         max_pass_length = current_pass_length;
1533                         max_start = current_start;
1534                         max_end = rdclt_offset + rdclt;
1535                     }
1536                 }
1537             }
1538             else {
1539                 current_pass_length = 0;
1540                 current_fail_length++;
1541
1542                 if (current_fail_length >= (dly_val>>2)) {
1543                     if (fail_found == FALSE) {
1544                         fail_found = TRUE;
1545                     }
1546                     else if (pass_found == TRUE) {
1547                         window_found = TRUE;
1548                         break;
1549                     }
1550                 }
1551             }
1552         }
1553 #ifdef DEBUG
1554         printf(".");
1555 #endif
1556         if (window_found == TRUE) {
1557             break;
1558         }
1559
1560         tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1561         rdclt_offset += dly_val;
1562     }
1563 #ifdef DEBUG
1564     printf("\n");
1565 #endif
1566
1567     /*
1568      * make sure we find the window
1569      */
1570     if (window_found == FALSE) {
1571        printf("ERROR: Cannot determine a common read delay.\n");
1572        hang();
1573     }
1574
1575     /*
1576      * restore the orignal ECC setting
1577      */
1578     mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1579
1580     /*
1581      * set the SDRAM TR1 RDCD value
1582      */
1583     tr1 &= ~SDRAM_TR1_RDCD_MASK;
1584     if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1585         tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1586     }
1587     else {
1588         tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1589     }
1590
1591     /*
1592      * set the SDRAM TR1 RDCLT value
1593      */
1594     tr1 &= ~SDRAM_TR1_RDCT_MASK;
1595     while (max_end >= (dly_val<<1)) {
1596         max_end -= (dly_val<<1);
1597         max_start -= (dly_val<<1);
1598     }
1599
1600     rdclt_average = ((max_start + max_end) >> 1);
1601     if (rdclt_average >= 0x60)
1602         while(1);
1603
1604     if (rdclt_average < 0) {
1605         rdclt_average = 0;
1606     }
1607
1608     if (rdclt_average >= dly_val) {
1609         rdclt_average -= dly_val;
1610         tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1611     }
1612     tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1613
1614 #if 0
1615     printf("tr1: %x\n", tr1);
1616 #endif
1617     /*
1618      * program SDRAM Timing Register 1 TR1
1619      */
1620     mtsdram(mem_tr1, tr1);
1621 }
1622
1623 unsigned long program_bxcr(unsigned long* dimm_populated,
1624                            unsigned char* iic0_dimm_addr,
1625                            unsigned long  num_dimm_banks)
1626 {
1627     unsigned long dimm_num;
1628     unsigned long bxcr_num;
1629     unsigned long bank_base_addr;
1630     unsigned long bank_size_bytes;
1631     unsigned long cr;
1632     unsigned long i;
1633     unsigned long temp;
1634     unsigned char num_row_addr;
1635     unsigned char num_col_addr;
1636     unsigned char num_banks;
1637     unsigned char bank_size_id;
1638
1639
1640     /*
1641      * Set the BxCR regs.  First, wipe out the bank config registers.
1642      */
1643     for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1644         mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1645         mtdcr(memcfgd, 0x00000000);
1646     }
1647
1648     /*
1649      * reset the bank_base address
1650      */
1651     bank_base_addr = CFG_SDRAM_BASE;
1652
1653     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1654         if (dimm_populated[dimm_num] == TRUE) {
1655             num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1656             num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1657             num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1658             bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1659
1660             /*
1661              * Set the SDRAM0_BxCR regs
1662              */
1663             cr = 0;
1664             bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
1665             switch (bank_size_id) {
1666             case 0x02:
1667                 cr |= SDRAM_BXCR_SDSZ_8;
1668                 break;
1669             case 0x04:
1670                 cr |= SDRAM_BXCR_SDSZ_16;
1671                 break;
1672             case 0x08:
1673                 cr |= SDRAM_BXCR_SDSZ_32;
1674                 break;
1675             case 0x10:
1676                 cr |= SDRAM_BXCR_SDSZ_64;
1677                 break;
1678             case 0x20:
1679                 cr |= SDRAM_BXCR_SDSZ_128;
1680                 break;
1681             case 0x40:
1682                 cr |= SDRAM_BXCR_SDSZ_256;
1683                 break;
1684             case 0x80:
1685                 cr |= SDRAM_BXCR_SDSZ_512;
1686                 break;
1687             default:
1688                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1689                     dimm_num);
1690                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1691                    bank_size_id);
1692                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1693                 hang();
1694             }
1695
1696             switch (num_col_addr) {
1697             case 0x08:
1698                 cr |= SDRAM_BXCR_SDAM_1;
1699                 break;
1700             case 0x09:
1701                 cr |= SDRAM_BXCR_SDAM_2;
1702                 break;
1703             case 0x0A:
1704                 cr |= SDRAM_BXCR_SDAM_3;
1705                 break;
1706             case 0x0B:
1707                 cr |= SDRAM_BXCR_SDAM_4;
1708                 break;
1709             default:
1710                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1711                    dimm_num);
1712                 printf("ERROR: Unsupported value for number of "
1713                    "column addresses: %d.\n", num_col_addr);
1714                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1715                 hang();
1716             }
1717
1718             /*
1719              * enable the bank
1720              */
1721             cr |= SDRAM_BXCR_SDBE;
1722
1723             /*------------------------------------------------------------------
1724             | This next section is hardware dependent and must be programmed
1725             | to match the hardware.
1726             +-----------------------------------------------------------------*/
1727             if (dimm_num == 0) {
1728                 for (i = 0; i < num_banks; i++) {
1729                     mtdcr(memcfga, mem_b0cr + (i << 2));
1730                     temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1731                                               SDRAM_BXCR_SDSZ_MASK |
1732                                               SDRAM_BXCR_SDAM_MASK |
1733                                               SDRAM_BXCR_SDBE);
1734                     cr |= temp;
1735                     cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1736                     mtdcr(memcfgd, cr);
1737                     bank_base_addr += bank_size_bytes;
1738                 }
1739             }
1740             else {
1741                 for (i = 0; i < num_banks; i++) {
1742                     mtdcr(memcfga, mem_b2cr + (i << 2));
1743                     temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1744                                               SDRAM_BXCR_SDSZ_MASK |
1745                                               SDRAM_BXCR_SDAM_MASK |
1746                                               SDRAM_BXCR_SDBE);
1747                     cr |= temp;
1748                     cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1749                     mtdcr(memcfgd, cr);
1750                     bank_base_addr += bank_size_bytes;
1751                 }
1752             }
1753         }
1754     }
1755
1756     return(bank_base_addr);
1757 }
1758
1759 void program_ecc (unsigned long  num_bytes)
1760 {
1761     unsigned long bank_base_addr;
1762     unsigned long current_address;
1763     unsigned long end_address;
1764     unsigned long address_increment;
1765     unsigned long cfg0;
1766
1767     /*
1768      * get Memory Controller Options 0 data
1769      */
1770     mfsdram(mem_cfg0, cfg0);
1771
1772     /*
1773      * reset the bank_base address
1774      */
1775     bank_base_addr = CFG_SDRAM_BASE;
1776
1777     if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1778         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1779             SDRAM_CFG0_MCHK_GEN);
1780
1781         if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1782             address_increment = 4;
1783         }
1784         else {
1785             address_increment = 8;
1786         }
1787
1788         current_address = (unsigned long)(bank_base_addr);
1789         end_address = (unsigned long)(bank_base_addr) + num_bytes;
1790
1791         while (current_address < end_address) {
1792             *((unsigned long*)current_address) = 0x00000000;
1793             current_address += address_increment;
1794         }
1795
1796         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1797             SDRAM_CFG0_MCHK_CHK);
1798     }
1799 }
1800
1801 #endif /* CONFIG_440 */
1802
1803 #endif /* CONFIG_SPD_EEPROM */