git.sur5r.net Git - u-boot/blob - drivers/clk/clk_zynqmp.c

   1 /*
   2  * ZynqMP clock driver
   3  *
   4  * Copyright (C) 2016 Xilinx, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <linux/bitops.h>
  11 #include <clk-uclass.h>
  12 #include <clk.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <dm.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
  19 static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
  20 static const resource_size_t zynqmp_iou_clkc_base = 0xff180000;
  21
  22 /* Full power domain clocks */
  23 #define CRF_APB_APLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x00)
  24 #define CRF_APB_DPLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x0c)
  25 #define CRF_APB_VPLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x18)
  26 #define CRF_APB_PLL_STATUS              (zynqmp_crf_apb_clkc_base + 0x24)
  27 #define CRF_APB_APLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x28)
  28 #define CRF_APB_DPLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x2c)
  29 #define CRF_APB_VPLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x30)
  30 /* Peripheral clocks */
  31 #define CRF_APB_ACPU_CTRL               (zynqmp_crf_apb_clkc_base + 0x40)
  32 #define CRF_APB_DBG_TRACE_CTRL          (zynqmp_crf_apb_clkc_base + 0x44)
  33 #define CRF_APB_DBG_FPD_CTRL            (zynqmp_crf_apb_clkc_base + 0x48)
  34 #define CRF_APB_DP_VIDEO_REF_CTRL       (zynqmp_crf_apb_clkc_base + 0x50)
  35 #define CRF_APB_DP_AUDIO_REF_CTRL       (zynqmp_crf_apb_clkc_base + 0x54)
  36 #define CRF_APB_DP_STC_REF_CTRL         (zynqmp_crf_apb_clkc_base + 0x5c)
  37 #define CRF_APB_DDR_CTRL                (zynqmp_crf_apb_clkc_base + 0x60)
  38 #define CRF_APB_GPU_REF_CTRL            (zynqmp_crf_apb_clkc_base + 0x64)
  39 #define CRF_APB_SATA_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x80)
  40 #define CRF_APB_PCIE_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x94)
  41 #define CRF_APB_GDMA_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x98)
  42 #define CRF_APB_DPDMA_REF_CTRL          (zynqmp_crf_apb_clkc_base + 0x9c)
  43 #define CRF_APB_TOPSW_MAIN_CTRL         (zynqmp_crf_apb_clkc_base + 0xa0)
  44 #define CRF_APB_TOPSW_LSBUS_CTRL        (zynqmp_crf_apb_clkc_base + 0xa4)
  45 #define CRF_APB_GTGREF0_REF_CTRL        (zynqmp_crf_apb_clkc_base + 0xa8)
  46 #define CRF_APB_DBG_TSTMP_CTRL          (zynqmp_crf_apb_clkc_base + 0xd8)
  47
  48 /* Low power domain clocks */
  49 #define CRL_APB_IOPLL_CTRL              (zynqmp_crl_apb_clkc_base + 0x00)
  50 #define CRL_APB_RPLL_CTRL               (zynqmp_crl_apb_clkc_base + 0x10)
  51 #define CRL_APB_PLL_STATUS              (zynqmp_crl_apb_clkc_base + 0x20)
  52 #define CRL_APB_IOPLL_TO_FPD_CTRL       (zynqmp_crl_apb_clkc_base + 0x24)
  53 #define CRL_APB_RPLL_TO_FPD_CTRL        (zynqmp_crl_apb_clkc_base + 0x28)
  54 /* Peripheral clocks */
  55 #define CRL_APB_USB3_DUAL_REF_CTRL      (zynqmp_crl_apb_clkc_base + 0x2c)
  56 #define CRL_APB_GEM0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x30)
  57 #define CRL_APB_GEM1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x34)
  58 #define CRL_APB_GEM2_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x38)
  59 #define CRL_APB_GEM3_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x3c)
  60 #define CRL_APB_USB0_BUS_REF_CTRL       (zynqmp_crl_apb_clkc_base + 0x40)
  61 #define CRL_APB_USB1_BUS_REF_CTRL       (zynqmp_crl_apb_clkc_base + 0x44)
  62 #define CRL_APB_QSPI_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x48)
  63 #define CRL_APB_SDIO0_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x4c)
  64 #define CRL_APB_SDIO1_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x50)
  65 #define CRL_APB_UART0_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x54)
  66 #define CRL_APB_UART1_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x58)
  67 #define CRL_APB_SPI0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x5c)
  68 #define CRL_APB_SPI1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x60)
  69 #define CRL_APB_CAN0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x64)
  70 #define CRL_APB_CAN1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x68)
  71 #define CRL_APB_CPU_R5_CTRL             (zynqmp_crl_apb_clkc_base + 0x70)
  72 #define CRL_APB_IOU_SWITCH_CTRL         (zynqmp_crl_apb_clkc_base + 0x7c)
  73 #define CRL_APB_CSU_PLL_CTRL            (zynqmp_crl_apb_clkc_base + 0x80)
  74 #define CRL_APB_PCAP_CTRL               (zynqmp_crl_apb_clkc_base + 0x84)
  75 #define CRL_APB_LPD_SWITCH_CTRL         (zynqmp_crl_apb_clkc_base + 0x88)
  76 #define CRL_APB_LPD_LSBUS_CTRL          (zynqmp_crl_apb_clkc_base + 0x8c)
  77 #define CRL_APB_DBG_LPD_CTRL            (zynqmp_crl_apb_clkc_base + 0x90)
  78 #define CRL_APB_NAND_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x94)
  79 #define CRL_APB_ADMA_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x98)
  80 #define CRL_APB_PL0_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa0)
  81 #define CRL_APB_PL1_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa4)
  82 #define CRL_APB_PL2_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa8)
  83 #define CRL_APB_PL3_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xac)
  84 #define CRL_APB_PL0_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xb4)
  85 #define CRL_APB_PL1_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xbc)
  86 #define CRL_APB_PL2_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xc4)
  87 #define CRL_APB_PL3_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xdc)
  88 #define CRL_APB_GEM_TSU_REF_CTRL        (zynqmp_crl_apb_clkc_base + 0xe0)
  89 #define CRL_APB_DLL_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xe4)
  90 #define CRL_APB_AMS_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xe8)
  91 #define CRL_APB_I2C0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x100)
  92 #define CRL_APB_I2C1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x104)
  93 #define CRL_APB_TIMESTAMP_REF_CTRL      (zynqmp_crl_apb_clkc_base + 0x108)
  94 #define IOU_SLCR_GEM_CLK_CTRL           (zynqmp_iou_clkc_base + 0x308)
  95 #define IOU_SLCR_CAN_MIO_CTRL           (zynqmp_iou_clkc_base + 0x304)
  96 #define IOU_SLCR_WDT_CLK_SEL            (zynqmp_iou_clkc_base + 0x300)
  97
  98 #define ZYNQ_CLK_MAXDIV         0x3f
  99 #define CLK_CTRL_DIV1_SHIFT     16
 100 #define CLK_CTRL_DIV1_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
 101 #define CLK_CTRL_DIV0_SHIFT     8
 102 #define CLK_CTRL_DIV0_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
 103 #define CLK_CTRL_SRCSEL_SHIFT   0
 104 #define CLK_CTRL_SRCSEL_MASK    (0x3 << CLK_CTRL_SRCSEL_SHIFT)
 105 #define PLLCTRL_FBDIV_MASK      0x7f00
 106 #define PLLCTRL_FBDIV_SHIFT     8
 107 #define PLLCTRL_RESET_MASK      1
 108 #define PLLCTRL_RESET_SHIFT     0
 109 #define PLLCTRL_BYPASS_MASK     0x8
 110 #define PLLCTRL_BYPASS_SHFT     3
 111 #define PLLCTRL_POST_SRC_SHFT   24
 112 #define PLLCTRL_POST_SRC_MASK   (0x7 << PLLCTRL_POST_SRC_SHFT)
 113
 114
 115 #define NUM_MIO_PINS    77
 116
 117 enum zynqmp_clk {
 118         iopll, rpll,
 119         apll, dpll, vpll,
 120         iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
 121         acpu, acpu_half,
 122         dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
 123         dp_video_ref, dp_audio_ref,
 124         dp_stc_ref, gdma_ref, dpdma_ref,
 125         ddr_ref, sata_ref, pcie_ref,
 126         gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
 127         topsw_main, topsw_lsbus,
 128         gtgref0_ref,
 129         lpd_switch, lpd_lsbus,
 130         usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
 131         cpu_r5, cpu_r5_core,
 132         csu_spb, csu_pll, pcap,
 133         iou_switch,
 134         gem_tsu_ref, gem_tsu,
 135         gem0_ref, gem1_ref, gem2_ref, gem3_ref,
 136         gem0_rx, gem1_rx, gem2_rx, gem3_rx,
 137         qspi_ref,
 138         sdio0_ref, sdio1_ref,
 139         uart0_ref, uart1_ref,
 140         spi0_ref, spi1_ref,
 141         nand_ref,
 142         i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
 143         dll_ref,
 144         adma_ref,
 145         timestamp_ref,
 146         ams_ref,
 147         pl0, pl1, pl2, pl3,
 148         wdt,
 149         clk_max,
 150 };
 151
 152 static const char * const clk_names[clk_max] = {
 153         "iopll", "rpll", "apll", "dpll",
 154         "vpll", "iopll_to_fpd", "rpll_to_fpd",
 155         "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
 156         "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
 157         "dbg_trace", "dbg_tstmp", "dp_video_ref",
 158         "dp_audio_ref", "dp_stc_ref", "gdma_ref",
 159         "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
 160         "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
 161         "topsw_main", "topsw_lsbus", "gtgref0_ref",
 162         "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
 163         "usb1_bus_ref", "usb3_dual_ref", "usb0",
 164         "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
 165         "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
 166         "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
 167         "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
 168         "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
 169         "uart0_ref", "uart1_ref", "spi0_ref",
 170         "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
 171         "can0_ref", "can1_ref", "can0", "can1",
 172         "dll_ref", "adma_ref", "timestamp_ref",
 173         "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
 174 };
 175
 176 struct zynqmp_clk_priv {
 177         unsigned long ps_clk_freq;
 178         unsigned long video_clk;
 179         unsigned long pss_alt_ref_clk;
 180         unsigned long gt_crx_ref_clk;
 181         unsigned long aux_ref_clk;
 182 };
 183
 184 static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
 185 {
 186         switch (id) {
 187         case iopll:
 188                 return CRL_APB_IOPLL_CTRL;
 189         case rpll:
 190                 return CRL_APB_RPLL_CTRL;
 191         case apll:
 192                 return CRF_APB_APLL_CTRL;
 193         case dpll:
 194                 return CRF_APB_DPLL_CTRL;
 195         case vpll:
 196                 return CRF_APB_VPLL_CTRL;
 197         case acpu:
 198                 return CRF_APB_ACPU_CTRL;
 199         case ddr_ref:
 200                 return CRF_APB_DDR_CTRL;
 201         case qspi_ref:
 202                 return CRL_APB_QSPI_REF_CTRL;
 203         case gem0_ref:
 204                 return CRL_APB_GEM0_REF_CTRL;
 205         case gem1_ref:
 206                 return CRL_APB_GEM1_REF_CTRL;
 207         case gem2_ref:
 208                 return CRL_APB_GEM2_REF_CTRL;
 209         case gem3_ref:
 210                 return CRL_APB_GEM3_REF_CTRL;
 211         case uart0_ref:
 212                 return CRL_APB_UART0_REF_CTRL;
 213         case uart1_ref:
 214                 return CRL_APB_UART1_REF_CTRL;
 215         case sdio0_ref:
 216                 return CRL_APB_SDIO0_REF_CTRL;
 217         case sdio1_ref:
 218                 return CRL_APB_SDIO1_REF_CTRL;
 219         case spi0_ref:
 220                 return CRL_APB_SPI0_REF_CTRL;
 221         case spi1_ref:
 222                 return CRL_APB_SPI1_REF_CTRL;
 223         case nand_ref:
 224                 return CRL_APB_NAND_REF_CTRL;
 225         case i2c0_ref:
 226                 return CRL_APB_I2C0_REF_CTRL;
 227         case i2c1_ref:
 228                 return CRL_APB_I2C1_REF_CTRL;
 229         case can0_ref:
 230                 return CRL_APB_CAN0_REF_CTRL;
 231         case can1_ref:
 232                 return CRL_APB_CAN1_REF_CTRL;
 233         default:
 234                 debug("Invalid clk id%d\n", id);
 235         }
 236         return 0;
 237 }
 238
 239 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
 240 {
 241         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 242                       CLK_CTRL_SRCSEL_SHIFT;
 243
 244         switch (srcsel) {
 245         case 2:
 246                 return dpll;
 247         case 3:
 248                 return vpll;
 249         case 0 ... 1:
 250         default:
 251                 return apll;
 252         }
 253 }
 254
 255 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
 256 {
 257         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 258                       CLK_CTRL_SRCSEL_SHIFT;
 259
 260         switch (srcsel) {
 261         case 1:
 262                 return vpll;
 263         case 0:
 264         default:
 265                 return dpll;
 266         }
 267 }
 268
 269 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
 270 {
 271         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 272                       CLK_CTRL_SRCSEL_SHIFT;
 273
 274         switch (srcsel) {
 275         case 2:
 276                 return rpll;
 277         case 3:
 278                 return dpll;
 279         case 0 ... 1:
 280         default:
 281                 return iopll;
 282         }
 283 }
 284
 285 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
 286                                     struct zynqmp_clk_priv *priv,
 287                                     bool is_pre_src)
 288 {
 289         u32 src_sel;
 290
 291         if (is_pre_src)
 292                 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
 293                            PLLCTRL_POST_SRC_SHFT;
 294         else
 295                 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
 296                            PLLCTRL_POST_SRC_SHFT;
 297
 298         switch (src_sel) {
 299         case 4:
 300                 return priv->video_clk;
 301         case 5:
 302                 return priv->pss_alt_ref_clk;
 303         case 6:
 304                 return priv->aux_ref_clk;
 305         case 7:
 306                 return priv->gt_crx_ref_clk;
 307         case 0 ... 3:
 308         default:
 309         return priv->ps_clk_freq;
 310         }
 311 }
 312
 313 static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
 314                                      enum zynqmp_clk id)
 315 {
 316         u32 clk_ctrl, reset, mul;
 317         ulong freq;
 318         int ret;
 319
 320         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 321         if (ret)
 322                 panic("%s mio read fail\n", __func__);
 323
 324         if (clk_ctrl & PLLCTRL_BYPASS_MASK)
 325                 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
 326         else
 327                 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
 328
 329         reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
 330         if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
 331                 return 0;
 332
 333         mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
 334
 335         freq *= mul;
 336
 337         if (clk_ctrl & (1 << 16))
 338                 freq /= 2;
 339
 340         return freq;
 341 }
 342
 343 static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
 344                                      enum zynqmp_clk id)
 345 {
 346         u32 clk_ctrl, div;
 347         enum zynqmp_clk pll;
 348         int ret;
 349
 350         ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
 351         if (ret)
 352                 panic("%s mio read fail\n", __func__);
 353
 354
 355         div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 356
 357         pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
 358
 359         return DIV_ROUND_CLOSEST(zynqmp_clk_get_pll_rate(priv, pll), div);
 360 }
 361
 362 static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
 363 {
 364         u32 clk_ctrl, div;
 365         enum zynqmp_clk pll;
 366         int ret;
 367
 368         ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
 369         if (ret)
 370                 panic("%s mio read fail\n", __func__);
 371
 372         div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 373
 374         pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
 375
 376         return DIV_ROUND_CLOSEST(zynqmp_clk_get_pll_rate(priv, pll), div);
 377 }
 378
 379 static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
 380                                           enum zynqmp_clk id, bool two_divs)
 381 {
 382         enum zynqmp_clk pll;
 383         u32 clk_ctrl, div0;
 384         u32 div1 = 1;
 385         int ret;
 386
 387         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 388         if (ret)
 389                 panic("%s mio read fail\n", __func__);
 390
 391         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 392         if (!div0)
 393                 div0 = 1;
 394
 395         if (two_divs) {
 396                 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 397                 if (!div1)
 398                         div1 = 1;
 399         }
 400
 401         pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
 402
 403         return
 404                 DIV_ROUND_CLOSEST(
 405                         DIV_ROUND_CLOSEST(
 406                                 zynqmp_clk_get_pll_rate(priv, pll), div0),
 407                         div1);
 408 }
 409
 410 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
 411                                                        ulong pll_rate,
 412                                                        u32 *div0, u32 *div1)
 413 {
 414         long new_err, best_err = (long)(~0UL >> 1);
 415         ulong new_rate, best_rate = 0;
 416         u32 d0, d1;
 417
 418         for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
 419                 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
 420                         new_rate = DIV_ROUND_CLOSEST(
 421                                         DIV_ROUND_CLOSEST(pll_rate, d0), d1);
 422                         new_err = abs(new_rate - rate);
 423
 424                         if (new_err < best_err) {
 425                                 *div0 = d0;
 426                                 *div1 = d1;
 427                                 best_err = new_err;
 428                                 best_rate = new_rate;
 429                         }
 430                 }
 431         }
 432
 433         return best_rate;
 434 }
 435
 436 static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
 437                                           enum zynqmp_clk id, ulong rate,
 438                                           bool two_divs)
 439 {
 440         enum zynqmp_clk pll;
 441         u32 clk_ctrl, div0 = 0, div1 = 0;
 442         ulong pll_rate, new_rate;
 443         u32 reg;
 444         int ret;
 445         u32 mask;
 446
 447         reg = zynqmp_clk_get_register(id);
 448         ret = zynqmp_mmio_read(reg, &clk_ctrl);
 449         if (ret)
 450                 panic("%s mio read fail\n", __func__);
 451
 452         pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
 453         pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
 454         clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
 455         if (two_divs) {
 456                 clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
 457                 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
 458                                 &div0, &div1);
 459                 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
 460         } else {
 461                 div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
 462                 if (div0 > ZYNQ_CLK_MAXDIV)
 463                         div0 = ZYNQ_CLK_MAXDIV;
 464                 new_rate = DIV_ROUND_CLOSEST(rate, div0);
 465         }
 466         clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
 467
 468         mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
 469                (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
 470
 471         ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
 472         if (ret)
 473                 panic("%s mio write fail\n", __func__);
 474
 475         return new_rate;
 476 }
 477
 478 static ulong zynqmp_clk_get_rate(struct clk *clk)
 479 {
 480         struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
 481         enum zynqmp_clk id = clk->id;
 482         bool two_divs = false;
 483
 484         switch (id) {
 485         case iopll ... vpll:
 486                 return zynqmp_clk_get_pll_rate(priv, id);
 487         case acpu:
 488                 return zynqmp_clk_get_cpu_rate(priv, id);
 489         case ddr_ref:
 490                 return zynqmp_clk_get_ddr_rate(priv);
 491         case gem0_ref ... gem3_ref:
 492         case qspi_ref ... can1_ref:
 493                 two_divs = true;
 494                 return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
 495         default:
 496                 return -ENXIO;
 497         }
 498 }
 499
 500 static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
 501 {
 502         struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
 503         enum zynqmp_clk id = clk->id;
 504         bool two_divs = true;
 505
 506         switch (id) {
 507         case gem0_ref ... gem3_ref:
 508         case qspi_ref ... can1_ref:
 509                 return zynqmp_clk_set_peripheral_rate(priv, id,
 510                                                       rate, two_divs);
 511         default:
 512                 return -ENXIO;
 513         }
 514 }
 515
 516 int soc_clk_dump(void)
 517 {
 518         struct udevice *dev;
 519         int i, ret;
 520
 521         ret = uclass_get_device_by_driver(UCLASS_CLK,
 522                 DM_GET_DRIVER(zynqmp_clk), &dev);
 523         if (ret)
 524                 return ret;
 525
 526         printf("clk\t\tfrequency\n");
 527         for (i = 0; i < clk_max; i++) {
 528                 const char *name = clk_names[i];
 529                 if (name) {
 530                         struct clk clk;
 531                         unsigned long rate;
 532
 533                         clk.id = i;
 534                         ret = clk_request(dev, &clk);
 535                         if (ret < 0)
 536                                 return ret;
 537
 538                         rate = clk_get_rate(&clk);
 539
 540                         clk_free(&clk);
 541
 542                         if ((rate == (unsigned long)-ENOSYS) ||
 543                             (rate == (unsigned long)-ENXIO))
 544                                 printf("%10s%20s\n", name, "unknown");
 545                         else
 546                                 printf("%10s%20lu\n", name, rate);
 547                 }
 548         }
 549
 550         return 0;
 551 }
 552
 553 static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
 554 {
 555         struct clk clk;
 556         int ret;
 557
 558         ret = clk_get_by_name(dev, name, &clk);
 559         if (ret < 0) {
 560                 dev_err(dev, "failed to get %s\n", name);
 561                 return ret;
 562         }
 563
 564         *freq = clk_get_rate(&clk);
 565         if (IS_ERR_VALUE(*freq)) {
 566                 dev_err(dev, "failed to get rate %s\n", name);
 567                 return -EINVAL;
 568         }
 569
 570         return 0;
 571 }
 572 static int zynqmp_clk_probe(struct udevice *dev)
 573 {
 574         int ret;
 575         struct zynqmp_clk_priv *priv = dev_get_priv(dev);
 576
 577         debug("%s\n", __func__);
 578         ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
 579         if (ret < 0)
 580                 return -EINVAL;
 581
 582         ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
 583         if (ret < 0)
 584                 return -EINVAL;
 585
 586         ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
 587                                       &priv->pss_alt_ref_clk);
 588         if (ret < 0)
 589                 return -EINVAL;
 590
 591         ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
 592         if (ret < 0)
 593                 return -EINVAL;
 594
 595         ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
 596                                       &priv->gt_crx_ref_clk);
 597         if (ret < 0)
 598                 return -EINVAL;
 599
 600         return 0;
 601 }
 602
 603 static struct clk_ops zynqmp_clk_ops = {
 604         .set_rate = zynqmp_clk_set_rate,
 605         .get_rate = zynqmp_clk_get_rate,
 606 };
 607
 608 static const struct udevice_id zynqmp_clk_ids[] = {
 609         { .compatible = "xlnx,zynqmp-clkc" },
 610         { }
 611 };
 612
 613 U_BOOT_DRIVER(zynqmp_clk) = {
 614         .name = "zynqmp-clk",
 615         .id = UCLASS_CLK,
 616         .of_match = zynqmp_clk_ids,
 617         .probe = zynqmp_clk_probe,
 618         .ops = &zynqmp_clk_ops,
 619         .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
 620 };