git.sur5r.net Git - u-boot/blob - drivers/clk/rockchip/clk_rk3128.c

   1 /*
   2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/cru_rk3128.h>
  15 #include <asm/arch/hardware.h>
  16 #include <bitfield.h>
  17 #include <dm/lists.h>
  18 #include <dt-bindings/clock/rk3128-cru.h>
  19 #include <linux/log2.h>
  20
  21 enum {
  22         VCO_MAX_HZ      = 2400U * 1000000,
  23         VCO_MIN_HZ      = 600 * 1000000,
  24         OUTPUT_MAX_HZ   = 2400U * 1000000,
  25         OUTPUT_MIN_HZ   = 24 * 1000000,
  26 };
  27
  28 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  29
  30 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  31         .refdiv = _refdiv,\
  32         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  33         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  34
  35 /* use integer mode*/
  36 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  38
  39 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id,
  40                          const struct pll_div *div)
  41 {
  42         int pll_id = rk_pll_id(clk_id);
  43         struct rk3128_pll *pll = &cru->pll[pll_id];
  44
  45         /* All PLLs have same VCO and output frequency range restrictions. */
  46         uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  47         uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  48
  49         debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n",
  50               pll, div->fbdiv, div->refdiv, div->postdiv1,
  51               div->postdiv2, vco_hz, output_hz);
  52         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  53                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  54
  55         /* use integer mode */
  56         rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  57         /* Power down */
  58         rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
  59
  60         rk_clrsetreg(&pll->con0,
  61                      PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  62                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  63         rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  64                      (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  65                      div->refdiv << PLL_REFDIV_SHIFT));
  66
  67         /* Power Up */
  68         rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
  69
  70         /* waiting for pll lock */
  71         while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  72                 udelay(1);
  73
  74         return 0;
  75 }
  76
  77 static int pll_para_config(u32 freq_hz, struct pll_div *div)
  78 {
  79         u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0;
  80         u32 postdiv1, postdiv2 = 1;
  81         u32 fref_khz;
  82         u32 diff_khz, best_diff_khz;
  83         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
  84         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
  85         u32 vco_khz;
  86         u32 freq_khz = freq_hz / 1000;
  87
  88         if (!freq_hz) {
  89                 printf("%s: the frequency can't be 0 Hz\n", __func__);
  90                 return -1;
  91         }
  92
  93         postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz);
  94         if (postdiv1 > max_postdiv1) {
  95                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
  96                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
  97         }
  98
  99         vco_khz = freq_khz * postdiv1 * postdiv2;
 100
 101         if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) ||
 102             postdiv2 > max_postdiv2) {
 103                 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n",
 104                        __func__, freq_hz);
 105                 return -1;
 106         }
 107
 108         div->postdiv1 = postdiv1;
 109         div->postdiv2 = postdiv2;
 110
 111         best_diff_khz = vco_khz;
 112         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 113                 fref_khz = ref_khz / refdiv;
 114
 115                 fbdiv = vco_khz / fref_khz;
 116                 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
 117                         continue;
 118                 diff_khz = vco_khz - fbdiv * fref_khz;
 119                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 120                         fbdiv++;
 121                         diff_khz = fref_khz - diff_khz;
 122                 }
 123
 124                 if (diff_khz >= best_diff_khz)
 125                         continue;
 126
 127                 best_diff_khz = diff_khz;
 128                 div->refdiv = refdiv;
 129                 div->fbdiv = fbdiv;
 130         }
 131
 132         if (best_diff_khz > 4 * (1000)) {
 133                 printf("%s: Failed to match output frequency %u bestis %u Hz\n",
 134                        __func__, freq_hz,
 135                        best_diff_khz * 1000);
 136                 return -1;
 137         }
 138         return 0;
 139 }
 140
 141 static void rkclk_init(struct rk3128_cru *cru)
 142 {
 143         u32 aclk_div;
 144         u32 hclk_div;
 145         u32 pclk_div;
 146
 147         /* pll enter slow-mode */
 148         rk_clrsetreg(&cru->cru_mode_con,
 149                      GPLL_MODE_MASK | APLL_MODE_MASK,
 150                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 151                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 152
 153         /* init pll */
 154         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 155         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 156
 157         /*
 158          * select apll as cpu/core clock pll source and
 159          * set up dependent divisors for PERI and ACLK clocks.
 160          * core hz : apll = 1:1
 161          */
 162         aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
 163         assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
 164
 165         pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
 166         assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
 167
 168         rk_clrsetreg(&cru->cru_clksel_con[0],
 169                      CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
 170                      CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
 171                      0 << CORE_DIV_CON_SHIFT);
 172
 173         rk_clrsetreg(&cru->cru_clksel_con[1],
 174                      CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
 175                      aclk_div << CORE_ACLK_DIV_SHIFT |
 176                      pclk_div << CORE_PERI_DIV_SHIFT);
 177
 178         /*
 179          * select gpll as pd_bus bus clock source and
 180          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 181          */
 182         aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
 183         assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 184
 185         pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
 186         assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
 187
 188         hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
 189         assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
 190
 191         rk_clrsetreg(&cru->cru_clksel_con[0],
 192                      BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
 193                      BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
 194                      aclk_div << BUS_ACLK_DIV_SHIFT);
 195
 196         rk_clrsetreg(&cru->cru_clksel_con[1],
 197                      BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
 198                      pclk_div << BUS_PCLK_DIV_SHIFT |
 199                      hclk_div << BUS_HCLK_DIV_SHIFT);
 200
 201         /*
 202          * select gpll as pd_peri bus clock source and
 203          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 204          */
 205         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 206         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 207
 208         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 209         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 210                 PERI_ACLK_HZ && (hclk_div < 0x4));
 211
 212         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 213         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 214                 PERI_ACLK_HZ && pclk_div < 0x8);
 215
 216         rk_clrsetreg(&cru->cru_clksel_con[10],
 217                      PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
 218                      PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
 219                      PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
 220                      pclk_div << PERI_PCLK_DIV_SHIFT |
 221                      hclk_div << PERI_HCLK_DIV_SHIFT |
 222                      aclk_div << PERI_ACLK_DIV_SHIFT);
 223
 224         /* PLL enter normal-mode */
 225         rk_clrsetreg(&cru->cru_mode_con,
 226                      GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK,
 227                      GPLL_MODE_NORM << GPLL_MODE_SHIFT |
 228                      APLL_MODE_NORM << APLL_MODE_SHIFT |
 229                      CPLL_MODE_NORM << CPLL_MODE_SHIFT);
 230
 231         /*fix NAND controller  working clock max to 150Mhz */
 232         rk_clrsetreg(&cru->cru_clksel_con[2],
 233                      NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK,
 234                      NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT |
 235                      3 << NANDC_CLK_DIV_SHIFT);
 236 }
 237
 238 /* Get pll rate by id */
 239 static u32 rkclk_pll_get_rate(struct rk3128_cru *cru,
 240                               enum rk_clk_id clk_id)
 241 {
 242         u32 refdiv, fbdiv, postdiv1, postdiv2;
 243         u32 con;
 244         int pll_id = rk_pll_id(clk_id);
 245         struct rk3128_pll *pll = &cru->pll[pll_id];
 246         static u8 clk_shift[CLK_COUNT] = {
 247                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 248                 GPLL_MODE_SHIFT, 0xff
 249         };
 250         static u32 clk_mask[CLK_COUNT] = {
 251                 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
 252                 GPLL_MODE_MASK, 0xff
 253         };
 254         uint shift;
 255         uint mask;
 256
 257         con = readl(&cru->cru_mode_con);
 258         shift = clk_shift[clk_id];
 259         mask = clk_mask[clk_id];
 260
 261         switch ((con & mask) >> shift) {
 262         case GPLL_MODE_SLOW:
 263                 return OSC_HZ;
 264         case GPLL_MODE_NORM:
 265                 /* normal mode */
 266                 con = readl(&pll->con0);
 267                 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
 268                 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
 269                 con = readl(&pll->con1);
 270                 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
 271                 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
 272                 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
 273         case GPLL_MODE_DEEP:
 274         default:
 275                 return 32768;
 276         }
 277 }
 278
 279 static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
 280                                   int periph)
 281 {
 282         uint src_rate;
 283         uint div, mux;
 284         u32 con;
 285
 286         switch (periph) {
 287         case HCLK_EMMC:
 288         case SCLK_EMMC:
 289         case SCLK_EMMC_SAMPLE:
 290                 con = readl(&cru->cru_clksel_con[12]);
 291                 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 292                 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 293                 break;
 294         case HCLK_SDMMC:
 295         case SCLK_SDMMC:
 296                 con = readl(&cru->cru_clksel_con[11]);
 297                 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
 298                 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 299                 break;
 300         default:
 301                 return -EINVAL;
 302         }
 303
 304         src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
 305         return DIV_TO_RATE(src_rate, div);
 306 }
 307
 308 static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
 309                                   int periph, uint freq)
 310 {
 311         int src_clk_div;
 312         int mux;
 313
 314         debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
 315
 316         /* mmc clock defaulg div 2 internal, need provide double in cru */
 317         src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
 318
 319         if (src_clk_div > 128) {
 320                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
 321                 mux = EMMC_SEL_24M;
 322         } else {
 323                 mux = EMMC_SEL_GPLL;
 324         }
 325
 326         switch (periph) {
 327         case HCLK_EMMC:
 328                 rk_clrsetreg(&cru->cru_clksel_con[12],
 329                              EMMC_PLL_MASK | EMMC_DIV_MASK,
 330                              mux << EMMC_PLL_SHIFT |
 331                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 332                 break;
 333         case HCLK_SDMMC:
 334         case SCLK_SDMMC:
 335                 rk_clrsetreg(&cru->cru_clksel_con[11],
 336                              MMC0_PLL_MASK | MMC0_DIV_MASK,
 337                              mux << MMC0_PLL_SHIFT |
 338                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 339                 break;
 340         default:
 341                 return -EINVAL;
 342         }
 343
 344         return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
 345 }
 346
 347 static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
 348 {
 349         u32 div, con;
 350
 351         switch (clk_id) {
 352         case PCLK_I2C0:
 353         case PCLK_I2C1:
 354         case PCLK_I2C2:
 355         case PCLK_I2C3:
 356         case PCLK_PWM:
 357                 con = readl(&cru->cru_clksel_con[10]);
 358                 div = con >> 12 & 0x3;
 359                 break;
 360         default:
 361                 printf("do not support this peripheral bus\n");
 362                 return -EINVAL;
 363         }
 364
 365         return DIV_TO_RATE(PERI_ACLK_HZ, div);
 366 }
 367
 368 static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz)
 369 {
 370         int src_clk_div;
 371
 372         src_clk_div = PERI_ACLK_HZ / hz;
 373         assert(src_clk_div - 1 < 4);
 374
 375         switch (clk_id) {
 376         case PCLK_I2C0:
 377         case PCLK_I2C1:
 378         case PCLK_I2C2:
 379         case PCLK_I2C3:
 380         case PCLK_PWM:
 381                 rk_setreg(&cru->cru_clksel_con[10],
 382                           ((src_clk_div - 1) << 12));
 383                 break;
 384         default:
 385                 printf("do not support this peripheral bus\n");
 386                 return -EINVAL;
 387         }
 388
 389         return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div);
 390 }
 391
 392 static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru)
 393 {
 394         u32 div, val;
 395
 396         val = readl(&cru->cru_clksel_con[24]);
 397         div = bitfield_extract(val, SARADC_DIV_CON_SHIFT,
 398                                SARADC_DIV_CON_WIDTH);
 399
 400         return DIV_TO_RATE(OSC_HZ, div);
 401 }
 402
 403 static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz)
 404 {
 405         int src_clk_div;
 406
 407         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 408         assert(src_clk_div < 128);
 409
 410         rk_clrsetreg(&cru->cru_clksel_con[24],
 411                      SARADC_DIV_CON_MASK,
 412                      src_clk_div << SARADC_DIV_CON_SHIFT);
 413
 414         return rk3128_saradc_get_clk(cru);
 415 }
 416
 417 static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
 418 {
 419         int src_clk_div;
 420         struct pll_div cpll_config = {0};
 421
 422         src_clk_div = GPLL_HZ / hz;
 423         assert(src_clk_div - 1 < 31);
 424
 425         switch (clk_id) {
 426         case ACLK_VIO0:
 427                 rk_clrsetreg(&cru->cru_clksel_con[31],
 428                              VIO0_PLL_MASK | VIO0_DIV_MASK,
 429                              VIO0_SEL_GPLL << VIO0_PLL_SHIFT |
 430                              (src_clk_div - 1) << VIO0_DIV_SHIFT);
 431                 break;
 432         case ACLK_VIO1:
 433                 rk_clrsetreg(&cru->cru_clksel_con[31],
 434                              VIO1_PLL_MASK | VIO1_DIV_MASK,
 435                              VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
 436                              (src_clk_div - 1) << VIO1_DIV_SHIFT);
 437                 break;
 438         case DCLK_LCDC:
 439                 if (pll_para_config(hz, &cpll_config))
 440                         return -1;
 441                 rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
 442
 443                 rk_clrsetreg(&cru->cru_clksel_con[27],
 444                              DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
 445                              DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT |
 446                              (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 447                 break;
 448         default:
 449                 printf("do not support this vop freq\n");
 450                 return -EINVAL;
 451         }
 452
 453         return hz;
 454 }
 455
 456 static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
 457 {
 458         u32 div, con, parent;
 459
 460         switch (clk_id) {
 461         case ACLK_VIO0:
 462                 con = readl(&cru->cru_clksel_con[31]);
 463                 div = con  & 0x1f;
 464                 parent = GPLL_HZ;
 465                 break;
 466         case ACLK_VIO1:
 467                 con = readl(&cru->cru_clksel_con[31]);
 468                 div = (con >> 8) & 0x1f;
 469                 parent = GPLL_HZ;
 470                 break;
 471         case DCLK_LCDC:
 472                 con = readl(&cru->cru_clksel_con[27]);
 473                 div = (con >> 8) & 0xfff;
 474                 parent = rkclk_pll_get_rate(cru, CLK_CODEC);
 475                 break;
 476         default:
 477                 return -ENOENT;
 478         }
 479         return DIV_TO_RATE(parent, div);
 480 }
 481
 482 static ulong rk3128_clk_get_rate(struct clk *clk)
 483 {
 484         struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
 485
 486         switch (clk->id) {
 487         case 0 ... 63:
 488                 return rkclk_pll_get_rate(priv->cru, clk->id);
 489         case PCLK_I2C0:
 490         case PCLK_I2C1:
 491         case PCLK_I2C2:
 492         case PCLK_I2C3:
 493         case PCLK_PWM:
 494                 return rk3128_peri_get_pclk(priv->cru, clk->id);
 495         case SCLK_SARADC:
 496                 return rk3128_saradc_get_clk(priv->cru);
 497         case DCLK_LCDC:
 498         case ACLK_VIO0:
 499         case ACLK_VIO1:
 500                 return rk3128_vop_get_rate(priv->cru, clk->id);
 501         default:
 502                 return -ENOENT;
 503         }
 504 }
 505
 506 static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
 507 {
 508         struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
 509         ulong new_rate, gclk_rate;
 510
 511         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 512         switch (clk->id) {
 513         case 0 ... 63:
 514                 return 0;
 515         case DCLK_LCDC:
 516         case ACLK_VIO0:
 517         case ACLK_VIO1:
 518                 new_rate = rk3128_vop_set_clk(priv->cru,
 519                                               clk->id, rate);
 520                 break;
 521         case HCLK_EMMC:
 522                 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
 523                                                 clk->id, rate);
 524                 break;
 525         case PCLK_I2C0:
 526         case PCLK_I2C1:
 527         case PCLK_I2C2:
 528         case PCLK_I2C3:
 529         case PCLK_PWM:
 530                 new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate);
 531                 break;
 532         case SCLK_SARADC:
 533                 new_rate = rk3128_saradc_set_clk(priv->cru, rate);
 534                 break;
 535         default:
 536                 return -ENOENT;
 537         }
 538
 539         return new_rate;
 540 }
 541
 542 static struct clk_ops rk3128_clk_ops = {
 543         .get_rate       = rk3128_clk_get_rate,
 544         .set_rate       = rk3128_clk_set_rate,
 545 };
 546
 547 static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
 548 {
 549         struct rk3128_clk_priv *priv = dev_get_priv(dev);
 550
 551         priv->cru = dev_read_addr_ptr(dev);
 552
 553         return 0;
 554 }
 555
 556 static int rk3128_clk_probe(struct udevice *dev)
 557 {
 558         struct rk3128_clk_priv *priv = dev_get_priv(dev);
 559
 560         rkclk_init(priv->cru);
 561
 562         return 0;
 563 }
 564
 565 static int rk3128_clk_bind(struct udevice *dev)
 566 {
 567         int ret;
 568         struct udevice *sys_child;
 569         struct sysreset_reg *priv;
 570
 571         /* The reset driver does not have a device node, so bind it here */
 572         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 573                                  &sys_child);
 574         if (ret) {
 575                 debug("Warning: No sysreset driver: ret=%d\n", ret);
 576         } else {
 577                 priv = malloc(sizeof(struct sysreset_reg));
 578                 priv->glb_srst_fst_value = offsetof(struct rk3128_cru,
 579                                                     cru_glb_srst_fst_value);
 580                 priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
 581                                                     cru_glb_srst_snd_value);
 582                 sys_child->priv = priv;
 583         }
 584
 585         return 0;
 586 }
 587
 588 static const struct udevice_id rk3128_clk_ids[] = {
 589         { .compatible = "rockchip,rk3128-cru" },
 590         { .compatible = "rockchip,rk3126-cru" },
 591         { }
 592 };
 593
 594 U_BOOT_DRIVER(rockchip_rk3128_cru) = {
 595         .name           = "clk_rk3128",
 596         .id             = UCLASS_CLK,
 597         .of_match       = rk3128_clk_ids,
 598         .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
 599         .ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
 600         .ops            = &rk3128_clk_ops,
 601         .bind           = rk3128_clk_bind,
 602         .probe          = rk3128_clk_probe,
 603 };