git.sur5r.net Git - u-boot/blob - drivers/cpu/bmips_cpu.c

   1 /*
   2  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   3  *
   4  * Derived from linux/arch/mips/bcm63xx/cpu.c:
   5  *      Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   6  *      Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <cpu.h>
  13 #include <dm.h>
  14 #include <errno.h>
  15 #include <asm/io.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #define REV_CHIPID_SHIFT                16
  20 #define REV_CHIPID_MASK                 (0xffff << REV_CHIPID_SHIFT)
  21 #define REV_LONG_CHIPID_SHIFT           12
  22 #define REV_LONG_CHIPID_MASK            (0xfffff << REV_LONG_CHIPID_SHIFT)
  23 #define REV_REVID_SHIFT                 0
  24 #define REV_REVID_MASK                  (0xff << REV_REVID_SHIFT)
  25
  26 #define REG_BCM6328_OTP                 0x62c
  27 #define BCM6328_TP1_DISABLED            BIT(9)
  28
  29 #define REG_BCM6328_MISC_STRAPBUS       0x1a40
  30 #define STRAPBUS_6328_FCVO_SHIFT        7
  31 #define STRAPBUS_6328_FCVO_MASK         (0x1f << STRAPBUS_6328_FCVO_SHIFT)
  32
  33 #define REG_BCM6348_PERF_MIPSPLLCFG     0x34
  34 #define MIPSPLLCFG_6348_M1CPU_SHIFT     6
  35 #define MIPSPLLCFG_6348_M1CPU_MASK      (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
  36 #define MIPSPLLCFG_6348_N2_SHIFT        15
  37 #define MIPSPLLCFG_6348_N2_MASK         (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
  38 #define MIPSPLLCFG_6348_N1_SHIFT        20
  39 #define MIPSPLLCFG_6348_N1_MASK         (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
  40
  41 #define REG_BCM6358_DDR_DMIPSPLLCFG     0x12b8
  42 #define DMIPSPLLCFG_6358_M1_SHIFT       0
  43 #define DMIPSPLLCFG_6358_M1_MASK        (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
  44 #define DMIPSPLLCFG_6358_N1_SHIFT       23
  45 #define DMIPSPLLCFG_6358_N1_MASK        (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
  46 #define DMIPSPLLCFG_6358_N2_SHIFT       29
  47 #define DMIPSPLLCFG_6358_N2_MASK        (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
  48
  49 #define REG_BCM63268_MISC_STRAPBUS      0x1814
  50 #define STRAPBUS_63268_FCVO_SHIFT       21
  51 #define STRAPBUS_63268_FCVO_MASK        (0xf << STRAPBUS_63268_FCVO_SHIFT)
  52
  53 struct bmips_cpu_priv;
  54
  55 struct bmips_cpu_hw {
  56         int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
  57         ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
  58         int (*get_cpu_count)(struct bmips_cpu_priv *);
  59 };
  60
  61 struct bmips_cpu_priv {
  62         void __iomem *regs;
  63         const struct bmips_cpu_hw *hw;
  64 };
  65
  66 /* Specific CPU Ops */
  67 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
  68                                 int size)
  69 {
  70         unsigned short cpu_id;
  71         unsigned char cpu_rev;
  72         u32 val;
  73
  74         val = readl_be(priv->regs);
  75         cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
  76         cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
  77
  78         snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
  79
  80         return 0;
  81 }
  82
  83 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
  84                                 int size)
  85 {
  86         unsigned int cpu_id;
  87         unsigned char cpu_rev;
  88         u32 val;
  89
  90         val = readl_be(priv->regs);
  91         cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
  92         cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
  93
  94         snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
  95
  96         return 0;
  97 }
  98
  99 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
 100 {
 101         return 333000000;
 102 }
 103
 104 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 105 {
 106         unsigned int mips_pll_fcvo;
 107
 108         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
 109         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
 110                         >> STRAPBUS_6328_FCVO_SHIFT;
 111
 112         switch (mips_pll_fcvo) {
 113         case 0x12:
 114         case 0x14:
 115         case 0x19:
 116                 return 160000000;
 117         case 0x1c:
 118                 return 192000000;
 119         case 0x13:
 120         case 0x15:
 121                 return 200000000;
 122         case 0x1a:
 123                 return 384000000;
 124         case 0x16:
 125                 return 400000000;
 126         default:
 127                 return 320000000;
 128         }
 129 }
 130
 131 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
 132 {
 133         unsigned int tmp, n1, n2, m1;
 134
 135         tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
 136         n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
 137         n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
 138         m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
 139
 140         return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
 141 }
 142
 143 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
 144 {
 145         unsigned int tmp, n1, n2, m1;
 146
 147         tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
 148         n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
 149         n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
 150         m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
 151
 152         return (16 * 1000000 * n1 * n2) / m1;
 153 }
 154
 155 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
 156 {
 157         unsigned int mips_pll_fcvo;
 158
 159         mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
 160         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
 161                         >> STRAPBUS_63268_FCVO_SHIFT;
 162
 163         switch (mips_pll_fcvo) {
 164         case 0x3:
 165         case 0xe:
 166                 return 320000000;
 167         case 0xa:
 168                 return 333000000;
 169         case 0x2:
 170         case 0xb:
 171         case 0xf:
 172                 return 400000000;
 173         default:
 174                 return 0;
 175         }
 176 }
 177
 178 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 179 {
 180         u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
 181
 182         if (val & BCM6328_TP1_DISABLED)
 183                 return 1;
 184         else
 185                 return 2;
 186 }
 187
 188 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
 189 {
 190         return 1;
 191 }
 192
 193 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 194 {
 195         return 2;
 196 }
 197
 198 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
 199         .get_cpu_desc = bmips_short_cpu_desc,
 200         .get_cpu_freq = bcm3380_get_cpu_freq,
 201         .get_cpu_count = bcm6358_get_cpu_count,
 202 };
 203
 204 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 205         .get_cpu_desc = bmips_long_cpu_desc,
 206         .get_cpu_freq = bcm6328_get_cpu_freq,
 207         .get_cpu_count = bcm6328_get_cpu_count,
 208 };
 209
 210 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
 211         .get_cpu_desc = bmips_short_cpu_desc,
 212         .get_cpu_freq = bcm6348_get_cpu_freq,
 213         .get_cpu_count = bcm6345_get_cpu_count,
 214 };
 215
 216 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
 217         .get_cpu_desc = bmips_short_cpu_desc,
 218         .get_cpu_freq = bcm6358_get_cpu_freq,
 219         .get_cpu_count = bcm6358_get_cpu_count,
 220 };
 221
 222 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
 223         .get_cpu_desc = bmips_long_cpu_desc,
 224         .get_cpu_freq = bcm63268_get_cpu_freq,
 225         .get_cpu_count = bcm6358_get_cpu_count,
 226 };
 227
 228 /* Generic CPU Ops */
 229 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
 230 {
 231         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 232         const struct bmips_cpu_hw *hw = priv->hw;
 233
 234         return hw->get_cpu_desc(priv, buf, size);
 235 }
 236
 237 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 238 {
 239         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 240         const struct bmips_cpu_hw *hw = priv->hw;
 241
 242         info->cpu_freq = hw->get_cpu_freq(priv);
 243         info->features = BIT(CPU_FEAT_L1_CACHE);
 244         info->features |= BIT(CPU_FEAT_MMU);
 245         info->features |= BIT(CPU_FEAT_DEVICE_ID);
 246
 247         return 0;
 248 }
 249
 250 static int bmips_cpu_get_count(struct udevice *dev)
 251 {
 252         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 253         const struct bmips_cpu_hw *hw = priv->hw;
 254
 255         return hw->get_cpu_count(priv);
 256 }
 257
 258 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
 259 {
 260         snprintf(buf, size, "Broadcom");
 261
 262         return 0;
 263 }
 264
 265 static const struct cpu_ops bmips_cpu_ops = {
 266         .get_desc = bmips_cpu_get_desc,
 267         .get_info = bmips_cpu_get_info,
 268         .get_count = bmips_cpu_get_count,
 269         .get_vendor = bmips_cpu_get_vendor,
 270 };
 271
 272 /* BMIPS CPU driver */
 273 int bmips_cpu_bind(struct udevice *dev)
 274 {
 275         struct cpu_platdata *plat = dev_get_parent_platdata(dev);
 276
 277         plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 278                 "reg", -1);
 279         plat->device_id = read_c0_prid();
 280
 281         return 0;
 282 }
 283
 284 int bmips_cpu_probe(struct udevice *dev)
 285 {
 286         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 287         const struct bmips_cpu_hw *hw =
 288                 (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
 289         fdt_addr_t addr;
 290         fdt_size_t size;
 291
 292         addr = dev_get_addr_size_index(dev_get_parent(dev), 0, &size);
 293         if (addr == FDT_ADDR_T_NONE)
 294                 return -EINVAL;
 295
 296         priv->regs = ioremap(addr, size);
 297         priv->hw = hw;
 298
 299         return 0;
 300 }
 301
 302 static const struct udevice_id bmips_cpu_ids[] = {
 303         {
 304                 .compatible = "brcm,bcm3380-cpu",
 305                 .data = (ulong)&bmips_cpu_bcm3380,
 306         }, {
 307                 .compatible = "brcm,bcm6328-cpu",
 308                 .data = (ulong)&bmips_cpu_bcm6328,
 309         }, {
 310                 .compatible = "brcm,bcm6348-cpu",
 311                 .data = (ulong)&bmips_cpu_bcm6348,
 312         }, {
 313                 .compatible = "brcm,bcm6358-cpu",
 314                 .data = (ulong)&bmips_cpu_bcm6358,
 315         }, {
 316                 .compatible = "brcm,bcm63268-cpu",
 317                 .data = (ulong)&bmips_cpu_bcm63268,
 318         },
 319         { /* sentinel */ }
 320 };
 321
 322 U_BOOT_DRIVER(bmips_cpu_drv) = {
 323         .name = "bmips_cpu",
 324         .id = UCLASS_CPU,
 325         .of_match = bmips_cpu_ids,
 326         .bind = bmips_cpu_bind,
 327         .probe = bmips_cpu_probe,
 328         .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
 329         .ops = &bmips_cpu_ops,
 330         .flags = DM_FLAG_PRE_RELOC,
 331 };
 332
 333 #ifdef CONFIG_DISPLAY_CPUINFO
 334 int print_cpuinfo(void)
 335 {
 336         struct cpu_info cpu;
 337         struct udevice *dev;
 338         int err;
 339         char desc[100];
 340
 341         err = uclass_get_device(UCLASS_CPU, 0, &dev);
 342         if (err)
 343                 return 0;
 344
 345         err = cpu_get_info(dev, &cpu);
 346         if (err)
 347                 return 0;
 348
 349         err = cpu_get_desc(dev, desc, sizeof(desc));
 350         if (err)
 351                 return 0;
 352
 353         printf("Chip ID: %s, MIPS: ", desc);
 354         print_freq(cpu.cpu_freq, "\n");
 355
 356         return 0;
 357 }
 358 #endif