git.sur5r.net Git - u-boot/blob - drivers/i2c/imx_lpi2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductors, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <imx_lpi2c.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <dm.h>
  14 #include <fdtdec.h>
  15 #include <i2c.h>
  16
  17 #define LPI2C_FIFO_SIZE 4
  18 #define LPI2C_NACK_TOUT_MS 1
  19 #define LPI2C_TIMEOUT_MS 100
  20
  21 /* Weak linked function for overridden by some SoC power function */
  22 int __weak init_i2c_power(unsigned i2c_num)
  23 {
  24         return 0;
  25 }
  26
  27 static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
  28 {
  29         lpi2c_status_t result = LPI2C_SUCESS;
  30         u32 status;
  31
  32         status = readl(&regs->msr);
  33
  34         if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
  35                 result = LPI2C_BUSY;
  36
  37         return result;
  38 }
  39
  40 static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
  41 {
  42         lpi2c_status_t result = LPI2C_SUCESS;
  43         u32 val, status;
  44
  45         status = readl(&regs->msr);
  46         /* errors to check for */
  47         status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
  48                 LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;
  49
  50         if (status) {
  51                 if (status & LPI2C_MSR_PLTF_MASK)
  52                         result = LPI2C_PIN_LOW_TIMEOUT_ERR;
  53                 else if (status & LPI2C_MSR_ALF_MASK)
  54                         result = LPI2C_ARB_LOST_ERR;
  55                 else if (status & LPI2C_MSR_NDF_MASK)
  56                         result = LPI2C_NAK_ERR;
  57                 else if (status & LPI2C_MSR_FEF_MASK)
  58                         result = LPI2C_FIFO_ERR;
  59
  60                 /* clear status flags */
  61                 writel(0x7f00, &regs->msr);
  62                 /* reset fifos */
  63                 val = readl(&regs->mcr);
  64                 val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
  65                 writel(val, &regs->mcr);
  66         }
  67
  68         return result;
  69 }
  70
  71 static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
  72 {
  73         lpi2c_status_t result = LPI2C_SUCESS;
  74         u32 txcount = 0;
  75         ulong start_time = get_timer(0);
  76
  77         do {
  78                 txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
  79                 txcount = LPI2C_FIFO_SIZE - txcount;
  80                 result = imx_lpci2c_check_clear_error(regs);
  81                 if (result) {
  82                         debug("i2c: wait for tx ready: result 0x%x\n", result);
  83                         return result;
  84                 }
  85                 if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
  86                         debug("i2c: wait for tx ready: timeout\n");
  87                         return -1;
  88                 }
  89         } while (!txcount);
  90
  91         return result;
  92 }
  93
  94 static int bus_i2c_send(struct imx_lpi2c_reg *regs, u8 *txbuf, int len)
  95 {
  96         lpi2c_status_t result = LPI2C_SUCESS;
  97
  98         /* empty tx */
  99         if (!len)
 100                 return result;
 101
 102         while (len--) {
 103                 result = bus_i2c_wait_for_tx_ready(regs);
 104                 if (result) {
 105                         debug("i2c: send wait fot tx ready: %d\n", result);
 106                         return result;
 107                 }
 108                 writel(*txbuf++, &regs->mtdr);
 109         }
 110
 111         return result;
 112 }
 113
 114 static int bus_i2c_receive(struct imx_lpi2c_reg *regs, u8 *rxbuf, int len)
 115 {
 116         lpi2c_status_t result = LPI2C_SUCESS;
 117         u32 val;
 118         ulong start_time = get_timer(0);
 119
 120         /* empty read */
 121         if (!len)
 122                 return result;
 123
 124         result = bus_i2c_wait_for_tx_ready(regs);
 125         if (result) {
 126                 debug("i2c: receive wait fot tx ready: %d\n", result);
 127                 return result;
 128         }
 129
 130         /* clear all status flags */
 131         writel(0x7f00, &regs->msr);
 132         /* send receive command */
 133         val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1);
 134         writel(val, &regs->mtdr);
 135
 136         while (len--) {
 137                 do {
 138                         result = imx_lpci2c_check_clear_error(regs);
 139                         if (result) {
 140                                 debug("i2c: receive check clear error: %d\n",
 141                                       result);
 142                                 return result;
 143                         }
 144                         if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
 145                                 debug("i2c: receive mrdr: timeout\n");
 146                                 return -1;
 147                         }
 148                         val = readl(&regs->mrdr);
 149                 } while (val & LPI2C_MRDR_RXEMPTY_MASK);
 150                 *rxbuf++ = LPI2C_MRDR_DATA(val);
 151         }
 152
 153         return result;
 154 }
 155
 156 static int bus_i2c_start(struct imx_lpi2c_reg *regs, u8 addr, u8 dir)
 157 {
 158         lpi2c_status_t result;
 159         u32 val;
 160
 161         result = imx_lpci2c_check_busy_bus(regs);
 162         if (result) {
 163                 debug("i2c: start check busy bus: 0x%x\n", result);
 164                 return result;
 165         }
 166         /* clear all status flags */
 167         writel(0x7f00, &regs->msr);
 168         /* turn off auto-stop condition */
 169         val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
 170         writel(val, &regs->mcfgr1);
 171         /* wait tx fifo ready */
 172         result = bus_i2c_wait_for_tx_ready(regs);
 173         if (result) {
 174                 debug("i2c: start wait for tx ready: 0x%x\n", result);
 175                 return result;
 176         }
 177         /* issue start command */
 178         val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
 179         writel(val, &regs->mtdr);
 180
 181         return result;
 182 }
 183
 184 static int bus_i2c_stop(struct imx_lpi2c_reg *regs)
 185 {
 186         lpi2c_status_t result;
 187         u32 status;
 188         ulong start_time;
 189
 190         result = bus_i2c_wait_for_tx_ready(regs);
 191         if (result) {
 192                 debug("i2c: stop wait for tx ready: 0x%x\n", result);
 193                 return result;
 194         }
 195
 196         /* send stop command */
 197         writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);
 198
 199         start_time = get_timer(0);
 200         while (1) {
 201                 status = readl(&regs->msr);
 202                 result = imx_lpci2c_check_clear_error(regs);
 203                 /* stop detect flag */
 204                 if (status & LPI2C_MSR_SDF_MASK) {
 205                         /* clear stop flag */
 206                         status &= LPI2C_MSR_SDF_MASK;
 207                         writel(status, &regs->msr);
 208                         break;
 209                 }
 210
 211                 if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
 212                         debug("stop timeout\n");
 213                         return -ETIMEDOUT;
 214                 }
 215         }
 216
 217         return result;
 218 }
 219
 220 static int bus_i2c_read(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
 221 {
 222         lpi2c_status_t result;
 223
 224         result = bus_i2c_start(regs, chip, 1);
 225         if (result)
 226                 return result;
 227         result = bus_i2c_receive(regs, buf, len);
 228         if (result)
 229                 return result;
 230         result = bus_i2c_stop(regs);
 231         if (result)
 232                 return result;
 233
 234         return result;
 235 }
 236
 237 static int bus_i2c_write(struct imx_lpi2c_reg *regs, u32 chip, u8 *buf, int len)
 238 {
 239         lpi2c_status_t result;
 240
 241         result = bus_i2c_start(regs, chip, 0);
 242         if (result)
 243                 return result;
 244         result = bus_i2c_send(regs, buf, len);
 245         if (result)
 246                 return result;
 247         result = bus_i2c_stop(regs);
 248         if (result)
 249                 return result;
 250
 251         return result;
 252 }
 253
 254
 255 static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
 256 {
 257         struct imx_lpi2c_reg *regs;
 258         u32 val;
 259         u32 preescale = 0, best_pre = 0, clkhi = 0;
 260         u32 best_clkhi = 0, abs_error = 0, rate;
 261         u32 error = 0xffffffff;
 262         u32 clock_rate;
 263         bool mode;
 264         int i;
 265
 266         regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 267         clock_rate = imx_get_i2cclk(bus->seq);
 268         if (!clock_rate)
 269                 return -EPERM;
 270
 271         mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
 272         /* disable master mode */
 273         val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
 274         writel(val | LPI2C_MCR_MEN(0), &regs->mcr);
 275
 276         for (preescale = 1; (preescale <= 128) &&
 277                 (error != 0); preescale = 2 * preescale) {
 278                 for (clkhi = 1; clkhi < 32; clkhi++) {
 279                         if (clkhi == 1)
 280                                 rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
 281                         else
 282                                 rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
 283
 284                         abs_error = speed > rate ? speed - rate : rate - speed;
 285
 286                         if (abs_error < error) {
 287                                 best_pre = preescale;
 288                                 best_clkhi = clkhi;
 289                                 error = abs_error;
 290                                 if (abs_error == 0)
 291                                         break;
 292                         }
 293                 }
 294         }
 295
 296         /* Standard, fast, fast mode plus and ultra-fast transfers. */
 297         val = LPI2C_MCCR0_CLKHI(best_clkhi);
 298         if (best_clkhi < 2)
 299                 val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
 300         else
 301                 val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
 302                         LPI2C_MCCR0_DATAVD(best_clkhi / 2);
 303         writel(val, &regs->mccr0);
 304
 305         for (i = 0; i < 8; i++) {
 306                 if (best_pre == (1 << i)) {
 307                         best_pre = i;
 308                         break;
 309                 }
 310         }
 311
 312         val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
 313         writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);
 314
 315         if (mode) {
 316                 val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
 317                 writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
 318         }
 319
 320         return 0;
 321 }
 322
 323 static int bus_i2c_init(struct udevice *bus, int speed)
 324 {
 325         struct imx_lpi2c_reg *regs;
 326         u32 val;
 327         int ret;
 328
 329         regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 330         /* reset peripheral */
 331         writel(LPI2C_MCR_RST_MASK, &regs->mcr);
 332         writel(0x0, &regs->mcr);
 333         /* Disable Dozen mode */
 334         writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
 335         /* host request disable, active high, external pin */
 336         val = readl(&regs->mcfgr0);
 337         val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
 338                                 LPI2C_MCFGR0_HRSEL_MASK));
 339         val |= LPI2C_MCFGR0_HRPOL(0x1);
 340         writel(val, &regs->mcfgr0);
 341         /* pincfg and ignore ack */
 342         val = readl(&regs->mcfgr1);
 343         val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
 344         val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
 345         val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
 346         writel(val, &regs->mcfgr1);
 347
 348         ret = bus_i2c_set_bus_speed(bus, speed);
 349
 350         /* enable lpi2c in master mode */
 351         val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
 352         writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
 353
 354         debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed);
 355
 356         return ret;
 357 }
 358
 359 static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
 360                                 u32 chip_flags)
 361 {
 362         struct imx_lpi2c_reg *regs;
 363         lpi2c_status_t result;
 364
 365         regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 366         result = bus_i2c_start(regs, chip, 0);
 367         if (result) {
 368                 bus_i2c_stop(regs);
 369                 bus_i2c_init(bus, 100000);
 370                 return result;
 371         }
 372
 373         result = bus_i2c_stop(regs);
 374         if (result)
 375                 bus_i2c_init(bus, 100000);
 376
 377         return result;
 378 }
 379
 380 static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 381 {
 382         struct imx_lpi2c_reg *regs;
 383         int ret = 0;
 384
 385         regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
 386         for (; nmsgs > 0; nmsgs--, msg++) {
 387                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 388                 if (msg->flags & I2C_M_RD)
 389                         ret = bus_i2c_read(regs, msg->addr, msg->buf, msg->len);
 390                 else {
 391                         ret = bus_i2c_write(regs, msg->addr, msg->buf,
 392                                             msg->len);
 393                         if (ret)
 394                                 break;
 395                 }
 396         }
 397
 398         if (ret)
 399                 debug("i2c_write: error sending\n");
 400
 401         return ret;
 402 }
 403
 404 static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 405 {
 406         return bus_i2c_set_bus_speed(bus, speed);
 407 }
 408
 409 static int imx_lpi2c_probe(struct udevice *bus)
 410 {
 411         struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
 412         fdt_addr_t addr;
 413         int ret;
 414
 415         i2c_bus->driver_data = dev_get_driver_data(bus);
 416
 417         addr = devfdt_get_addr(bus);
 418         if (addr == FDT_ADDR_T_NONE)
 419                 return -EINVAL;
 420
 421         i2c_bus->base = addr;
 422         i2c_bus->index = bus->seq;
 423         i2c_bus->bus = bus;
 424
 425         /* power up i2c resource */
 426         ret = init_i2c_power(bus->seq);
 427         if (ret) {
 428                 debug("init_i2c_power err = %d\n", ret);
 429                 return ret;
 430         }
 431
 432         /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
 433         ret = enable_i2c_clk(1, bus->seq);
 434         if (ret < 0)
 435                 return ret;
 436
 437         ret = bus_i2c_init(bus, 100000);
 438         if (ret < 0)
 439                 return ret;
 440
 441         debug("i2c : controller bus %d at %lu , speed %d: ",
 442               bus->seq, i2c_bus->base,
 443               i2c_bus->speed);
 444
 445         return 0;
 446 }
 447
 448 static const struct dm_i2c_ops imx_lpi2c_ops = {
 449         .xfer           = imx_lpi2c_xfer,
 450         .probe_chip     = imx_lpi2c_probe_chip,
 451         .set_bus_speed  = imx_lpi2c_set_bus_speed,
 452 };
 453
 454 static const struct udevice_id imx_lpi2c_ids[] = {
 455         { .compatible = "fsl,imx7ulp-lpi2c", },
 456         { .compatible = "fsl,imx8qm-lpi2c", },
 457         {}
 458 };
 459
 460 U_BOOT_DRIVER(imx_lpi2c) = {
 461         .name = "imx_lpi2c",
 462         .id = UCLASS_I2C,
 463         .of_match = imx_lpi2c_ids,
 464         .probe = imx_lpi2c_probe,
 465         .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus),
 466         .ops = &imx_lpi2c_ops,
 467 };