git.sur5r.net Git - u-boot/blob - drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #ifdef CONFIG_OMAP54XX
  38 #include <asm/arch/mux_dra7xx.h>
  39 #include <asm/arch/dra7xx_iodelay.h>
  40 #endif
  41 #if !defined(CONFIG_SOC_KEYSTONE)
  42 #include <asm/gpio.h>
  43 #include <asm/arch/sys_proto.h>
  44 #endif
  45 #ifdef CONFIG_MMC_OMAP36XX_PINS
  46 #include <asm/arch/mux.h>
  47 #endif
  48 #include <dm.h>
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  53 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  54         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  55 #define OMAP_HSMMC_USE_GPIO
  56 #else
  57 #undef OMAP_HSMMC_USE_GPIO
  58 #endif
  59
  60 /* common definitions for all OMAPs */
  61 #define SYSCTL_SRC      (1 << 25)
  62 #define SYSCTL_SRD      (1 << 26)
  63
  64 #ifdef CONFIG_IODELAY_RECALIBRATION
  65 struct omap_hsmmc_pinctrl_state {
  66         struct pad_conf_entry *padconf;
  67         int npads;
  68         struct iodelay_cfg_entry *iodelay;
  69         int niodelays;
  70 };
  71 #endif
  72
  73 struct omap_hsmmc_data {
  74         struct hsmmc *base_addr;
  75 #if !CONFIG_IS_ENABLED(DM_MMC)
  76         struct mmc_config cfg;
  77 #endif
  78         uint bus_width;
  79         uint clock;
  80 #ifdef OMAP_HSMMC_USE_GPIO
  81 #if CONFIG_IS_ENABLED(DM_MMC)
  82         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  83         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  84         bool cd_inverted;
  85 #else
  86         int cd_gpio;
  87         int wp_gpio;
  88 #endif
  89 #endif
  90 #if CONFIG_IS_ENABLED(DM_MMC)
  91         uint iov;
  92         enum bus_mode mode;
  93 #endif
  94         u8 controller_flags;
  95 #ifndef CONFIG_OMAP34XX
  96         struct omap_hsmmc_adma_desc *adma_desc_table;
  97         uint desc_slot;
  98 #endif
  99         const char *hw_rev;
 100 #ifdef CONFIG_IODELAY_RECALIBRATION
 101         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 102         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 103         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 104         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 105         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 106         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 107         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 110 #endif
 111 };
 112
 113 struct omap_mmc_of_data {
 114         u8 controller_flags;
 115 };
 116
 117 #ifndef CONFIG_OMAP34XX
 118 struct omap_hsmmc_adma_desc {
 119         u8 attr;
 120         u8 reserved;
 121         u16 len;
 122         u32 addr;
 123 };
 124
 125 #define ADMA_MAX_LEN    63488
 126
 127 /* Decriptor table defines */
 128 #define ADMA_DESC_ATTR_VALID            BIT(0)
 129 #define ADMA_DESC_ATTR_END              BIT(1)
 130 #define ADMA_DESC_ATTR_INT              BIT(2)
 131 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 132 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 133
 134 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 135 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 136 #endif
 137
 138 /* If we fail after 1 second wait, something is really bad */
 139 #define MAX_RETRY_MS    1000
 140 #define MMC_TIMEOUT_MS  20
 141
 142 /* DMA transfers can take a long time if a lot a data is transferred.
 143  * The timeout must take in account the amount of data. Let's assume
 144  * that the time will never exceed 333 ms per MB (in other word we assume
 145  * that the bandwidth is always above 3MB/s).
 146  */
 147 #define DMA_TIMEOUT_PER_MB      333
 148 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 149 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 150 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 151 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 152
 153 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 154 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 155                         unsigned int siz);
 156 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 157 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 158 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 159
 160 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 161 {
 162 #if CONFIG_IS_ENABLED(DM_MMC)
 163         return dev_get_priv(mmc->dev);
 164 #else
 165         return (struct omap_hsmmc_data *)mmc->priv;
 166 #endif
 167 }
 168 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 169 {
 170 #if CONFIG_IS_ENABLED(DM_MMC)
 171         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 172         return &plat->cfg;
 173 #else
 174         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 175 #endif
 176 }
 177
 178 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 179 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 180 {
 181         int ret;
 182
 183 #ifndef CONFIG_DM_GPIO
 184         if (!gpio_is_valid(gpio))
 185                 return -1;
 186 #endif
 187         ret = gpio_request(gpio, label);
 188         if (ret)
 189                 return ret;
 190
 191         ret = gpio_direction_input(gpio);
 192         if (ret)
 193                 return ret;
 194
 195         return gpio;
 196 }
 197 #endif
 198
 199 static unsigned char mmc_board_init(struct mmc *mmc)
 200 {
 201 #if defined(CONFIG_OMAP34XX)
 202         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 203         t2_t *t2_base = (t2_t *)T2_BASE;
 204         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 205         u32 pbias_lite;
 206 #ifdef CONFIG_MMC_OMAP36XX_PINS
 207         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 208 #endif
 209
 210         pbias_lite = readl(&t2_base->pbias_lite);
 211         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 212 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 213         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 214         pbias_lite &= ~PBIASLITEVMODE0;
 215 #endif
 216 #ifdef CONFIG_MMC_OMAP36XX_PINS
 217         if (get_cpu_family() == CPU_OMAP36XX) {
 218                 /* Disable extended drain IO before changing PBIAS */
 219                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 220                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 221         }
 222 #endif
 223         writel(pbias_lite, &t2_base->pbias_lite);
 224
 225         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 226                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 227                 &t2_base->pbias_lite);
 228
 229 #ifdef CONFIG_MMC_OMAP36XX_PINS
 230         if (get_cpu_family() == CPU_OMAP36XX)
 231                 /* Enable extended drain IO after changing PBIAS */
 232                 writel(wkup_ctrl |
 233                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 234                                 OMAP34XX_CTRL_WKUP_CTRL);
 235 #endif
 236         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 237                 &t2_base->devconf0);
 238
 239         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 240                 &t2_base->devconf1);
 241
 242         /* Change from default of 52MHz to 26MHz if necessary */
 243         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 244                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 245                         &t2_base->ctl_prog_io1);
 246
 247         writel(readl(&prcm_base->fclken1_core) |
 248                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 249                 &prcm_base->fclken1_core);
 250
 251         writel(readl(&prcm_base->iclken1_core) |
 252                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 253                 &prcm_base->iclken1_core);
 254 #endif
 255
 256 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 257         /* PBIAS config needed for MMC1 only */
 258         if (mmc_get_blk_desc(mmc)->devnum == 0)
 259                 vmmc_pbias_config(LDO_VOLT_3V0);
 260 #endif
 261
 262         return 0;
 263 }
 264
 265 void mmc_init_stream(struct hsmmc *mmc_base)
 266 {
 267         ulong start;
 268
 269         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 270
 271         writel(MMC_CMD0, &mmc_base->cmd);
 272         start = get_timer(0);
 273         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 274                 if (get_timer(0) - start > MAX_RETRY_MS) {
 275                         printf("%s: timedout waiting for cc!\n", __func__);
 276                         return;
 277                 }
 278         }
 279         writel(CC_MASK, &mmc_base->stat)
 280                 ;
 281         writel(MMC_CMD0, &mmc_base->cmd)
 282                 ;
 283         start = get_timer(0);
 284         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 285                 if (get_timer(0) - start > MAX_RETRY_MS) {
 286                         printf("%s: timedout waiting for cc2!\n", __func__);
 287                         return;
 288                 }
 289         }
 290         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 291 }
 292
 293 #if CONFIG_IS_ENABLED(DM_MMC)
 294 #ifdef CONFIG_IODELAY_RECALIBRATION
 295 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 296 {
 297         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 298         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 299
 300         switch (priv->mode) {
 301         case MMC_HS_200:
 302                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 303                 break;
 304         case UHS_SDR104:
 305                 pinctrl_state = priv->sdr104_pinctrl_state;
 306                 break;
 307         case UHS_SDR50:
 308                 pinctrl_state = priv->sdr50_pinctrl_state;
 309                 break;
 310         case UHS_DDR50:
 311                 pinctrl_state = priv->ddr50_pinctrl_state;
 312                 break;
 313         case UHS_SDR25:
 314                 pinctrl_state = priv->sdr25_pinctrl_state;
 315                 break;
 316         case UHS_SDR12:
 317                 pinctrl_state = priv->sdr12_pinctrl_state;
 318                 break;
 319         case SD_HS:
 320         case MMC_HS:
 321         case MMC_HS_52:
 322                 pinctrl_state = priv->hs_pinctrl_state;
 323                 break;
 324         case MMC_DDR_52:
 325                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 326         default:
 327                 pinctrl_state = priv->default_pinctrl_state;
 328                 break;
 329         }
 330
 331         if (!pinctrl_state)
 332                 pinctrl_state = priv->default_pinctrl_state;
 333
 334         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 335                 if (pinctrl_state->iodelay)
 336                         late_recalibrate_iodelay(pinctrl_state->padconf,
 337                                                  pinctrl_state->npads,
 338                                                  pinctrl_state->iodelay,
 339                                                  pinctrl_state->niodelays);
 340                 else
 341                         do_set_mux32((*ctrl)->control_padconf_core_base,
 342                                      pinctrl_state->padconf,
 343                                      pinctrl_state->npads);
 344         }
 345 }
 346 #endif
 347 static void omap_hsmmc_set_timing(struct mmc *mmc)
 348 {
 349         u32 val;
 350         struct hsmmc *mmc_base;
 351         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 352
 353         mmc_base = priv->base_addr;
 354
 355         omap_hsmmc_stop_clock(mmc_base);
 356         val = readl(&mmc_base->ac12);
 357         val &= ~AC12_UHSMC_MASK;
 358         priv->mode = mmc->selected_mode;
 359
 360         if (mmc_is_mode_ddr(priv->mode))
 361                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 362         else
 363                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 364
 365         switch (priv->mode) {
 366         case MMC_HS_200:
 367         case UHS_SDR104:
 368                 val |= AC12_UHSMC_SDR104;
 369                 break;
 370         case UHS_SDR50:
 371                 val |= AC12_UHSMC_SDR50;
 372                 break;
 373         case MMC_DDR_52:
 374         case UHS_DDR50:
 375                 val |= AC12_UHSMC_DDR50;
 376                 break;
 377         case SD_HS:
 378         case MMC_HS_52:
 379         case UHS_SDR25:
 380                 val |= AC12_UHSMC_SDR25;
 381                 break;
 382         case MMC_LEGACY:
 383         case MMC_HS:
 384         case SD_LEGACY:
 385         case UHS_SDR12:
 386                 val |= AC12_UHSMC_SDR12;
 387                 break;
 388         default:
 389                 val |= AC12_UHSMC_RES;
 390                 break;
 391         }
 392         writel(val, &mmc_base->ac12);
 393
 394 #ifdef CONFIG_IODELAY_RECALIBRATION
 395         omap_hsmmc_io_recalibrate(mmc);
 396 #endif
 397         omap_hsmmc_start_clock(mmc_base);
 398 }
 399
 400 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
 401 {
 402         struct hsmmc *mmc_base;
 403         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 404         u32 val;
 405
 406         mmc_base = priv->base_addr;
 407
 408         val = readl(&mmc_base->hctl) & ~SDVS_MASK;
 409
 410         switch (priv->iov) {
 411         case IOV_3V3:
 412                 val |= SDVS_3V3;
 413                 break;
 414         case IOV_3V0:
 415                 val |= SDVS_3V0;
 416                 break;
 417         case IOV_1V8:
 418                 val |= SDVS_1V8;
 419                 break;
 420         }
 421
 422         writel(val, &mmc_base->hctl);
 423 }
 424
 425 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
 426 {
 427         struct hsmmc *mmc_base;
 428         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 429         u32 val;
 430
 431         mmc_base = priv->base_addr;
 432         val = readl(&mmc_base->capa);
 433
 434         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 435                 val |= (VS30_3V0SUP | VS18_1V8SUP);
 436                 priv->iov = IOV_3V0;
 437         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 438                 val |= VS30_3V0SUP;
 439                 val &= ~VS18_1V8SUP;
 440                 priv->iov = IOV_3V0;
 441         } else {
 442                 val |= VS18_1V8SUP;
 443                 val &= ~VS30_3V0SUP;
 444                 priv->iov = IOV_1V8;
 445         }
 446
 447         writel(val, &mmc_base->capa);
 448 }
 449
 450 #ifdef MMC_SUPPORTS_TUNING
 451 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 452 {
 453         struct hsmmc *mmc_base;
 454         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 455         u32 val;
 456
 457         mmc_base = priv->base_addr;
 458         val = readl(&mmc_base->ac12);
 459         val &= ~(AC12_SCLK_SEL);
 460         writel(val, &mmc_base->ac12);
 461
 462         val = readl(&mmc_base->dll);
 463         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 464         writel(val, &mmc_base->dll);
 465 }
 466
 467 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 468 {
 469         int i;
 470         struct hsmmc *mmc_base;
 471         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 472         u32 val;
 473
 474         mmc_base = priv->base_addr;
 475         val = readl(&mmc_base->dll);
 476         val |= DLL_FORCE_VALUE;
 477         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 478         val |= (count << DLL_FORCE_SR_C_SHIFT);
 479         writel(val, &mmc_base->dll);
 480
 481         val |= DLL_CALIB;
 482         writel(val, &mmc_base->dll);
 483         for (i = 0; i < 1000; i++) {
 484                 if (readl(&mmc_base->dll) & DLL_CALIB)
 485                         break;
 486         }
 487         val &= ~DLL_CALIB;
 488         writel(val, &mmc_base->dll);
 489 }
 490
 491 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 492 {
 493         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 494         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 495         struct mmc *mmc = upriv->mmc;
 496         struct hsmmc *mmc_base;
 497         u32 val;
 498         u8 cur_match, prev_match = 0;
 499         int ret;
 500         u32 phase_delay = 0;
 501         u32 start_window = 0, max_window = 0;
 502         u32 length = 0, max_len = 0;
 503
 504         mmc_base = priv->base_addr;
 505         val = readl(&mmc_base->capa2);
 506
 507         /* clock tuning is not needed for upto 52MHz */
 508         if (!((mmc->selected_mode == MMC_HS_200) ||
 509               (mmc->selected_mode == UHS_SDR104) ||
 510               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 511                 return 0;
 512
 513         val = readl(&mmc_base->dll);
 514         val |= DLL_SWT;
 515         writel(val, &mmc_base->dll);
 516         while (phase_delay <= MAX_PHASE_DELAY) {
 517                 omap_hsmmc_set_dll(mmc, phase_delay);
 518
 519                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 520
 521                 if (cur_match) {
 522                         if (prev_match) {
 523                                 length++;
 524                         } else {
 525                                 start_window = phase_delay;
 526                                 length = 1;
 527                         }
 528                 }
 529
 530                 if (length > max_len) {
 531                         max_window = start_window;
 532                         max_len = length;
 533                 }
 534
 535                 prev_match = cur_match;
 536                 phase_delay += 4;
 537         }
 538
 539         if (!max_len) {
 540                 ret = -EIO;
 541                 goto tuning_error;
 542         }
 543
 544         val = readl(&mmc_base->ac12);
 545         if (!(val & AC12_SCLK_SEL)) {
 546                 ret = -EIO;
 547                 goto tuning_error;
 548         }
 549
 550         phase_delay = max_window + 4 * ((3 * max_len) >> 2);
 551         omap_hsmmc_set_dll(mmc, phase_delay);
 552
 553         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 554         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 555
 556         return 0;
 557
 558 tuning_error:
 559
 560         omap_hsmmc_disable_tuning(mmc);
 561         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 562         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 563
 564         return ret;
 565 }
 566 #endif
 567 #endif
 568
 569 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 570 {
 571         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 572         struct hsmmc *mmc_base = priv->base_addr;
 573         u32 irq_mask = INT_EN_MASK;
 574
 575         /*
 576          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 577          * tuning procedure and DCRC should be disabled. But see occurences
 578          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 579          * interrupts occur along with BRR, so the data is actually in the
 580          * buffer. It has to be debugged why these interrutps occur
 581          */
 582         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 583                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 584
 585         writel(irq_mask, &mmc_base->ie);
 586 }
 587
 588 static int omap_hsmmc_init_setup(struct mmc *mmc)
 589 {
 590         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 591         struct hsmmc *mmc_base;
 592         unsigned int reg_val;
 593         unsigned int dsor;
 594         ulong start;
 595
 596         mmc_base = priv->base_addr;
 597         mmc_board_init(mmc);
 598
 599         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 600                 &mmc_base->sysconfig);
 601         start = get_timer(0);
 602         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 603                 if (get_timer(0) - start > MAX_RETRY_MS) {
 604                         printf("%s: timedout waiting for cc2!\n", __func__);
 605                         return -ETIMEDOUT;
 606                 }
 607         }
 608         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 609         start = get_timer(0);
 610         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 611                 if (get_timer(0) - start > MAX_RETRY_MS) {
 612                         printf("%s: timedout waiting for softresetall!\n",
 613                                 __func__);
 614                         return -ETIMEDOUT;
 615                 }
 616         }
 617 #ifndef CONFIG_OMAP34XX
 618         reg_val = readl(&mmc_base->hl_hwinfo);
 619         if (reg_val & MADMA_EN)
 620                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 621 #endif
 622
 623 #if CONFIG_IS_ENABLED(DM_MMC)
 624         omap_hsmmc_set_capabilities(mmc);
 625         omap_hsmmc_conf_bus_power(mmc);
 626 #else
 627         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 628         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 629                 &mmc_base->capa);
 630 #endif
 631
 632         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 633
 634         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 635                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 636                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 637
 638         dsor = 240;
 639         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 640                 (ICE_STOP | DTO_15THDTO));
 641         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 642                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 643         start = get_timer(0);
 644         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 645                 if (get_timer(0) - start > MAX_RETRY_MS) {
 646                         printf("%s: timedout waiting for ics!\n", __func__);
 647                         return -ETIMEDOUT;
 648                 }
 649         }
 650         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 651
 652         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 653
 654         mmc_enable_irq(mmc, NULL);
 655         mmc_init_stream(mmc_base);
 656
 657         return 0;
 658 }
 659
 660 /*
 661  * MMC controller internal finite state machine reset
 662  *
 663  * Used to reset command or data internal state machines, using respectively
 664  * SRC or SRD bit of SYSCTL register
 665  */
 666 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 667 {
 668         ulong start;
 669
 670         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 671
 672         /*
 673          * CMD(DAT) lines reset procedures are slightly different
 674          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 675          * According to OMAP3 TRM:
 676          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 677          * returns to 0x0.
 678          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 679          * procedure steps must be as follows:
 680          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 681          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 682          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 683          * 3. Wait until the SRC (SRD) bit returns to 0x0
 684          *    (reset procedure is completed).
 685          */
 686 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 687         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 688         if (!(readl(&mmc_base->sysctl) & bit)) {
 689                 start = get_timer(0);
 690                 while (!(readl(&mmc_base->sysctl) & bit)) {
 691                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 692                                 return;
 693                 }
 694         }
 695 #endif
 696         start = get_timer(0);
 697         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 698                 if (get_timer(0) - start > MAX_RETRY_MS) {
 699                         printf("%s: timedout waiting for sysctl %x to clear\n",
 700                                 __func__, bit);
 701                         return;
 702                 }
 703         }
 704 }
 705
 706 #ifndef CONFIG_OMAP34XX
 707 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 708 {
 709         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 710         struct omap_hsmmc_adma_desc *desc;
 711         u8 attr;
 712
 713         desc = &priv->adma_desc_table[priv->desc_slot];
 714
 715         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 716         if (!end)
 717                 priv->desc_slot++;
 718         else
 719                 attr |= ADMA_DESC_ATTR_END;
 720
 721         desc->len = len;
 722         desc->addr = (u32)buf;
 723         desc->reserved = 0;
 724         desc->attr = attr;
 725 }
 726
 727 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 728                                           struct mmc_data *data)
 729 {
 730         uint total_len = data->blocksize * data->blocks;
 731         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 732         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 733         int i = desc_count;
 734         char *buf;
 735
 736         priv->desc_slot = 0;
 737         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 738                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 739                                 sizeof(struct omap_hsmmc_adma_desc));
 740
 741         if (data->flags & MMC_DATA_READ)
 742                 buf = data->dest;
 743         else
 744                 buf = (char *)data->src;
 745
 746         while (--i) {
 747                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 748                 buf += ADMA_MAX_LEN;
 749                 total_len -= ADMA_MAX_LEN;
 750         }
 751
 752         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 753
 754         flush_dcache_range((long)priv->adma_desc_table,
 755                            (long)priv->adma_desc_table +
 756                            ROUND(desc_count *
 757                            sizeof(struct omap_hsmmc_adma_desc),
 758                            ARCH_DMA_MINALIGN));
 759 }
 760
 761 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 762 {
 763         struct hsmmc *mmc_base;
 764         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 765         u32 val;
 766         char *buf;
 767
 768         mmc_base = priv->base_addr;
 769         omap_hsmmc_prepare_adma_table(mmc, data);
 770
 771         if (data->flags & MMC_DATA_READ)
 772                 buf = data->dest;
 773         else
 774                 buf = (char *)data->src;
 775
 776         val = readl(&mmc_base->hctl);
 777         val |= DMA_SELECT;
 778         writel(val, &mmc_base->hctl);
 779
 780         val = readl(&mmc_base->con);
 781         val |= DMA_MASTER;
 782         writel(val, &mmc_base->con);
 783
 784         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
 785
 786         flush_dcache_range((u32)buf,
 787                            (u32)buf +
 788                            ROUND(data->blocksize * data->blocks,
 789                                  ARCH_DMA_MINALIGN));
 790 }
 791
 792 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
 793 {
 794         struct hsmmc *mmc_base;
 795         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 796         u32 val;
 797
 798         mmc_base = priv->base_addr;
 799
 800         val = readl(&mmc_base->con);
 801         val &= ~DMA_MASTER;
 802         writel(val, &mmc_base->con);
 803
 804         val = readl(&mmc_base->hctl);
 805         val &= ~DMA_SELECT;
 806         writel(val, &mmc_base->hctl);
 807
 808         kfree(priv->adma_desc_table);
 809 }
 810 #else
 811 #define omap_hsmmc_adma_desc
 812 #define omap_hsmmc_prepare_adma_table
 813 #define omap_hsmmc_prepare_data
 814 #define omap_hsmmc_dma_cleanup
 815 #endif
 816
 817 #if !CONFIG_IS_ENABLED(DM_MMC)
 818 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 819                         struct mmc_data *data)
 820 {
 821         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 822 #else
 823 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 824                         struct mmc_data *data)
 825 {
 826         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 827         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 828         struct mmc *mmc = upriv->mmc;
 829 #endif
 830         struct hsmmc *mmc_base;
 831         unsigned int flags, mmc_stat;
 832         ulong start;
 833
 834         mmc_base = priv->base_addr;
 835
 836         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 837                 return 0;
 838
 839         start = get_timer(0);
 840         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 841                 if (get_timer(0) - start > MAX_RETRY_MS) {
 842                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 843                                         __func__);
 844                         return -ETIMEDOUT;
 845                 }
 846         }
 847         writel(0xFFFFFFFF, &mmc_base->stat);
 848         start = get_timer(0);
 849         while (readl(&mmc_base->stat)) {
 850                 if (get_timer(0) - start > MAX_RETRY_MS) {
 851                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 852                                 __func__, readl(&mmc_base->stat));
 853                         return -ETIMEDOUT;
 854                 }
 855         }
 856         /*
 857          * CMDREG
 858          * CMDIDX[13:8] : Command index
 859          * DATAPRNT[5]  : Data Present Select
 860          * ENCMDIDX[4]  : Command Index Check Enable
 861          * ENCMDCRC[3]  : Command CRC Check Enable
 862          * RSPTYP[1:0]
 863          *      00 = No Response
 864          *      01 = Length 136
 865          *      10 = Length 48
 866          *      11 = Length 48 Check busy after response
 867          */
 868         /* Delay added before checking the status of frq change
 869          * retry not supported by mmc.c(core file)
 870          */
 871         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 872                 udelay(50000); /* wait 50 ms */
 873
 874         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 875                 flags = 0;
 876         else if (cmd->resp_type & MMC_RSP_136)
 877                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 878         else if (cmd->resp_type & MMC_RSP_BUSY)
 879                 flags = RSP_TYPE_LGHT48B;
 880         else
 881                 flags = RSP_TYPE_LGHT48;
 882
 883         /* enable default flags */
 884         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 885                         MSBS_SGLEBLK);
 886         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
 887
 888         if (cmd->resp_type & MMC_RSP_CRC)
 889                 flags |= CCCE_CHECK;
 890         if (cmd->resp_type & MMC_RSP_OPCODE)
 891                 flags |= CICE_CHECK;
 892
 893         if (data) {
 894                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 895                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 896                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
 897                         data->blocksize = 512;
 898                         writel(data->blocksize | (data->blocks << 16),
 899                                                         &mmc_base->blk);
 900                 } else
 901                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 902
 903                 if (data->flags & MMC_DATA_READ)
 904                         flags |= (DP_DATA | DDIR_READ);
 905                 else
 906                         flags |= (DP_DATA | DDIR_WRITE);
 907
 908 #ifndef CONFIG_OMAP34XX
 909                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
 910                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
 911                         omap_hsmmc_prepare_data(mmc, data);
 912                         flags |= DE_ENABLE;
 913                 }
 914 #endif
 915         }
 916
 917         mmc_enable_irq(mmc, cmd);
 918
 919         writel(cmd->cmdarg, &mmc_base->arg);
 920         udelay(20);             /* To fix "No status update" error on eMMC */
 921         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 922
 923         start = get_timer(0);
 924         do {
 925                 mmc_stat = readl(&mmc_base->stat);
 926                 if (get_timer(start) > MAX_RETRY_MS) {
 927                         printf("%s : timeout: No status update\n", __func__);
 928                         return -ETIMEDOUT;
 929                 }
 930         } while (!mmc_stat);
 931
 932         if ((mmc_stat & IE_CTO) != 0) {
 933                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 934                 return -ETIMEDOUT;
 935         } else if ((mmc_stat & ERRI_MASK) != 0)
 936                 return -1;
 937
 938         if (mmc_stat & CC_MASK) {
 939                 writel(CC_MASK, &mmc_base->stat);
 940                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 941                         if (cmd->resp_type & MMC_RSP_136) {
 942                                 /* response type 2 */
 943                                 cmd->response[3] = readl(&mmc_base->rsp10);
 944                                 cmd->response[2] = readl(&mmc_base->rsp32);
 945                                 cmd->response[1] = readl(&mmc_base->rsp54);
 946                                 cmd->response[0] = readl(&mmc_base->rsp76);
 947                         } else
 948                                 /* response types 1, 1b, 3, 4, 5, 6 */
 949                                 cmd->response[0] = readl(&mmc_base->rsp10);
 950                 }
 951         }
 952
 953 #ifndef CONFIG_OMAP34XX
 954         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
 955             !mmc_is_tuning_cmd(cmd->cmdidx)) {
 956                 u32 sz_mb, timeout;
 957
 958                 if (mmc_stat & IE_ADMAE) {
 959                         omap_hsmmc_dma_cleanup(mmc);
 960                         return -EIO;
 961                 }
 962
 963                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
 964                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
 965                 if (timeout < MAX_RETRY_MS)
 966                         timeout = MAX_RETRY_MS;
 967
 968                 start = get_timer(0);
 969                 do {
 970                         mmc_stat = readl(&mmc_base->stat);
 971                         if (mmc_stat & TC_MASK) {
 972                                 writel(readl(&mmc_base->stat) | TC_MASK,
 973                                        &mmc_base->stat);
 974                                 break;
 975                         }
 976                         if (get_timer(start) > timeout) {
 977                                 printf("%s : DMA timeout: No status update\n",
 978                                        __func__);
 979                                 return -ETIMEDOUT;
 980                         }
 981                 } while (1);
 982
 983                 omap_hsmmc_dma_cleanup(mmc);
 984                 return 0;
 985         }
 986 #endif
 987
 988         if (data && (data->flags & MMC_DATA_READ)) {
 989                 mmc_read_data(mmc_base, data->dest,
 990                                 data->blocksize * data->blocks);
 991         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 992                 mmc_write_data(mmc_base, data->src,
 993                                 data->blocksize * data->blocks);
 994         }
 995         return 0;
 996 }
 997
 998 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 999 {
1000         unsigned int *output_buf = (unsigned int *)buf;
1001         unsigned int mmc_stat;
1002         unsigned int count;
1003
1004         /*
1005          * Start Polled Read
1006          */
1007         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1008         count /= 4;
1009
1010         while (size) {
1011                 ulong start = get_timer(0);
1012                 do {
1013                         mmc_stat = readl(&mmc_base->stat);
1014                         if (get_timer(0) - start > MAX_RETRY_MS) {
1015                                 printf("%s: timedout waiting for status!\n",
1016                                                 __func__);
1017                                 return -ETIMEDOUT;
1018                         }
1019                 } while (mmc_stat == 0);
1020
1021                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1022                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1023
1024                 if ((mmc_stat & ERRI_MASK) != 0)
1025                         return 1;
1026
1027                 if (mmc_stat & BRR_MASK) {
1028                         unsigned int k;
1029
1030                         writel(readl(&mmc_base->stat) | BRR_MASK,
1031                                 &mmc_base->stat);
1032                         for (k = 0; k < count; k++) {
1033                                 *output_buf = readl(&mmc_base->data);
1034                                 output_buf++;
1035                         }
1036                         size -= (count*4);
1037                 }
1038
1039                 if (mmc_stat & BWR_MASK)
1040                         writel(readl(&mmc_base->stat) | BWR_MASK,
1041                                 &mmc_base->stat);
1042
1043                 if (mmc_stat & TC_MASK) {
1044                         writel(readl(&mmc_base->stat) | TC_MASK,
1045                                 &mmc_base->stat);
1046                         break;
1047                 }
1048         }
1049         return 0;
1050 }
1051
1052 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1053                                 unsigned int size)
1054 {
1055         unsigned int *input_buf = (unsigned int *)buf;
1056         unsigned int mmc_stat;
1057         unsigned int count;
1058
1059         /*
1060          * Start Polled Write
1061          */
1062         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1063         count /= 4;
1064
1065         while (size) {
1066                 ulong start = get_timer(0);
1067                 do {
1068                         mmc_stat = readl(&mmc_base->stat);
1069                         if (get_timer(0) - start > MAX_RETRY_MS) {
1070                                 printf("%s: timedout waiting for status!\n",
1071                                                 __func__);
1072                                 return -ETIMEDOUT;
1073                         }
1074                 } while (mmc_stat == 0);
1075
1076                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1077                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1078
1079                 if ((mmc_stat & ERRI_MASK) != 0)
1080                         return 1;
1081
1082                 if (mmc_stat & BWR_MASK) {
1083                         unsigned int k;
1084
1085                         writel(readl(&mmc_base->stat) | BWR_MASK,
1086                                         &mmc_base->stat);
1087                         for (k = 0; k < count; k++) {
1088                                 writel(*input_buf, &mmc_base->data);
1089                                 input_buf++;
1090                         }
1091                         size -= (count*4);
1092                 }
1093
1094                 if (mmc_stat & BRR_MASK)
1095                         writel(readl(&mmc_base->stat) | BRR_MASK,
1096                                 &mmc_base->stat);
1097
1098                 if (mmc_stat & TC_MASK) {
1099                         writel(readl(&mmc_base->stat) | TC_MASK,
1100                                 &mmc_base->stat);
1101                         break;
1102                 }
1103         }
1104         return 0;
1105 }
1106
1107 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1108 {
1109         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1110 }
1111
1112 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1113 {
1114         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1115 }
1116
1117 static void omap_hsmmc_set_clock(struct mmc *mmc)
1118 {
1119         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1120         struct hsmmc *mmc_base;
1121         unsigned int dsor = 0;
1122         ulong start;
1123
1124         mmc_base = priv->base_addr;
1125         omap_hsmmc_stop_clock(mmc_base);
1126
1127         /* TODO: Is setting DTO required here? */
1128         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1129                     (ICE_STOP | DTO_15THDTO));
1130
1131         if (mmc->clock != 0) {
1132                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1133                 if (dsor > CLKD_MAX)
1134                         dsor = CLKD_MAX;
1135         } else {
1136                 dsor = CLKD_MAX;
1137         }
1138
1139         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1140                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1141
1142         start = get_timer(0);
1143         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1144                 if (get_timer(0) - start > MAX_RETRY_MS) {
1145                         printf("%s: timedout waiting for ics!\n", __func__);
1146                         return;
1147                 }
1148         }
1149
1150         priv->clock = mmc->clock;
1151         omap_hsmmc_start_clock(mmc_base);
1152 }
1153
1154 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1155 {
1156         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1157         struct hsmmc *mmc_base;
1158
1159         mmc_base = priv->base_addr;
1160         /* configue bus width */
1161         switch (mmc->bus_width) {
1162         case 8:
1163                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1164                         &mmc_base->con);
1165                 break;
1166
1167         case 4:
1168                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1169                         &mmc_base->con);
1170                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1171                         &mmc_base->hctl);
1172                 break;
1173
1174         case 1:
1175         default:
1176                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1177                         &mmc_base->con);
1178                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1179                         &mmc_base->hctl);
1180                 break;
1181         }
1182
1183         priv->bus_width = mmc->bus_width;
1184 }
1185
1186 #if !CONFIG_IS_ENABLED(DM_MMC)
1187 static int omap_hsmmc_set_ios(struct mmc *mmc)
1188 {
1189         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1190 #else
1191 static int omap_hsmmc_set_ios(struct udevice *dev)
1192 {
1193         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1194         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1195         struct mmc *mmc = upriv->mmc;
1196 #endif
1197
1198         if (priv->bus_width != mmc->bus_width)
1199                 omap_hsmmc_set_bus_width(mmc);
1200
1201         if (priv->clock != mmc->clock)
1202                 omap_hsmmc_set_clock(mmc);
1203
1204 #if CONFIG_IS_ENABLED(DM_MMC)
1205         if (priv->mode != mmc->selected_mode)
1206                 omap_hsmmc_set_timing(mmc);
1207 #endif
1208         return 0;
1209 }
1210
1211 #ifdef OMAP_HSMMC_USE_GPIO
1212 #if CONFIG_IS_ENABLED(DM_MMC)
1213 static int omap_hsmmc_getcd(struct udevice *dev)
1214 {
1215         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1216         int value;
1217
1218         value = dm_gpio_get_value(&priv->cd_gpio);
1219         /* if no CD return as 1 */
1220         if (value < 0)
1221                 return 1;
1222
1223         if (priv->cd_inverted)
1224                 return !value;
1225         return value;
1226 }
1227
1228 static int omap_hsmmc_getwp(struct udevice *dev)
1229 {
1230         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1231         int value;
1232
1233         value = dm_gpio_get_value(&priv->wp_gpio);
1234         /* if no WP return as 0 */
1235         if (value < 0)
1236                 return 0;
1237         return value;
1238 }
1239 #else
1240 static int omap_hsmmc_getcd(struct mmc *mmc)
1241 {
1242         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1243         int cd_gpio;
1244
1245         /* if no CD return as 1 */
1246         cd_gpio = priv->cd_gpio;
1247         if (cd_gpio < 0)
1248                 return 1;
1249
1250         /* NOTE: assumes card detect signal is active-low */
1251         return !gpio_get_value(cd_gpio);
1252 }
1253
1254 static int omap_hsmmc_getwp(struct mmc *mmc)
1255 {
1256         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1257         int wp_gpio;
1258
1259         /* if no WP return as 0 */
1260         wp_gpio = priv->wp_gpio;
1261         if (wp_gpio < 0)
1262                 return 0;
1263
1264         /* NOTE: assumes write protect signal is active-high */
1265         return gpio_get_value(wp_gpio);
1266 }
1267 #endif
1268 #endif
1269
1270 #if CONFIG_IS_ENABLED(DM_MMC)
1271 static const struct dm_mmc_ops omap_hsmmc_ops = {
1272         .send_cmd       = omap_hsmmc_send_cmd,
1273         .set_ios        = omap_hsmmc_set_ios,
1274 #ifdef OMAP_HSMMC_USE_GPIO
1275         .get_cd         = omap_hsmmc_getcd,
1276         .get_wp         = omap_hsmmc_getwp,
1277 #endif
1278 #ifdef MMC_SUPPORTS_TUNING
1279         .execute_tuning = omap_hsmmc_execute_tuning,
1280 #endif
1281 };
1282 #else
1283 static const struct mmc_ops omap_hsmmc_ops = {
1284         .send_cmd       = omap_hsmmc_send_cmd,
1285         .set_ios        = omap_hsmmc_set_ios,
1286         .init           = omap_hsmmc_init_setup,
1287 #ifdef OMAP_HSMMC_USE_GPIO
1288         .getcd          = omap_hsmmc_getcd,
1289         .getwp          = omap_hsmmc_getwp,
1290 #endif
1291 };
1292 #endif
1293
1294 #if !CONFIG_IS_ENABLED(DM_MMC)
1295 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1296                 int wp_gpio)
1297 {
1298         struct mmc *mmc;
1299         struct omap_hsmmc_data *priv;
1300         struct mmc_config *cfg;
1301         uint host_caps_val;
1302
1303         priv = malloc(sizeof(*priv));
1304         if (priv == NULL)
1305                 return -1;
1306
1307         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1308
1309         switch (dev_index) {
1310         case 0:
1311                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1312                 break;
1313 #ifdef OMAP_HSMMC2_BASE
1314         case 1:
1315                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1316 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1317         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1318         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1319                 defined(CONFIG_HSMMC2_8BIT)
1320                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1321                 host_caps_val |= MMC_MODE_8BIT;
1322 #endif
1323                 break;
1324 #endif
1325 #ifdef OMAP_HSMMC3_BASE
1326         case 2:
1327                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1328 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1329                 /* Enable 8-bit interface for eMMC on DRA7XX */
1330                 host_caps_val |= MMC_MODE_8BIT;
1331 #endif
1332                 break;
1333 #endif
1334         default:
1335                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1336                 return 1;
1337         }
1338 #ifdef OMAP_HSMMC_USE_GPIO
1339         /* on error gpio values are set to -1, which is what we want */
1340         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1341         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1342 #endif
1343
1344         cfg = &priv->cfg;
1345
1346         cfg->name = "OMAP SD/MMC";
1347         cfg->ops = &omap_hsmmc_ops;
1348
1349         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1350         cfg->host_caps = host_caps_val & ~host_caps_mask;
1351
1352         cfg->f_min = 400000;
1353
1354         if (f_max != 0)
1355                 cfg->f_max = f_max;
1356         else {
1357                 if (cfg->host_caps & MMC_MODE_HS) {
1358                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1359                                 cfg->f_max = 52000000;
1360                         else
1361                                 cfg->f_max = 26000000;
1362                 } else
1363                         cfg->f_max = 20000000;
1364         }
1365
1366         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1367
1368 #if defined(CONFIG_OMAP34XX)
1369         /*
1370          * Silicon revs 2.1 and older do not support multiblock transfers.
1371          */
1372         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1373                 cfg->b_max = 1;
1374 #endif
1375
1376         mmc = mmc_create(cfg, priv);
1377         if (mmc == NULL)
1378                 return -1;
1379
1380         return 0;
1381 }
1382 #else
1383
1384 #ifdef CONFIG_IODELAY_RECALIBRATION
1385 static struct pad_conf_entry *
1386 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1387 {
1388         int index = 0;
1389         struct pad_conf_entry *padconf;
1390
1391         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1392         if (!padconf) {
1393                 debug("failed to allocate memory\n");
1394                 return 0;
1395         }
1396
1397         while (index < count) {
1398                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1399                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1400                 index++;
1401         }
1402
1403         return padconf;
1404 }
1405
1406 static struct iodelay_cfg_entry *
1407 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1408 {
1409         int index = 0;
1410         struct iodelay_cfg_entry *iodelay;
1411
1412         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1413         if (!iodelay) {
1414                 debug("failed to allocate memory\n");
1415                 return 0;
1416         }
1417
1418         while (index < count) {
1419                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1420                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1421                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1422                 index++;
1423         }
1424
1425         return iodelay;
1426 }
1427
1428 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1429                                                    const char *name, int *len)
1430 {
1431         const void *fdt = gd->fdt_blob;
1432         int offset;
1433         const fdt32_t *pinctrl;
1434
1435         offset = fdt_node_offset_by_phandle(fdt, phandle);
1436         if (offset < 0) {
1437                 debug("failed to get pinctrl node %s.\n",
1438                       fdt_strerror(offset));
1439                 return 0;
1440         }
1441
1442         pinctrl = fdt_getprop(fdt, offset, name, len);
1443         if (!pinctrl) {
1444                 debug("failed to get property %s\n", name);
1445                 return 0;
1446         }
1447
1448         return pinctrl;
1449 }
1450
1451 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1452                                                 char *prop_name)
1453 {
1454         const void *fdt = gd->fdt_blob;
1455         const __be32 *phandle;
1456         int node = dev_of_offset(mmc->dev);
1457
1458         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1459         if (!phandle) {
1460                 debug("failed to get property %s\n", prop_name);
1461                 return 0;
1462         }
1463
1464         return fdt32_to_cpu(*phandle);
1465 }
1466
1467 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1468                                                char *prop_name)
1469 {
1470         const void *fdt = gd->fdt_blob;
1471         const __be32 *phandle;
1472         int len;
1473         int count;
1474         int node = dev_of_offset(mmc->dev);
1475
1476         phandle = fdt_getprop(fdt, node, prop_name, &len);
1477         if (!phandle) {
1478                 debug("failed to get property %s\n", prop_name);
1479                 return 0;
1480         }
1481
1482         /* No manual mode iodelay values if count < 2 */
1483         count = len / sizeof(*phandle);
1484         if (count < 2)
1485                 return 0;
1486
1487         return fdt32_to_cpu(*(phandle + 1));
1488 }
1489
1490 static struct pad_conf_entry *
1491 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1492 {
1493         int len;
1494         int count;
1495         struct pad_conf_entry *padconf;
1496         u32 phandle;
1497         const fdt32_t *pinctrl;
1498
1499         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1500         if (!phandle)
1501                 return ERR_PTR(-EINVAL);
1502
1503         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1504                                                &len);
1505         if (!pinctrl)
1506                 return ERR_PTR(-EINVAL);
1507
1508         count = (len / sizeof(*pinctrl)) / 2;
1509         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1510         if (!padconf)
1511                 return ERR_PTR(-EINVAL);
1512
1513         *npads = count;
1514
1515         return padconf;
1516 }
1517
1518 static struct iodelay_cfg_entry *
1519 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1520 {
1521         int len;
1522         int count;
1523         struct iodelay_cfg_entry *iodelay;
1524         u32 phandle;
1525         const fdt32_t *pinctrl;
1526
1527         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1528         /* Not all modes have manual mode iodelay values. So its not fatal */
1529         if (!phandle)
1530                 return 0;
1531
1532         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1533                                                &len);
1534         if (!pinctrl)
1535                 return ERR_PTR(-EINVAL);
1536
1537         count = (len / sizeof(*pinctrl)) / 3;
1538         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1539         if (!iodelay)
1540                 return ERR_PTR(-EINVAL);
1541
1542         *niodelay = count;
1543
1544         return iodelay;
1545 }
1546
1547 static struct omap_hsmmc_pinctrl_state *
1548 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1549 {
1550         int index;
1551         int npads = 0;
1552         int niodelays = 0;
1553         const void *fdt = gd->fdt_blob;
1554         int node = dev_of_offset(mmc->dev);
1555         char prop_name[11];
1556         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1557
1558         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1559                          malloc(sizeof(*pinctrl_state));
1560         if (!pinctrl_state) {
1561                 debug("failed to allocate memory\n");
1562                 return 0;
1563         }
1564
1565         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1566         if (index < 0) {
1567                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1568                 goto err_pinctrl_state;
1569         }
1570
1571         sprintf(prop_name, "pinctrl-%d", index);
1572
1573         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1574                                                          &npads);
1575         if (IS_ERR(pinctrl_state->padconf))
1576                 goto err_pinctrl_state;
1577         pinctrl_state->npads = npads;
1578
1579         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1580                                                         &niodelays);
1581         if (IS_ERR(pinctrl_state->iodelay))
1582                 goto err_padconf;
1583         pinctrl_state->niodelays = niodelays;
1584
1585         return pinctrl_state;
1586
1587 err_padconf:
1588         kfree(pinctrl_state->padconf);
1589
1590 err_pinctrl_state:
1591         kfree(pinctrl_state);
1592         return 0;
1593 }
1594
1595 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1596         do {                                                            \
1597                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1598                 char str[20];                                           \
1599                 if (!(cfg->host_caps & capmask))                        \
1600                         break;                                          \
1601                                                                         \
1602                 if (priv->hw_rev) {                                     \
1603                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1604                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1605                 }                                                       \
1606                                                                         \
1607                 if (!s)                                                 \
1608                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1609                                                                         \
1610                 if (!s && !optional) {                                  \
1611                         debug("%s: no pinctrl for %s\n",                \
1612                               mmc->dev->name, #mode);                   \
1613                         cfg->host_caps &= ~(capmask);                   \
1614                 } else {                                                \
1615                         priv->mode##_pinctrl_state = s;                 \
1616                 }                                                       \
1617         } while (0)
1618
1619 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1620 {
1621         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1622         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1623         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1624
1625         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1626                 return 0;
1627
1628         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1629         if (!default_pinctrl) {
1630                 printf("no pinctrl state for default mode\n");
1631                 return -EINVAL;
1632         }
1633
1634         priv->default_pinctrl_state = default_pinctrl;
1635
1636         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1637         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1638         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1639         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1640         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1641
1642         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1643         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1644         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1645
1646         return 0;
1647 }
1648 #endif
1649
1650 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1651 #ifdef CONFIG_OMAP54XX
1652 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1653 {
1654         return NULL;
1655 }
1656 #endif
1657
1658 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1659 {
1660         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1661         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1662
1663         struct mmc_config *cfg = &plat->cfg;
1664 #ifdef CONFIG_OMAP54XX
1665         const struct mmc_platform_fixups *fixups;
1666 #endif
1667         const void *fdt = gd->fdt_blob;
1668         int node = dev_of_offset(dev);
1669         int ret;
1670
1671         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1672                                       sizeof(struct hsmmc *),
1673                                       MAP_NOCACHE);
1674
1675         ret = mmc_of_parse(dev, cfg);
1676         if (ret < 0)
1677                 return ret;
1678
1679         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1680         cfg->f_min = 400000;
1681         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1682         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1683         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1684                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1685         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1686                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1687         if (of_data)
1688                 plat->controller_flags |= of_data->controller_flags;
1689
1690 #ifdef CONFIG_OMAP54XX
1691         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1692         if (fixups) {
1693                 plat->hw_rev = fixups->hw_rev;
1694                 cfg->host_caps &= ~fixups->unsupported_caps;
1695                 cfg->f_max = fixups->max_freq;
1696         }
1697 #endif
1698
1699 #ifdef OMAP_HSMMC_USE_GPIO
1700         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1701 #endif
1702
1703         return 0;
1704 }
1705 #endif
1706
1707 #ifdef CONFIG_BLK
1708
1709 static int omap_hsmmc_bind(struct udevice *dev)
1710 {
1711         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1712
1713         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1714 }
1715 #endif
1716 static int omap_hsmmc_probe(struct udevice *dev)
1717 {
1718         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1719         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1720         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1721         struct mmc_config *cfg = &plat->cfg;
1722         struct mmc *mmc;
1723 #ifdef CONFIG_IODELAY_RECALIBRATION
1724         int ret;
1725 #endif
1726
1727         cfg->name = "OMAP SD/MMC";
1728         priv->base_addr = plat->base_addr;
1729         priv->controller_flags = plat->controller_flags;
1730         priv->hw_rev = plat->hw_rev;
1731 #ifdef OMAP_HSMMC_USE_GPIO
1732         priv->cd_inverted = plat->cd_inverted;
1733 #endif
1734
1735 #ifdef CONFIG_BLK
1736         mmc = &plat->mmc;
1737 #else
1738         mmc = mmc_create(cfg, priv);
1739         if (mmc == NULL)
1740                 return -1;
1741 #endif
1742
1743 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1744         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1745         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1746 #endif
1747
1748         mmc->dev = dev;
1749         upriv->mmc = mmc;
1750
1751 #ifdef CONFIG_IODELAY_RECALIBRATION
1752         ret = omap_hsmmc_get_pinctrl_state(mmc);
1753         /*
1754          * disable high speed modes for the platforms that require IO delay
1755          * and for which we don't have this information
1756          */
1757         if ((ret < 0) &&
1758             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1759                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1760                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1761                                     UHS_CAPS);
1762         }
1763 #endif
1764
1765         return omap_hsmmc_init_setup(mmc);
1766 }
1767
1768 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1769
1770 static const struct omap_mmc_of_data dra7_mmc_of_data = {
1771         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
1772 };
1773
1774 static const struct udevice_id omap_hsmmc_ids[] = {
1775         { .compatible = "ti,omap3-hsmmc" },
1776         { .compatible = "ti,omap4-hsmmc" },
1777         { .compatible = "ti,am33xx-hsmmc" },
1778         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
1779         { }
1780 };
1781 #endif
1782
1783 U_BOOT_DRIVER(omap_hsmmc) = {
1784         .name   = "omap_hsmmc",
1785         .id     = UCLASS_MMC,
1786 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1787         .of_match = omap_hsmmc_ids,
1788         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1789         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1790 #endif
1791 #ifdef CONFIG_BLK
1792         .bind = omap_hsmmc_bind,
1793 #endif
1794         .ops = &omap_hsmmc_ops,
1795         .probe  = omap_hsmmc_probe,
1796         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1797         .flags  = DM_FLAG_PRE_RELOC,
1798 };
1799 #endif