git.sur5r.net Git - u-boot/blob - drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #if !defined(CONFIG_SOC_KEYSTONE)
  38 #include <asm/gpio.h>
  39 #include <asm/arch/sys_proto.h>
  40 #endif
  41 #ifdef CONFIG_MMC_OMAP36XX_PINS
  42 #include <asm/arch/mux.h>
  43 #endif
  44 #include <dm.h>
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  49 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  50         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  51 #define OMAP_HSMMC_USE_GPIO
  52 #else
  53 #undef OMAP_HSMMC_USE_GPIO
  54 #endif
  55
  56 /* common definitions for all OMAPs */
  57 #define SYSCTL_SRC      (1 << 25)
  58 #define SYSCTL_SRD      (1 << 26)
  59
  60 struct omap_hsmmc_data {
  61         struct hsmmc *base_addr;
  62 #if !CONFIG_IS_ENABLED(DM_MMC)
  63         struct mmc_config cfg;
  64 #endif
  65         uint bus_width;
  66         uint clock;
  67 #ifdef OMAP_HSMMC_USE_GPIO
  68 #if CONFIG_IS_ENABLED(DM_MMC)
  69         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  70         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  71         bool cd_inverted;
  72 #else
  73         int cd_gpio;
  74         int wp_gpio;
  75 #endif
  76 #endif
  77 #if CONFIG_IS_ENABLED(DM_MMC)
  78         uint iov;
  79 #endif
  80         u8 controller_flags;
  81 #ifndef CONFIG_OMAP34XX
  82         struct omap_hsmmc_adma_desc *adma_desc_table;
  83         uint desc_slot;
  84 #endif
  85 };
  86
  87 #ifndef CONFIG_OMAP34XX
  88 struct omap_hsmmc_adma_desc {
  89         u8 attr;
  90         u8 reserved;
  91         u16 len;
  92         u32 addr;
  93 };
  94
  95 #define ADMA_MAX_LEN    63488
  96
  97 /* Decriptor table defines */
  98 #define ADMA_DESC_ATTR_VALID            BIT(0)
  99 #define ADMA_DESC_ATTR_END              BIT(1)
 100 #define ADMA_DESC_ATTR_INT              BIT(2)
 101 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 102 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 103
 104 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 105 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 106 #endif
 107
 108 /* If we fail after 1 second wait, something is really bad */
 109 #define MAX_RETRY_MS    1000
 110
 111 /* DMA transfers can take a long time if a lot a data is transferred.
 112  * The timeout must take in account the amount of data. Let's assume
 113  * that the time will never exceed 333 ms per MB (in other word we assume
 114  * that the bandwidth is always above 3MB/s).
 115  */
 116 #define DMA_TIMEOUT_PER_MB      333
 117 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 118 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 119 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 120
 121 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 122 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 123                         unsigned int siz);
 124 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 125 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 126
 127 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 128 {
 129 #if CONFIG_IS_ENABLED(DM_MMC)
 130         return dev_get_priv(mmc->dev);
 131 #else
 132         return (struct omap_hsmmc_data *)mmc->priv;
 133 #endif
 134 }
 135 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 136 {
 137 #if CONFIG_IS_ENABLED(DM_MMC)
 138         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 139         return &plat->cfg;
 140 #else
 141         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 142 #endif
 143 }
 144
 145 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 146 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 147 {
 148         int ret;
 149
 150 #ifndef CONFIG_DM_GPIO
 151         if (!gpio_is_valid(gpio))
 152                 return -1;
 153 #endif
 154         ret = gpio_request(gpio, label);
 155         if (ret)
 156                 return ret;
 157
 158         ret = gpio_direction_input(gpio);
 159         if (ret)
 160                 return ret;
 161
 162         return gpio;
 163 }
 164 #endif
 165
 166 static unsigned char mmc_board_init(struct mmc *mmc)
 167 {
 168 #if defined(CONFIG_OMAP34XX)
 169         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 170         t2_t *t2_base = (t2_t *)T2_BASE;
 171         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 172         u32 pbias_lite;
 173 #ifdef CONFIG_MMC_OMAP36XX_PINS
 174         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 175 #endif
 176
 177         pbias_lite = readl(&t2_base->pbias_lite);
 178         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 179 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 180         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 181         pbias_lite &= ~PBIASLITEVMODE0;
 182 #endif
 183 #ifdef CONFIG_MMC_OMAP36XX_PINS
 184         if (get_cpu_family() == CPU_OMAP36XX) {
 185                 /* Disable extended drain IO before changing PBIAS */
 186                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 187                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 188         }
 189 #endif
 190         writel(pbias_lite, &t2_base->pbias_lite);
 191
 192         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 193                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 194                 &t2_base->pbias_lite);
 195
 196 #ifdef CONFIG_MMC_OMAP36XX_PINS
 197         if (get_cpu_family() == CPU_OMAP36XX)
 198                 /* Enable extended drain IO after changing PBIAS */
 199                 writel(wkup_ctrl |
 200                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 201                                 OMAP34XX_CTRL_WKUP_CTRL);
 202 #endif
 203         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 204                 &t2_base->devconf0);
 205
 206         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 207                 &t2_base->devconf1);
 208
 209         /* Change from default of 52MHz to 26MHz if necessary */
 210         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 211                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 212                         &t2_base->ctl_prog_io1);
 213
 214         writel(readl(&prcm_base->fclken1_core) |
 215                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 216                 &prcm_base->fclken1_core);
 217
 218         writel(readl(&prcm_base->iclken1_core) |
 219                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 220                 &prcm_base->iclken1_core);
 221 #endif
 222
 223 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 224         /* PBIAS config needed for MMC1 only */
 225         if (mmc_get_blk_desc(mmc)->devnum == 0)
 226                 vmmc_pbias_config(LDO_VOLT_3V0);
 227 #endif
 228
 229         return 0;
 230 }
 231
 232 void mmc_init_stream(struct hsmmc *mmc_base)
 233 {
 234         ulong start;
 235
 236         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 237
 238         writel(MMC_CMD0, &mmc_base->cmd);
 239         start = get_timer(0);
 240         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 241                 if (get_timer(0) - start > MAX_RETRY_MS) {
 242                         printf("%s: timedout waiting for cc!\n", __func__);
 243                         return;
 244                 }
 245         }
 246         writel(CC_MASK, &mmc_base->stat)
 247                 ;
 248         writel(MMC_CMD0, &mmc_base->cmd)
 249                 ;
 250         start = get_timer(0);
 251         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 252                 if (get_timer(0) - start > MAX_RETRY_MS) {
 253                         printf("%s: timedout waiting for cc2!\n", __func__);
 254                         return;
 255                 }
 256         }
 257         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 258 }
 259
 260 #if CONFIG_IS_ENABLED(DM_MMC)
 261 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
 262 {
 263         struct hsmmc *mmc_base;
 264         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 265         u32 val;
 266
 267         mmc_base = priv->base_addr;
 268
 269         val = readl(&mmc_base->hctl) & ~SDVS_MASK;
 270
 271         switch (priv->iov) {
 272         case IOV_3V3:
 273                 val |= SDVS_3V3;
 274                 break;
 275         case IOV_3V0:
 276                 val |= SDVS_3V0;
 277                 break;
 278         case IOV_1V8:
 279                 val |= SDVS_1V8;
 280                 break;
 281         }
 282
 283         writel(val, &mmc_base->hctl);
 284 }
 285
 286 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
 287 {
 288         struct hsmmc *mmc_base;
 289         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 290         u32 val;
 291
 292         mmc_base = priv->base_addr;
 293         val = readl(&mmc_base->capa);
 294
 295         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 296                 val |= (VS30_3V0SUP | VS18_1V8SUP);
 297                 priv->iov = IOV_3V0;
 298         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 299                 val |= VS30_3V0SUP;
 300                 val &= ~VS18_1V8SUP;
 301                 priv->iov = IOV_3V0;
 302         } else {
 303                 val |= VS18_1V8SUP;
 304                 val &= ~VS30_3V0SUP;
 305                 priv->iov = IOV_1V8;
 306         }
 307
 308         writel(val, &mmc_base->capa);
 309 }
 310 #endif
 311
 312 static int omap_hsmmc_init_setup(struct mmc *mmc)
 313 {
 314         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 315         struct hsmmc *mmc_base;
 316         unsigned int reg_val;
 317         unsigned int dsor;
 318         ulong start;
 319
 320         mmc_base = priv->base_addr;
 321         mmc_board_init(mmc);
 322
 323         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 324                 &mmc_base->sysconfig);
 325         start = get_timer(0);
 326         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 327                 if (get_timer(0) - start > MAX_RETRY_MS) {
 328                         printf("%s: timedout waiting for cc2!\n", __func__);
 329                         return -ETIMEDOUT;
 330                 }
 331         }
 332         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 333         start = get_timer(0);
 334         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 335                 if (get_timer(0) - start > MAX_RETRY_MS) {
 336                         printf("%s: timedout waiting for softresetall!\n",
 337                                 __func__);
 338                         return -ETIMEDOUT;
 339                 }
 340         }
 341 #ifndef CONFIG_OMAP34XX
 342         reg_val = readl(&mmc_base->hl_hwinfo);
 343         if (reg_val & MADMA_EN)
 344                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 345 #endif
 346
 347 #if CONFIG_IS_ENABLED(DM_MMC)
 348         omap_hsmmc_set_capabilities(mmc);
 349         omap_hsmmc_conf_bus_power(mmc);
 350 #else
 351         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 352         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 353                 &mmc_base->capa);
 354 #endif
 355
 356         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 357
 358         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 359                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 360                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 361
 362         dsor = 240;
 363         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 364                 (ICE_STOP | DTO_15THDTO));
 365         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 366                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 367         start = get_timer(0);
 368         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 369                 if (get_timer(0) - start > MAX_RETRY_MS) {
 370                         printf("%s: timedout waiting for ics!\n", __func__);
 371                         return -ETIMEDOUT;
 372                 }
 373         }
 374         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 375
 376         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 377
 378         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 379                 IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
 380                 IE_CC, &mmc_base->ie);
 381
 382         mmc_init_stream(mmc_base);
 383
 384         return 0;
 385 }
 386
 387 /*
 388  * MMC controller internal finite state machine reset
 389  *
 390  * Used to reset command or data internal state machines, using respectively
 391  * SRC or SRD bit of SYSCTL register
 392  */
 393 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 394 {
 395         ulong start;
 396
 397         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 398
 399         /*
 400          * CMD(DAT) lines reset procedures are slightly different
 401          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 402          * According to OMAP3 TRM:
 403          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 404          * returns to 0x0.
 405          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 406          * procedure steps must be as follows:
 407          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 408          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 409          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 410          * 3. Wait until the SRC (SRD) bit returns to 0x0
 411          *    (reset procedure is completed).
 412          */
 413 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 414         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 415         if (!(readl(&mmc_base->sysctl) & bit)) {
 416                 start = get_timer(0);
 417                 while (!(readl(&mmc_base->sysctl) & bit)) {
 418                         if (get_timer(0) - start > MAX_RETRY_MS)
 419                                 return;
 420                 }
 421         }
 422 #endif
 423         start = get_timer(0);
 424         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 425                 if (get_timer(0) - start > MAX_RETRY_MS) {
 426                         printf("%s: timedout waiting for sysctl %x to clear\n",
 427                                 __func__, bit);
 428                         return;
 429                 }
 430         }
 431 }
 432
 433 #ifndef CONFIG_OMAP34XX
 434 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 435 {
 436         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 437         struct omap_hsmmc_adma_desc *desc;
 438         u8 attr;
 439
 440         desc = &priv->adma_desc_table[priv->desc_slot];
 441
 442         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 443         if (!end)
 444                 priv->desc_slot++;
 445         else
 446                 attr |= ADMA_DESC_ATTR_END;
 447
 448         desc->len = len;
 449         desc->addr = (u32)buf;
 450         desc->reserved = 0;
 451         desc->attr = attr;
 452 }
 453
 454 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 455                                           struct mmc_data *data)
 456 {
 457         uint total_len = data->blocksize * data->blocks;
 458         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 459         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 460         int i = desc_count;
 461         char *buf;
 462
 463         priv->desc_slot = 0;
 464         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 465                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 466                                 sizeof(struct omap_hsmmc_adma_desc));
 467
 468         if (data->flags & MMC_DATA_READ)
 469                 buf = data->dest;
 470         else
 471                 buf = (char *)data->src;
 472
 473         while (--i) {
 474                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 475                 buf += ADMA_MAX_LEN;
 476                 total_len -= ADMA_MAX_LEN;
 477         }
 478
 479         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 480
 481         flush_dcache_range((long)priv->adma_desc_table,
 482                            (long)priv->adma_desc_table +
 483                            ROUND(desc_count *
 484                            sizeof(struct omap_hsmmc_adma_desc),
 485                            ARCH_DMA_MINALIGN));
 486 }
 487
 488 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 489 {
 490         struct hsmmc *mmc_base;
 491         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 492         u32 val;
 493         char *buf;
 494
 495         mmc_base = priv->base_addr;
 496         omap_hsmmc_prepare_adma_table(mmc, data);
 497
 498         if (data->flags & MMC_DATA_READ)
 499                 buf = data->dest;
 500         else
 501                 buf = (char *)data->src;
 502
 503         val = readl(&mmc_base->hctl);
 504         val |= DMA_SELECT;
 505         writel(val, &mmc_base->hctl);
 506
 507         val = readl(&mmc_base->con);
 508         val |= DMA_MASTER;
 509         writel(val, &mmc_base->con);
 510
 511         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
 512
 513         flush_dcache_range((u32)buf,
 514                            (u32)buf +
 515                            ROUND(data->blocksize * data->blocks,
 516                                  ARCH_DMA_MINALIGN));
 517 }
 518
 519 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
 520 {
 521         struct hsmmc *mmc_base;
 522         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 523         u32 val;
 524
 525         mmc_base = priv->base_addr;
 526
 527         val = readl(&mmc_base->con);
 528         val &= ~DMA_MASTER;
 529         writel(val, &mmc_base->con);
 530
 531         val = readl(&mmc_base->hctl);
 532         val &= ~DMA_SELECT;
 533         writel(val, &mmc_base->hctl);
 534
 535         kfree(priv->adma_desc_table);
 536 }
 537 #else
 538 #define omap_hsmmc_adma_desc
 539 #define omap_hsmmc_prepare_adma_table
 540 #define omap_hsmmc_prepare_data
 541 #define omap_hsmmc_dma_cleanup
 542 #endif
 543
 544 #if !CONFIG_IS_ENABLED(DM_MMC)
 545 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 546                         struct mmc_data *data)
 547 {
 548         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 549 #else
 550 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 551                         struct mmc_data *data)
 552 {
 553         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 554 #ifndef CONFIG_OMAP34XX
 555         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 556         struct mmc *mmc = upriv->mmc;
 557 #endif
 558 #endif
 559         struct hsmmc *mmc_base;
 560         unsigned int flags, mmc_stat;
 561         ulong start;
 562
 563         mmc_base = priv->base_addr;
 564
 565         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 566                 return 0;
 567
 568         start = get_timer(0);
 569         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 570                 if (get_timer(0) - start > MAX_RETRY_MS) {
 571                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 572                                         __func__);
 573                         return -ETIMEDOUT;
 574                 }
 575         }
 576         writel(0xFFFFFFFF, &mmc_base->stat);
 577         start = get_timer(0);
 578         while (readl(&mmc_base->stat)) {
 579                 if (get_timer(0) - start > MAX_RETRY_MS) {
 580                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 581                                 __func__, readl(&mmc_base->stat));
 582                         return -ETIMEDOUT;
 583                 }
 584         }
 585         /*
 586          * CMDREG
 587          * CMDIDX[13:8] : Command index
 588          * DATAPRNT[5]  : Data Present Select
 589          * ENCMDIDX[4]  : Command Index Check Enable
 590          * ENCMDCRC[3]  : Command CRC Check Enable
 591          * RSPTYP[1:0]
 592          *      00 = No Response
 593          *      01 = Length 136
 594          *      10 = Length 48
 595          *      11 = Length 48 Check busy after response
 596          */
 597         /* Delay added before checking the status of frq change
 598          * retry not supported by mmc.c(core file)
 599          */
 600         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 601                 udelay(50000); /* wait 50 ms */
 602
 603         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 604                 flags = 0;
 605         else if (cmd->resp_type & MMC_RSP_136)
 606                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 607         else if (cmd->resp_type & MMC_RSP_BUSY)
 608                 flags = RSP_TYPE_LGHT48B;
 609         else
 610                 flags = RSP_TYPE_LGHT48;
 611
 612         /* enable default flags */
 613         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 614                         MSBS_SGLEBLK);
 615         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
 616
 617         if (cmd->resp_type & MMC_RSP_CRC)
 618                 flags |= CCCE_CHECK;
 619         if (cmd->resp_type & MMC_RSP_OPCODE)
 620                 flags |= CICE_CHECK;
 621
 622         if (data) {
 623                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 624                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 625                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
 626                         data->blocksize = 512;
 627                         writel(data->blocksize | (data->blocks << 16),
 628                                                         &mmc_base->blk);
 629                 } else
 630                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 631
 632                 if (data->flags & MMC_DATA_READ)
 633                         flags |= (DP_DATA | DDIR_READ);
 634                 else
 635                         flags |= (DP_DATA | DDIR_WRITE);
 636
 637 #ifndef CONFIG_OMAP34XX
 638                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
 639                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
 640                         omap_hsmmc_prepare_data(mmc, data);
 641                         flags |= DE_ENABLE;
 642                 }
 643 #endif
 644         }
 645
 646         writel(cmd->cmdarg, &mmc_base->arg);
 647         udelay(20);             /* To fix "No status update" error on eMMC */
 648         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 649
 650         start = get_timer(0);
 651         do {
 652                 mmc_stat = readl(&mmc_base->stat);
 653                 if (get_timer(start) > MAX_RETRY_MS) {
 654                         printf("%s : timeout: No status update\n", __func__);
 655                         return -ETIMEDOUT;
 656                 }
 657         } while (!mmc_stat);
 658
 659         if ((mmc_stat & IE_CTO) != 0) {
 660                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 661                 return -ETIMEDOUT;
 662         } else if ((mmc_stat & ERRI_MASK) != 0)
 663                 return -1;
 664
 665         if (mmc_stat & CC_MASK) {
 666                 writel(CC_MASK, &mmc_base->stat);
 667                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 668                         if (cmd->resp_type & MMC_RSP_136) {
 669                                 /* response type 2 */
 670                                 cmd->response[3] = readl(&mmc_base->rsp10);
 671                                 cmd->response[2] = readl(&mmc_base->rsp32);
 672                                 cmd->response[1] = readl(&mmc_base->rsp54);
 673                                 cmd->response[0] = readl(&mmc_base->rsp76);
 674                         } else
 675                                 /* response types 1, 1b, 3, 4, 5, 6 */
 676                                 cmd->response[0] = readl(&mmc_base->rsp10);
 677                 }
 678         }
 679
 680 #ifndef CONFIG_OMAP34XX
 681         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
 682             !mmc_is_tuning_cmd(cmd->cmdidx)) {
 683                 u32 sz_mb, timeout;
 684
 685                 if (mmc_stat & IE_ADMAE) {
 686                         omap_hsmmc_dma_cleanup(mmc);
 687                         return -EIO;
 688                 }
 689
 690                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
 691                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
 692                 if (timeout < MAX_RETRY_MS)
 693                         timeout = MAX_RETRY_MS;
 694
 695                 start = get_timer(0);
 696                 do {
 697                         mmc_stat = readl(&mmc_base->stat);
 698                         if (mmc_stat & TC_MASK) {
 699                                 writel(readl(&mmc_base->stat) | TC_MASK,
 700                                        &mmc_base->stat);
 701                                 break;
 702                         }
 703                         if (get_timer(start) > timeout) {
 704                                 printf("%s : DMA timeout: No status update\n",
 705                                        __func__);
 706                                 return -ETIMEDOUT;
 707                         }
 708                 } while (1);
 709
 710                 omap_hsmmc_dma_cleanup(mmc);
 711                 return 0;
 712         }
 713 #endif
 714
 715         if (data && (data->flags & MMC_DATA_READ)) {
 716                 mmc_read_data(mmc_base, data->dest,
 717                                 data->blocksize * data->blocks);
 718         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 719                 mmc_write_data(mmc_base, data->src,
 720                                 data->blocksize * data->blocks);
 721         }
 722         return 0;
 723 }
 724
 725 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 726 {
 727         unsigned int *output_buf = (unsigned int *)buf;
 728         unsigned int mmc_stat;
 729         unsigned int count;
 730
 731         /*
 732          * Start Polled Read
 733          */
 734         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 735         count /= 4;
 736
 737         while (size) {
 738                 ulong start = get_timer(0);
 739                 do {
 740                         mmc_stat = readl(&mmc_base->stat);
 741                         if (get_timer(0) - start > MAX_RETRY_MS) {
 742                                 printf("%s: timedout waiting for status!\n",
 743                                                 __func__);
 744                                 return -ETIMEDOUT;
 745                         }
 746                 } while (mmc_stat == 0);
 747
 748                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 749                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 750
 751                 if ((mmc_stat & ERRI_MASK) != 0)
 752                         return 1;
 753
 754                 if (mmc_stat & BRR_MASK) {
 755                         unsigned int k;
 756
 757                         writel(readl(&mmc_base->stat) | BRR_MASK,
 758                                 &mmc_base->stat);
 759                         for (k = 0; k < count; k++) {
 760                                 *output_buf = readl(&mmc_base->data);
 761                                 output_buf++;
 762                         }
 763                         size -= (count*4);
 764                 }
 765
 766                 if (mmc_stat & BWR_MASK)
 767                         writel(readl(&mmc_base->stat) | BWR_MASK,
 768                                 &mmc_base->stat);
 769
 770                 if (mmc_stat & TC_MASK) {
 771                         writel(readl(&mmc_base->stat) | TC_MASK,
 772                                 &mmc_base->stat);
 773                         break;
 774                 }
 775         }
 776         return 0;
 777 }
 778
 779 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 780                                 unsigned int size)
 781 {
 782         unsigned int *input_buf = (unsigned int *)buf;
 783         unsigned int mmc_stat;
 784         unsigned int count;
 785
 786         /*
 787          * Start Polled Write
 788          */
 789         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 790         count /= 4;
 791
 792         while (size) {
 793                 ulong start = get_timer(0);
 794                 do {
 795                         mmc_stat = readl(&mmc_base->stat);
 796                         if (get_timer(0) - start > MAX_RETRY_MS) {
 797                                 printf("%s: timedout waiting for status!\n",
 798                                                 __func__);
 799                                 return -ETIMEDOUT;
 800                         }
 801                 } while (mmc_stat == 0);
 802
 803                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 804                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 805
 806                 if ((mmc_stat & ERRI_MASK) != 0)
 807                         return 1;
 808
 809                 if (mmc_stat & BWR_MASK) {
 810                         unsigned int k;
 811
 812                         writel(readl(&mmc_base->stat) | BWR_MASK,
 813                                         &mmc_base->stat);
 814                         for (k = 0; k < count; k++) {
 815                                 writel(*input_buf, &mmc_base->data);
 816                                 input_buf++;
 817                         }
 818                         size -= (count*4);
 819                 }
 820
 821                 if (mmc_stat & BRR_MASK)
 822                         writel(readl(&mmc_base->stat) | BRR_MASK,
 823                                 &mmc_base->stat);
 824
 825                 if (mmc_stat & TC_MASK) {
 826                         writel(readl(&mmc_base->stat) | TC_MASK,
 827                                 &mmc_base->stat);
 828                         break;
 829                 }
 830         }
 831         return 0;
 832 }
 833
 834 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
 835 {
 836         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
 837 }
 838
 839 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
 840 {
 841         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 842 }
 843
 844 static void omap_hsmmc_set_clock(struct mmc *mmc)
 845 {
 846         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 847         struct hsmmc *mmc_base;
 848         unsigned int dsor = 0;
 849         ulong start;
 850
 851         mmc_base = priv->base_addr;
 852         omap_hsmmc_stop_clock(mmc_base);
 853
 854         /* TODO: Is setting DTO required here? */
 855         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
 856                     (ICE_STOP | DTO_15THDTO));
 857
 858         if (mmc->clock != 0) {
 859                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
 860                 if (dsor > CLKD_MAX)
 861                         dsor = CLKD_MAX;
 862         } else {
 863                 dsor = CLKD_MAX;
 864         }
 865
 866         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 867                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 868
 869         start = get_timer(0);
 870         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 871                 if (get_timer(0) - start > MAX_RETRY_MS) {
 872                         printf("%s: timedout waiting for ics!\n", __func__);
 873                         return;
 874                 }
 875         }
 876
 877         priv->clock = mmc->clock;
 878         omap_hsmmc_start_clock(mmc_base);
 879 }
 880
 881 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
 882 {
 883         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 884         struct hsmmc *mmc_base;
 885
 886         mmc_base = priv->base_addr;
 887         /* configue bus width */
 888         switch (mmc->bus_width) {
 889         case 8:
 890                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 891                         &mmc_base->con);
 892                 break;
 893
 894         case 4:
 895                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 896                         &mmc_base->con);
 897                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 898                         &mmc_base->hctl);
 899                 break;
 900
 901         case 1:
 902         default:
 903                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 904                         &mmc_base->con);
 905                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 906                         &mmc_base->hctl);
 907                 break;
 908         }
 909
 910         priv->bus_width = mmc->bus_width;
 911 }
 912
 913 #if !CONFIG_IS_ENABLED(DM_MMC)
 914 static int omap_hsmmc_set_ios(struct mmc *mmc)
 915 {
 916         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 917 #else
 918 static int omap_hsmmc_set_ios(struct udevice *dev)
 919 {
 920         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 921         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 922         struct mmc *mmc = upriv->mmc;
 923 #endif
 924
 925         if (priv->bus_width != mmc->bus_width)
 926                 omap_hsmmc_set_bus_width(mmc);
 927
 928         if (priv->clock != mmc->clock)
 929                 omap_hsmmc_set_clock(mmc);
 930
 931         return 0;
 932 }
 933
 934 #ifdef OMAP_HSMMC_USE_GPIO
 935 #if CONFIG_IS_ENABLED(DM_MMC)
 936 static int omap_hsmmc_getcd(struct udevice *dev)
 937 {
 938         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 939         int value;
 940
 941         value = dm_gpio_get_value(&priv->cd_gpio);
 942         /* if no CD return as 1 */
 943         if (value < 0)
 944                 return 1;
 945
 946         if (priv->cd_inverted)
 947                 return !value;
 948         return value;
 949 }
 950
 951 static int omap_hsmmc_getwp(struct udevice *dev)
 952 {
 953         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 954         int value;
 955
 956         value = dm_gpio_get_value(&priv->wp_gpio);
 957         /* if no WP return as 0 */
 958         if (value < 0)
 959                 return 0;
 960         return value;
 961 }
 962 #else
 963 static int omap_hsmmc_getcd(struct mmc *mmc)
 964 {
 965         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 966         int cd_gpio;
 967
 968         /* if no CD return as 1 */
 969         cd_gpio = priv->cd_gpio;
 970         if (cd_gpio < 0)
 971                 return 1;
 972
 973         /* NOTE: assumes card detect signal is active-low */
 974         return !gpio_get_value(cd_gpio);
 975 }
 976
 977 static int omap_hsmmc_getwp(struct mmc *mmc)
 978 {
 979         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 980         int wp_gpio;
 981
 982         /* if no WP return as 0 */
 983         wp_gpio = priv->wp_gpio;
 984         if (wp_gpio < 0)
 985                 return 0;
 986
 987         /* NOTE: assumes write protect signal is active-high */
 988         return gpio_get_value(wp_gpio);
 989 }
 990 #endif
 991 #endif
 992
 993 #if CONFIG_IS_ENABLED(DM_MMC)
 994 static const struct dm_mmc_ops omap_hsmmc_ops = {
 995         .send_cmd       = omap_hsmmc_send_cmd,
 996         .set_ios        = omap_hsmmc_set_ios,
 997 #ifdef OMAP_HSMMC_USE_GPIO
 998         .get_cd         = omap_hsmmc_getcd,
 999         .get_wp         = omap_hsmmc_getwp,
1000 #endif
1001 };
1002 #else
1003 static const struct mmc_ops omap_hsmmc_ops = {
1004         .send_cmd       = omap_hsmmc_send_cmd,
1005         .set_ios        = omap_hsmmc_set_ios,
1006         .init           = omap_hsmmc_init_setup,
1007 #ifdef OMAP_HSMMC_USE_GPIO
1008         .getcd          = omap_hsmmc_getcd,
1009         .getwp          = omap_hsmmc_getwp,
1010 #endif
1011 };
1012 #endif
1013
1014 #if !CONFIG_IS_ENABLED(DM_MMC)
1015 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1016                 int wp_gpio)
1017 {
1018         struct mmc *mmc;
1019         struct omap_hsmmc_data *priv;
1020         struct mmc_config *cfg;
1021         uint host_caps_val;
1022
1023         priv = malloc(sizeof(*priv));
1024         if (priv == NULL)
1025                 return -1;
1026
1027         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1028
1029         switch (dev_index) {
1030         case 0:
1031                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1032                 break;
1033 #ifdef OMAP_HSMMC2_BASE
1034         case 1:
1035                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1036 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1037         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1038         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1039                 defined(CONFIG_HSMMC2_8BIT)
1040                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1041                 host_caps_val |= MMC_MODE_8BIT;
1042 #endif
1043                 break;
1044 #endif
1045 #ifdef OMAP_HSMMC3_BASE
1046         case 2:
1047                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1048 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1049                 /* Enable 8-bit interface for eMMC on DRA7XX */
1050                 host_caps_val |= MMC_MODE_8BIT;
1051 #endif
1052                 break;
1053 #endif
1054         default:
1055                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1056                 return 1;
1057         }
1058 #ifdef OMAP_HSMMC_USE_GPIO
1059         /* on error gpio values are set to -1, which is what we want */
1060         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1061         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1062 #endif
1063
1064         cfg = &priv->cfg;
1065
1066         cfg->name = "OMAP SD/MMC";
1067         cfg->ops = &omap_hsmmc_ops;
1068
1069         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1070         cfg->host_caps = host_caps_val & ~host_caps_mask;
1071
1072         cfg->f_min = 400000;
1073
1074         if (f_max != 0)
1075                 cfg->f_max = f_max;
1076         else {
1077                 if (cfg->host_caps & MMC_MODE_HS) {
1078                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1079                                 cfg->f_max = 52000000;
1080                         else
1081                                 cfg->f_max = 26000000;
1082                 } else
1083                         cfg->f_max = 20000000;
1084         }
1085
1086         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1087
1088 #if defined(CONFIG_OMAP34XX)
1089         /*
1090          * Silicon revs 2.1 and older do not support multiblock transfers.
1091          */
1092         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1093                 cfg->b_max = 1;
1094 #endif
1095         mmc = mmc_create(cfg, priv);
1096         if (mmc == NULL)
1097                 return -1;
1098
1099         return 0;
1100 }
1101 #else
1102 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1103 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1104 {
1105         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1106         struct mmc_config *cfg = &plat->cfg;
1107         const void *fdt = gd->fdt_blob;
1108         int node = dev_of_offset(dev);
1109         int val;
1110
1111         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1112                                       sizeof(struct hsmmc *),
1113                                       MAP_NOCACHE);
1114
1115         cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1116         val = fdtdec_get_int(fdt, node, "bus-width", -1);
1117         if (val < 0) {
1118                 printf("error: bus-width property missing\n");
1119                 return -ENOENT;
1120         }
1121
1122         switch (val) {
1123         case 0x8:
1124                 cfg->host_caps |= MMC_MODE_8BIT;
1125         case 0x4:
1126                 cfg->host_caps |= MMC_MODE_4BIT;
1127                 break;
1128         default:
1129                 printf("error: invalid bus-width property\n");
1130                 return -ENOENT;
1131         }
1132
1133         cfg->f_min = 400000;
1134         cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1135         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1136         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1137         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1138                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1139         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1140                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1141
1142 #ifdef OMAP_HSMMC_USE_GPIO
1143         plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1144 #endif
1145
1146         return 0;
1147 }
1148 #endif
1149
1150 #ifdef CONFIG_BLK
1151
1152 static int omap_hsmmc_bind(struct udevice *dev)
1153 {
1154         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1155
1156         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1157 }
1158 #endif
1159 static int omap_hsmmc_probe(struct udevice *dev)
1160 {
1161         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1162         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1163         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1164         struct mmc_config *cfg = &plat->cfg;
1165         struct mmc *mmc;
1166
1167         cfg->name = "OMAP SD/MMC";
1168         priv->base_addr = plat->base_addr;
1169 #ifdef OMAP_HSMMC_USE_GPIO
1170         priv->cd_inverted = plat->cd_inverted;
1171 #endif
1172
1173 #ifdef CONFIG_BLK
1174         mmc = &plat->mmc;
1175 #else
1176         mmc = mmc_create(cfg, priv);
1177         if (mmc == NULL)
1178                 return -1;
1179 #endif
1180
1181 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1182         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1183         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1184 #endif
1185
1186         mmc->dev = dev;
1187         upriv->mmc = mmc;
1188
1189         return omap_hsmmc_init_setup(mmc);
1190 }
1191
1192 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1193 static const struct udevice_id omap_hsmmc_ids[] = {
1194         { .compatible = "ti,omap3-hsmmc" },
1195         { .compatible = "ti,omap4-hsmmc" },
1196         { .compatible = "ti,am33xx-hsmmc" },
1197         { }
1198 };
1199 #endif
1200
1201 U_BOOT_DRIVER(omap_hsmmc) = {
1202         .name   = "omap_hsmmc",
1203         .id     = UCLASS_MMC,
1204 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1205         .of_match = omap_hsmmc_ids,
1206         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1207         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1208 #endif
1209 #ifdef CONFIG_BLK
1210         .bind = omap_hsmmc_bind,
1211 #endif
1212         .ops = &omap_hsmmc_ops,
1213         .probe  = omap_hsmmc_probe,
1214         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1215         .flags  = DM_FLAG_PRE_RELOC,
1216 };
1217 #endif