git.sur5r.net Git - u-boot/blob - drivers/mmc/sdhci.c

   1 /*
   2  * Copyright 2011, Marvell Semiconductor Inc.
   3  * Lei Wen <leiwen@marvell.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  *
   7  * Back ported to the 8xx platform (from the 8260 platform) by
   8  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <malloc.h>
  14 #include <mmc.h>
  15 #include <sdhci.h>
  16
  17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  19 #else
  20 void *aligned_buffer;
  21 #endif
  22
  23 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  24 {
  25         unsigned long timeout;
  26
  27         /* Wait max 100 ms */
  28         timeout = 100;
  29         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  30         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  31                 if (timeout == 0) {
  32                         printf("%s: Reset 0x%x never completed.\n",
  33                                __func__, (int)mask);
  34                         return;
  35                 }
  36                 timeout--;
  37                 udelay(1000);
  38         }
  39 }
  40
  41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  42 {
  43         int i;
  44         if (cmd->resp_type & MMC_RSP_136) {
  45                 /* CRC is stripped so we need to do some shifting. */
  46                 for (i = 0; i < 4; i++) {
  47                         cmd->response[i] = sdhci_readl(host,
  48                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  49                         if (i != 3)
  50                                 cmd->response[i] |= sdhci_readb(host,
  51                                                 SDHCI_RESPONSE + (3-i)*4-1);
  52                 }
  53         } else {
  54                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  55         }
  56 }
  57
  58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  59 {
  60         int i;
  61         char *offs;
  62         for (i = 0; i < data->blocksize; i += 4) {
  63                 offs = data->dest + i;
  64                 if (data->flags == MMC_DATA_READ)
  65                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  66                 else
  67                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  68         }
  69 }
  70
  71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  72                                 unsigned int start_addr)
  73 {
  74         unsigned int stat, rdy, mask, timeout, block = 0;
  75 #ifdef CONFIG_MMC_SDHCI_SDMA
  76         unsigned char ctrl;
  77         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  78         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  79         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  80 #endif
  81
  82         timeout = 1000000;
  83         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  84         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  85         do {
  86                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
  87                 if (stat & SDHCI_INT_ERROR) {
  88                         printf("%s: Error detected in status(0x%X)!\n",
  89                                __func__, stat);
  90                         return -EIO;
  91                 }
  92                 if (stat & rdy) {
  93                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  94                                 continue;
  95                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  96                         sdhci_transfer_pio(host, data);
  97                         data->dest += data->blocksize;
  98                         if (++block >= data->blocks)
  99                                 break;
 100                 }
 101 #ifdef CONFIG_MMC_SDHCI_SDMA
 102                 if (stat & SDHCI_INT_DMA_END) {
 103                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 104                         start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 105                         start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 106                         sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 107                 }
 108 #endif
 109                 if (timeout-- > 0)
 110                         udelay(10);
 111                 else {
 112                         printf("%s: Transfer data timeout\n", __func__);
 113                         return -ETIMEDOUT;
 114                 }
 115         } while (!(stat & SDHCI_INT_DATA_END));
 116         return 0;
 117 }
 118
 119 /*
 120  * No command will be sent by driver if card is busy, so driver must wait
 121  * for card ready state.
 122  * Every time when card is busy after timeout then (last) timeout value will be
 123  * increased twice but only if it doesn't exceed global defined maximum.
 124  * Each function call will use last timeout value.
 125  */
 126 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 127 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 128 #define SDHCI_READ_STATUS_TIMEOUT               1000
 129
 130 #ifdef CONFIG_DM_MMC_OPS
 131 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 132                               struct mmc_data *data)
 133 {
 134         struct mmc *mmc = mmc_get_mmc_dev(dev);
 135
 136 #else
 137 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 138                               struct mmc_data *data)
 139 {
 140 #endif
 141         struct sdhci_host *host = mmc->priv;
 142         unsigned int stat = 0;
 143         int ret = 0;
 144         int trans_bytes = 0, is_aligned = 1;
 145         u32 mask, flags, mode;
 146         unsigned int time = 0, start_addr = 0;
 147         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 148         unsigned start = get_timer(0);
 149
 150         /* Timeout unit - ms */
 151         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 152
 153         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 154         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 155
 156         /* We shouldn't wait for data inihibit for stop commands, even
 157            though they might use busy signaling */
 158         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 159                 mask &= ~SDHCI_DATA_INHIBIT;
 160
 161         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 162                 if (time >= cmd_timeout) {
 163                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 164                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 165                                 cmd_timeout += cmd_timeout;
 166                                 printf("timeout increasing to: %u ms.\n",
 167                                        cmd_timeout);
 168                         } else {
 169                                 puts("timeout.\n");
 170                                 return -ECOMM;
 171                         }
 172                 }
 173                 time++;
 174                 udelay(1000);
 175         }
 176
 177         mask = SDHCI_INT_RESPONSE;
 178         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 179                 flags = SDHCI_CMD_RESP_NONE;
 180         else if (cmd->resp_type & MMC_RSP_136)
 181                 flags = SDHCI_CMD_RESP_LONG;
 182         else if (cmd->resp_type & MMC_RSP_BUSY) {
 183                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 184                 if (data)
 185                         mask |= SDHCI_INT_DATA_END;
 186         } else
 187                 flags = SDHCI_CMD_RESP_SHORT;
 188
 189         if (cmd->resp_type & MMC_RSP_CRC)
 190                 flags |= SDHCI_CMD_CRC;
 191         if (cmd->resp_type & MMC_RSP_OPCODE)
 192                 flags |= SDHCI_CMD_INDEX;
 193         if (data)
 194                 flags |= SDHCI_CMD_DATA;
 195
 196         /* Set Transfer mode regarding to data flag */
 197         if (data != 0) {
 198                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 199                 mode = SDHCI_TRNS_BLK_CNT_EN;
 200                 trans_bytes = data->blocks * data->blocksize;
 201                 if (data->blocks > 1)
 202                         mode |= SDHCI_TRNS_MULTI;
 203
 204                 if (data->flags == MMC_DATA_READ)
 205                         mode |= SDHCI_TRNS_READ;
 206
 207 #ifdef CONFIG_MMC_SDHCI_SDMA
 208                 if (data->flags == MMC_DATA_READ)
 209                         start_addr = (unsigned long)data->dest;
 210                 else
 211                         start_addr = (unsigned long)data->src;
 212                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 213                                 (start_addr & 0x7) != 0x0) {
 214                         is_aligned = 0;
 215                         start_addr = (unsigned long)aligned_buffer;
 216                         if (data->flags != MMC_DATA_READ)
 217                                 memcpy(aligned_buffer, data->src, trans_bytes);
 218                 }
 219
 220 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 221                 /*
 222                  * Always use this bounce-buffer when
 223                  * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
 224                  */
 225                 is_aligned = 0;
 226                 start_addr = (unsigned long)aligned_buffer;
 227                 if (data->flags != MMC_DATA_READ)
 228                         memcpy(aligned_buffer, data->src, trans_bytes);
 229 #endif
 230
 231                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 232                 mode |= SDHCI_TRNS_DMA;
 233 #endif
 234                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 235                                 data->blocksize),
 236                                 SDHCI_BLOCK_SIZE);
 237                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 238                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 239         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 240                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 241         }
 242
 243         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 244 #ifdef CONFIG_MMC_SDHCI_SDMA
 245         trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
 246         flush_cache(start_addr, trans_bytes);
 247 #endif
 248         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 249         start = get_timer(0);
 250         do {
 251                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 252                 if (stat & SDHCI_INT_ERROR)
 253                         break;
 254
 255                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 256                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 257                                 return 0;
 258                         } else {
 259                                 printf("%s: Timeout for status update!\n",
 260                                        __func__);
 261                                 return -ETIMEDOUT;
 262                         }
 263                 }
 264         } while ((stat & mask) != mask);
 265
 266         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 267                 sdhci_cmd_done(host, cmd);
 268                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 269         } else
 270                 ret = -1;
 271
 272         if (!ret && data)
 273                 ret = sdhci_transfer_data(host, data, start_addr);
 274
 275         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 276                 udelay(1000);
 277
 278         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 279         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 280         if (!ret) {
 281                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 282                                 !is_aligned && (data->flags == MMC_DATA_READ))
 283                         memcpy(data->dest, aligned_buffer, trans_bytes);
 284                 return 0;
 285         }
 286
 287         sdhci_reset(host, SDHCI_RESET_CMD);
 288         sdhci_reset(host, SDHCI_RESET_DATA);
 289         if (stat & SDHCI_INT_TIMEOUT)
 290                 return -ETIMEDOUT;
 291         else
 292                 return -ECOMM;
 293 }
 294
 295 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 296 {
 297         struct sdhci_host *host = mmc->priv;
 298         unsigned int div, clk = 0, timeout;
 299
 300         /* Wait max 20 ms */
 301         timeout = 200;
 302         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 303                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 304                 if (timeout == 0) {
 305                         printf("%s: Timeout to wait cmd & data inhibit\n",
 306                                __func__);
 307                         return -EBUSY;
 308                 }
 309
 310                 timeout--;
 311                 udelay(100);
 312         }
 313
 314         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 315
 316         if (clock == 0)
 317                 return 0;
 318
 319         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 320                 /*
 321                  * Check if the Host Controller supports Programmable Clock
 322                  * Mode.
 323                  */
 324                 if (host->clk_mul) {
 325                         for (div = 1; div <= 1024; div++) {
 326                                 if ((host->max_clk * host->clk_mul / div)
 327                                         <= clock)
 328                                         break;
 329                         }
 330
 331                         /*
 332                          * Set Programmable Clock Mode in the Clock
 333                          * Control register.
 334                          */
 335                         clk = SDHCI_PROG_CLOCK_MODE;
 336                         div--;
 337                 } else {
 338                         /* Version 3.00 divisors must be a multiple of 2. */
 339                         if (host->max_clk <= clock) {
 340                                 div = 1;
 341                         } else {
 342                                 for (div = 2;
 343                                      div < SDHCI_MAX_DIV_SPEC_300;
 344                                      div += 2) {
 345                                         if ((host->max_clk / div) <= clock)
 346                                                 break;
 347                                 }
 348                         }
 349                         div >>= 1;
 350                 }
 351         } else {
 352                 /* Version 2.00 divisors must be a power of 2. */
 353                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 354                         if ((host->max_clk / div) <= clock)
 355                                 break;
 356                 }
 357                 div >>= 1;
 358         }
 359
 360         if (host->ops && host->ops->set_clock)
 361                 host->ops->set_clock(host, div);
 362
 363         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 364         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 365                 << SDHCI_DIVIDER_HI_SHIFT;
 366         clk |= SDHCI_CLOCK_INT_EN;
 367         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 368
 369         /* Wait max 20 ms */
 370         timeout = 20;
 371         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 372                 & SDHCI_CLOCK_INT_STABLE)) {
 373                 if (timeout == 0) {
 374                         printf("%s: Internal clock never stabilised.\n",
 375                                __func__);
 376                         return -EBUSY;
 377                 }
 378                 timeout--;
 379                 udelay(1000);
 380         }
 381
 382         clk |= SDHCI_CLOCK_CARD_EN;
 383         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 384         return 0;
 385 }
 386
 387 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 388 {
 389         u8 pwr = 0;
 390
 391         if (power != (unsigned short)-1) {
 392                 switch (1 << power) {
 393                 case MMC_VDD_165_195:
 394                         pwr = SDHCI_POWER_180;
 395                         break;
 396                 case MMC_VDD_29_30:
 397                 case MMC_VDD_30_31:
 398                         pwr = SDHCI_POWER_300;
 399                         break;
 400                 case MMC_VDD_32_33:
 401                 case MMC_VDD_33_34:
 402                         pwr = SDHCI_POWER_330;
 403                         break;
 404                 }
 405         }
 406
 407         if (pwr == 0) {
 408                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 409                 return;
 410         }
 411
 412         pwr |= SDHCI_POWER_ON;
 413
 414         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 415 }
 416
 417 #ifdef CONFIG_DM_MMC_OPS
 418 static int sdhci_set_ios(struct udevice *dev)
 419 {
 420         struct mmc *mmc = mmc_get_mmc_dev(dev);
 421 #else
 422 static int sdhci_set_ios(struct mmc *mmc)
 423 {
 424 #endif
 425         u32 ctrl;
 426         struct sdhci_host *host = mmc->priv;
 427
 428         if (host->ops && host->ops->set_control_reg)
 429                 host->ops->set_control_reg(host);
 430
 431         if (mmc->clock != host->clock)
 432                 sdhci_set_clock(mmc, mmc->clock);
 433
 434         /* Set bus width */
 435         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 436         if (mmc->bus_width == 8) {
 437                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 438                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 439                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 440                         ctrl |= SDHCI_CTRL_8BITBUS;
 441         } else {
 442                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 443                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 444                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 445                 if (mmc->bus_width == 4)
 446                         ctrl |= SDHCI_CTRL_4BITBUS;
 447                 else
 448                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 449         }
 450
 451         if (mmc->clock > 26000000)
 452                 ctrl |= SDHCI_CTRL_HISPD;
 453         else
 454                 ctrl &= ~SDHCI_CTRL_HISPD;
 455
 456         if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
 457                 ctrl &= ~SDHCI_CTRL_HISPD;
 458
 459         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 460
 461         return 0;
 462 }
 463
 464 static int sdhci_init(struct mmc *mmc)
 465 {
 466         struct sdhci_host *host = mmc->priv;
 467
 468         sdhci_reset(host, SDHCI_RESET_ALL);
 469
 470         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 471                 aligned_buffer = memalign(8, 512*1024);
 472                 if (!aligned_buffer) {
 473                         printf("%s: Aligned buffer alloc failed!!!\n",
 474                                __func__);
 475                         return -ENOMEM;
 476                 }
 477         }
 478
 479         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 480
 481         if (host->ops && host->ops->get_cd)
 482                 host->ops->get_cd(host);
 483
 484         /* Enable only interrupts served by the SD controller */
 485         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 486                      SDHCI_INT_ENABLE);
 487         /* Mask all sdhci interrupt sources */
 488         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 489
 490         return 0;
 491 }
 492
 493 #ifdef CONFIG_DM_MMC_OPS
 494 int sdhci_probe(struct udevice *dev)
 495 {
 496         struct mmc *mmc = mmc_get_mmc_dev(dev);
 497
 498         return sdhci_init(mmc);
 499 }
 500
 501 const struct dm_mmc_ops sdhci_ops = {
 502         .send_cmd       = sdhci_send_command,
 503         .set_ios        = sdhci_set_ios,
 504 };
 505 #else
 506 static const struct mmc_ops sdhci_ops = {
 507         .send_cmd       = sdhci_send_command,
 508         .set_ios        = sdhci_set_ios,
 509         .init           = sdhci_init,
 510 };
 511 #endif
 512
 513 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 514                 u32 f_max, u32 f_min)
 515 {
 516         u32 caps, caps_1;
 517
 518         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 519
 520 #ifdef CONFIG_MMC_SDHCI_SDMA
 521         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 522                 printf("%s: Your controller doesn't support SDMA!!\n",
 523                        __func__);
 524                 return -EINVAL;
 525         }
 526 #endif
 527         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 528                 host->version =
 529                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 530         else
 531                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 532
 533         cfg->name = host->name;
 534 #ifndef CONFIG_DM_MMC_OPS
 535         cfg->ops = &sdhci_ops;
 536 #endif
 537         if (host->max_clk == 0) {
 538                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 539                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 540                                 SDHCI_CLOCK_BASE_SHIFT;
 541                 else
 542                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 543                                 SDHCI_CLOCK_BASE_SHIFT;
 544                 host->max_clk *= 1000000;
 545         }
 546         if (host->max_clk == 0) {
 547                 printf("%s: Hardware doesn't specify base clock frequency\n",
 548                        __func__);
 549                 return -EINVAL;
 550         }
 551         if (f_max && (f_max < host->max_clk))
 552                 cfg->f_max = f_max;
 553         else
 554                 cfg->f_max = host->max_clk;
 555         if (f_min)
 556                 cfg->f_min = f_min;
 557         else {
 558                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 559                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 560                 else
 561                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 562         }
 563         cfg->voltages = 0;
 564         if (caps & SDHCI_CAN_VDD_330)
 565                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 566         if (caps & SDHCI_CAN_VDD_300)
 567                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 568         if (caps & SDHCI_CAN_VDD_180)
 569                 cfg->voltages |= MMC_VDD_165_195;
 570
 571         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 572                 cfg->voltages |= host->voltages;
 573
 574         cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 575
 576         /* Since Host Controller Version3.0 */
 577         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 578                 if (!(caps & SDHCI_CAN_DO_8BIT))
 579                         cfg->host_caps &= ~MMC_MODE_8BIT;
 580
 581                 /* Find out whether clock multiplier is supported */
 582                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 583                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 584                                 SDHCI_CLOCK_MUL_SHIFT;
 585         }
 586
 587         if (host->host_caps)
 588                 cfg->host_caps |= host->host_caps;
 589
 590         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 591
 592         return 0;
 593 }
 594
 595 #ifdef CONFIG_BLK
 596 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 597 {
 598         return mmc_bind(dev, mmc, cfg);
 599 }
 600 #else
 601 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 602 {
 603         int ret;
 604
 605         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 606         if (ret)
 607                 return ret;
 608
 609         host->mmc = mmc_create(&host->cfg, host);
 610         if (host->mmc == NULL) {
 611                 printf("%s: mmc create fail!\n", __func__);
 612                 return -ENOMEM;
 613         }
 614
 615         return 0;
 616 }
 617 #endif