git.sur5r.net Git - u-boot/blob - drivers/mmc/socfpga_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch/clock_manager.h>
   8 #include <asm/arch/system_manager.h>
   9 #include <dm.h>
  10 #include <dwmmc.h>
  11 #include <errno.h>
  12 #include <fdtdec.h>
  13 #include <linux/libfdt.h>
  14 #include <linux/err.h>
  15 #include <malloc.h>
  16 #include <reset.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static const struct socfpga_clock_manager *clock_manager_base =
  21                 (void *)SOCFPGA_CLKMGR_ADDRESS;
  22 static const struct socfpga_system_manager *system_manager_base =
  23                 (void *)SOCFPGA_SYSMGR_ADDRESS;
  24
  25 struct socfpga_dwmci_plat {
  26         struct mmc_config cfg;
  27         struct mmc mmc;
  28 };
  29
  30 /* socfpga implmentation specific driver private data */
  31 struct dwmci_socfpga_priv_data {
  32         struct dwmci_host       host;
  33         unsigned int            drvsel;
  34         unsigned int            smplsel;
  35 };
  36
  37 static void socfpga_dwmci_reset(struct udevice *dev)
  38 {
  39         struct reset_ctl_bulk reset_bulk;
  40         int ret;
  41
  42         ret = reset_get_bulk(dev, &reset_bulk);
  43         if (ret) {
  44                 dev_warn(dev, "Can't get reset: %d\n", ret);
  45                 return;
  46         }
  47
  48         reset_deassert_bulk(&reset_bulk);
  49 }
  50
  51 static void socfpga_dwmci_clksel(struct dwmci_host *host)
  52 {
  53         struct dwmci_socfpga_priv_data *priv = host->priv;
  54         u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
  55                          ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
  56
  57         /* Disable SDMMC clock. */
  58         clrbits_le32(&clock_manager_base->per_pll.en,
  59                 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  60
  61         debug("%s: drvsel %d smplsel %d\n", __func__,
  62               priv->drvsel, priv->smplsel);
  63         writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
  64
  65         debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  66                 readl(&system_manager_base->sdmmcgrp_ctrl));
  67
  68         /* Enable SDMMC clock */
  69         setbits_le32(&clock_manager_base->per_pll.en,
  70                 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  71 }
  72
  73 static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
  74 {
  75         /* FIXME: probe from DT eventually too/ */
  76         const unsigned long clk = cm_get_mmc_controller_clk_hz();
  77
  78         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  79         struct dwmci_host *host = &priv->host;
  80         int fifo_depth;
  81
  82         if (clk == 0) {
  83                 printf("DWMMC: MMC clock is zero!");
  84                 return -EINVAL;
  85         }
  86
  87         fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  88                                     "fifo-depth", 0);
  89         if (fifo_depth < 0) {
  90                 printf("DWMMC: Can't get FIFO depth\n");
  91                 return -EINVAL;
  92         }
  93
  94         host->name = dev->name;
  95         host->ioaddr = (void *)devfdt_get_addr(dev);
  96         host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  97                                         "bus-width", 4);
  98         host->clksel = socfpga_dwmci_clksel;
  99
 100         /*
 101          * TODO(sjg@chromium.org): Remove the need for this hack.
 102          * We only have one dwmmc block on gen5 SoCFPGA.
 103          */
 104         host->dev_index = 0;
 105         /* Fixed clock divide by 4 which due to the SDMMC wrapper */
 106         host->bus_hz = clk;
 107         host->fifoth_val = MSIZE(0x2) |
 108                 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
 109         priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 110                                        "drvsel", 3);
 111         priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
 112                                         "smplsel", 0);
 113         host->priv = priv;
 114
 115         return 0;
 116 }
 117
 118 static int socfpga_dwmmc_probe(struct udevice *dev)
 119 {
 120 #ifdef CONFIG_BLK
 121         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 122 #endif
 123         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 124         struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
 125         struct dwmci_host *host = &priv->host;
 126
 127         socfpga_dwmci_reset(dev);
 128
 129 #ifdef CONFIG_BLK
 130         dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
 131         host->mmc = &plat->mmc;
 132 #else
 133         int ret;
 134
 135         ret = add_dwmci(host, host->bus_hz, 400000);
 136         if (ret)
 137                 return ret;
 138 #endif
 139         host->mmc->priv = &priv->host;
 140         upriv->mmc = host->mmc;
 141         host->mmc->dev = dev;
 142
 143         return dwmci_probe(dev);
 144 }
 145
 146 static int socfpga_dwmmc_bind(struct udevice *dev)
 147 {
 148 #ifdef CONFIG_BLK
 149         struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
 150         int ret;
 151
 152         ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
 153         if (ret)
 154                 return ret;
 155 #endif
 156
 157         return 0;
 158 }
 159
 160 static const struct udevice_id socfpga_dwmmc_ids[] = {
 161         { .compatible = "altr,socfpga-dw-mshc" },
 162         { }
 163 };
 164
 165 U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
 166         .name           = "socfpga_dwmmc",
 167         .id             = UCLASS_MMC,
 168         .of_match       = socfpga_dwmmc_ids,
 169         .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
 170         .ops            = &dm_dwmci_ops,
 171         .bind           = socfpga_dwmmc_bind,
 172         .probe          = socfpga_dwmmc_probe,
 173         .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
 174         .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
 175 };