git.sur5r.net Git - u-boot/blob - drivers/mmc/sunxi_mmc.c

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   4  * Aaron <leafy.myeh@allwinnertech.com>
   5  *
   6  * MMC driver for allwinner sunxi platform.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <malloc.h>
  14 #include <mmc.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc.h>
  20 #include <asm-generic/gpio.h>
  21
  22 struct sunxi_mmc_priv {
  23         unsigned mmc_no;
  24         uint32_t *mclkreg;
  25         unsigned fatal_err;
  26         struct sunxi_mmc *reg;
  27         struct mmc_config cfg;
  28 };
  29
  30 /* support 4 mmc hosts */
  31 struct sunxi_mmc_priv mmc_host[4];
  32
  33 static int sunxi_mmc_getcd_gpio(int sdc_no)
  34 {
  35         switch (sdc_no) {
  36         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  37         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  38         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  39         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  40         }
  41         return -EINVAL;
  42 }
  43
  44 static int mmc_resource_init(int sdc_no)
  45 {
  46         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  47         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  48         int cd_pin, ret = 0;
  49
  50         debug("init mmc %d resource\n", sdc_no);
  51
  52         switch (sdc_no) {
  53         case 0:
  54                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  55                 priv->mclkreg = &ccm->sd0_clk_cfg;
  56                 break;
  57         case 1:
  58                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  59                 priv->mclkreg = &ccm->sd1_clk_cfg;
  60                 break;
  61         case 2:
  62                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  63                 priv->mclkreg = &ccm->sd2_clk_cfg;
  64                 break;
  65         case 3:
  66                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  67                 priv->mclkreg = &ccm->sd3_clk_cfg;
  68                 break;
  69         default:
  70                 printf("Wrong mmc number %d\n", sdc_no);
  71                 return -1;
  72         }
  73         priv->mmc_no = sdc_no;
  74
  75         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  76         if (cd_pin >= 0) {
  77                 ret = gpio_request(cd_pin, "mmc_cd");
  78                 if (!ret) {
  79                         sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  80                         ret = gpio_direction_input(cd_pin);
  81                 }
  82         }
  83
  84         return ret;
  85 }
  86
  87 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
  88 {
  89         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
  90
  91         if (hz <= 24000000) {
  92                 pll = CCM_MMC_CTRL_OSCM24;
  93                 pll_hz = 24000000;
  94         } else {
  95 #ifdef CONFIG_MACH_SUN9I
  96                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
  97                 pll_hz = clock_get_pll4_periph0();
  98 #else
  99                 pll = CCM_MMC_CTRL_PLL6;
 100                 pll_hz = clock_get_pll6();
 101 #endif
 102         }
 103
 104         div = pll_hz / hz;
 105         if (pll_hz % hz)
 106                 div++;
 107
 108         n = 0;
 109         while (div > 16) {
 110                 n++;
 111                 div = (div + 1) / 2;
 112         }
 113
 114         if (n > 3) {
 115                 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
 116                        hz);
 117                 return -1;
 118         }
 119
 120         /* determine delays */
 121         if (hz <= 400000) {
 122                 oclk_dly = 0;
 123                 sclk_dly = 0;
 124         } else if (hz <= 25000000) {
 125                 oclk_dly = 0;
 126                 sclk_dly = 5;
 127 #ifdef CONFIG_MACH_SUN9I
 128         } else if (hz <= 50000000) {
 129                 oclk_dly = 5;
 130                 sclk_dly = 4;
 131         } else {
 132                 /* hz > 50000000 */
 133                 oclk_dly = 2;
 134                 sclk_dly = 4;
 135 #else
 136         } else if (hz <= 50000000) {
 137                 oclk_dly = 3;
 138                 sclk_dly = 4;
 139         } else {
 140                 /* hz > 50000000 */
 141                 oclk_dly = 1;
 142                 sclk_dly = 4;
 143 #endif
 144         }
 145
 146         writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
 147                CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 148                CCM_MMC_CTRL_M(div), priv->mclkreg);
 149
 150         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 151               priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
 152
 153         return 0;
 154 }
 155
 156 static int mmc_clk_io_on(int sdc_no)
 157 {
 158         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
 159         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 160
 161         debug("init mmc %d clock and io\n", sdc_no);
 162
 163         /* config ahb clock */
 164         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 165
 166 #ifdef CONFIG_SUNXI_GEN_SUN6I
 167         /* unassert reset */
 168         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 169 #endif
 170 #if defined(CONFIG_MACH_SUN9I)
 171         /* sun9i has a mmc-common module, also set the gate and reset there */
 172         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 173                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 174 #endif
 175
 176         return mmc_set_mod_clk(priv, 24000000);
 177 }
 178
 179 static int mmc_update_clk(struct mmc *mmc)
 180 {
 181         struct sunxi_mmc_priv *priv = mmc->priv;
 182         unsigned int cmd;
 183         unsigned timeout_msecs = 2000;
 184
 185         cmd = SUNXI_MMC_CMD_START |
 186               SUNXI_MMC_CMD_UPCLK_ONLY |
 187               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 188         writel(cmd, &priv->reg->cmd);
 189         while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
 190                 if (!timeout_msecs--)
 191                         return -1;
 192                 udelay(1000);
 193         }
 194
 195         /* clock update sets various irq status bits, clear these */
 196         writel(readl(&priv->reg->rint), &priv->reg->rint);
 197
 198         return 0;
 199 }
 200
 201 static int mmc_config_clock(struct mmc *mmc)
 202 {
 203         struct sunxi_mmc_priv *priv = mmc->priv;
 204         unsigned rval = readl(&priv->reg->clkcr);
 205
 206         /* Disable Clock */
 207         rval &= ~SUNXI_MMC_CLK_ENABLE;
 208         writel(rval, &priv->reg->clkcr);
 209         if (mmc_update_clk(mmc))
 210                 return -1;
 211
 212         /* Set mod_clk to new rate */
 213         if (mmc_set_mod_clk(priv, mmc->clock))
 214                 return -1;
 215
 216         /* Clear internal divider */
 217         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 218         writel(rval, &priv->reg->clkcr);
 219
 220         /* Re-enable Clock */
 221         rval |= SUNXI_MMC_CLK_ENABLE;
 222         writel(rval, &priv->reg->clkcr);
 223         if (mmc_update_clk(mmc))
 224                 return -1;
 225
 226         return 0;
 227 }
 228
 229 static int sunxi_mmc_set_ios(struct mmc *mmc)
 230 {
 231         struct sunxi_mmc_priv *priv = mmc->priv;
 232
 233         debug("set ios: bus_width: %x, clock: %d\n",
 234               mmc->bus_width, mmc->clock);
 235
 236         /* Change clock first */
 237         if (mmc->clock && mmc_config_clock(mmc) != 0) {
 238                 priv->fatal_err = 1;
 239                 return -EINVAL;
 240         }
 241
 242         /* Change bus width */
 243         if (mmc->bus_width == 8)
 244                 writel(0x2, &priv->reg->width);
 245         else if (mmc->bus_width == 4)
 246                 writel(0x1, &priv->reg->width);
 247         else
 248                 writel(0x0, &priv->reg->width);
 249
 250         return 0;
 251 }
 252
 253 static int sunxi_mmc_core_init(struct mmc *mmc)
 254 {
 255         struct sunxi_mmc_priv *priv = mmc->priv;
 256
 257         /* Reset controller */
 258         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 259         udelay(1000);
 260
 261         return 0;
 262 }
 263
 264 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 265 {
 266         struct sunxi_mmc_priv *priv = mmc->priv;
 267         const int reading = !!(data->flags & MMC_DATA_READ);
 268         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 269                                               SUNXI_MMC_STATUS_FIFO_FULL;
 270         unsigned i;
 271         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 272         unsigned byte_cnt = data->blocksize * data->blocks;
 273         unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
 274         if (timeout_usecs < 2000000)
 275                 timeout_usecs = 2000000;
 276
 277         /* Always read / write data through the CPU */
 278         setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 279
 280         for (i = 0; i < (byte_cnt >> 2); i++) {
 281                 while (readl(&priv->reg->status) & status_bit) {
 282                         if (!timeout_usecs--)
 283                                 return -1;
 284                         udelay(1);
 285                 }
 286
 287                 if (reading)
 288                         buff[i] = readl(&priv->reg->fifo);
 289                 else
 290                         writel(buff[i], &priv->reg->fifo);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
 297                          unsigned int done_bit, const char *what)
 298 {
 299         struct sunxi_mmc_priv *priv = mmc->priv;
 300         unsigned int status;
 301
 302         do {
 303                 status = readl(&priv->reg->rint);
 304                 if (!timeout_msecs-- ||
 305                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 306                         debug("%s timeout %x\n", what,
 307                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 308                         return -ETIMEDOUT;
 309                 }
 310                 udelay(1000);
 311         } while (!(status & done_bit));
 312
 313         return 0;
 314 }
 315
 316 static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 317                               struct mmc_data *data)
 318 {
 319         struct sunxi_mmc_priv *priv = mmc->priv;
 320         unsigned int cmdval = SUNXI_MMC_CMD_START;
 321         unsigned int timeout_msecs;
 322         int error = 0;
 323         unsigned int status = 0;
 324         unsigned int bytecnt = 0;
 325
 326         if (priv->fatal_err)
 327                 return -1;
 328         if (cmd->resp_type & MMC_RSP_BUSY)
 329                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 330         if (cmd->cmdidx == 12)
 331                 return 0;
 332
 333         if (!cmd->cmdidx)
 334                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 335         if (cmd->resp_type & MMC_RSP_PRESENT)
 336                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 337         if (cmd->resp_type & MMC_RSP_136)
 338                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 339         if (cmd->resp_type & MMC_RSP_CRC)
 340                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 341
 342         if (data) {
 343                 if ((u32)(long)data->dest & 0x3) {
 344                         error = -1;
 345                         goto out;
 346                 }
 347
 348                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 349                 if (data->flags & MMC_DATA_WRITE)
 350                         cmdval |= SUNXI_MMC_CMD_WRITE;
 351                 if (data->blocks > 1)
 352                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 353                 writel(data->blocksize, &priv->reg->blksz);
 354                 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 355         }
 356
 357         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
 358               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 359         writel(cmd->cmdarg, &priv->reg->arg);
 360
 361         if (!data)
 362                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 363
 364         /*
 365          * transfer data and check status
 366          * STATREG[2] : FIFO empty
 367          * STATREG[3] : FIFO full
 368          */
 369         if (data) {
 370                 int ret = 0;
 371
 372                 bytecnt = data->blocksize * data->blocks;
 373                 debug("trans data %d bytes\n", bytecnt);
 374                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 375                 ret = mmc_trans_data_by_cpu(mmc, data);
 376                 if (ret) {
 377                         error = readl(&priv->reg->rint) &
 378                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 379                         error = -ETIMEDOUT;
 380                         goto out;
 381                 }
 382         }
 383
 384         error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
 385         if (error)
 386                 goto out;
 387
 388         if (data) {
 389                 timeout_msecs = 120;
 390                 debug("cacl timeout %x msec\n", timeout_msecs);
 391                 error = mmc_rint_wait(mmc, timeout_msecs,
 392                                       data->blocks > 1 ?
 393                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 394                                       SUNXI_MMC_RINT_DATA_OVER,
 395                                       "data");
 396                 if (error)
 397                         goto out;
 398         }
 399
 400         if (cmd->resp_type & MMC_RSP_BUSY) {
 401                 timeout_msecs = 2000;
 402                 do {
 403                         status = readl(&priv->reg->status);
 404                         if (!timeout_msecs--) {
 405                                 debug("busy timeout\n");
 406                                 error = -ETIMEDOUT;
 407                                 goto out;
 408                         }
 409                         udelay(1000);
 410                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 411         }
 412
 413         if (cmd->resp_type & MMC_RSP_136) {
 414                 cmd->response[0] = readl(&priv->reg->resp3);
 415                 cmd->response[1] = readl(&priv->reg->resp2);
 416                 cmd->response[2] = readl(&priv->reg->resp1);
 417                 cmd->response[3] = readl(&priv->reg->resp0);
 418                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 419                       cmd->response[3], cmd->response[2],
 420                       cmd->response[1], cmd->response[0]);
 421         } else {
 422                 cmd->response[0] = readl(&priv->reg->resp0);
 423                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 424         }
 425 out:
 426         if (error < 0) {
 427                 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 428                 mmc_update_clk(mmc);
 429         }
 430         writel(0xffffffff, &priv->reg->rint);
 431         writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 432                &priv->reg->gctrl);
 433
 434         return error;
 435 }
 436
 437 static int sunxi_mmc_getcd(struct mmc *mmc)
 438 {
 439         struct sunxi_mmc_priv *priv = mmc->priv;
 440         int cd_pin;
 441
 442         cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
 443         if (cd_pin < 0)
 444                 return 1;
 445
 446         return !gpio_get_value(cd_pin);
 447 }
 448
 449 static const struct mmc_ops sunxi_mmc_ops = {
 450         .send_cmd       = sunxi_mmc_send_cmd,
 451         .set_ios        = sunxi_mmc_set_ios,
 452         .init           = sunxi_mmc_core_init,
 453         .getcd          = sunxi_mmc_getcd,
 454 };
 455
 456 struct mmc *sunxi_mmc_init(int sdc_no)
 457 {
 458         struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
 459
 460         memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_priv));
 461
 462         cfg->name = "SUNXI SD/MMC";
 463         cfg->ops  = &sunxi_mmc_ops;
 464
 465         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 466         cfg->host_caps = MMC_MODE_4BIT;
 467 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
 468         if (sdc_no == 2)
 469                 cfg->host_caps = MMC_MODE_8BIT;
 470 #endif
 471         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 472         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 473
 474         cfg->f_min = 400000;
 475         cfg->f_max = 52000000;
 476
 477         if (mmc_resource_init(sdc_no) != 0)
 478                 return NULL;
 479
 480         mmc_clk_io_on(sdc_no);
 481
 482         return mmc_create(cfg, &mmc_host[sdc_no]);
 483 }