git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/zynq_nand.c

   1 /*
   2  * (C) Copyright 2016 Xilinx, Inc.
   3  *
   4  * Xilinx Zynq NAND Flash Controller Driver
   5  * This driver is based on plat_nand.c and mxc_nand.c drivers
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <linux/errno.h>
  14 #include <nand.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/mtd/nand_ecc.h>
  19 #include <asm/arch/hardware.h>
  20
  21 /* The NAND flash driver defines */
  22 #define ZYNQ_NAND_CMD_PHASE             1
  23 #define ZYNQ_NAND_DATA_PHASE            2
  24 #define ZYNQ_NAND_ECC_SIZE              512
  25 #define ZYNQ_NAND_SET_OPMODE_8BIT       (0 << 0)
  26 #define ZYNQ_NAND_SET_OPMODE_16BIT      (1 << 0)
  27 #define ZYNQ_NAND_ECC_STATUS            (1 << 6)
  28 #define ZYNQ_MEMC_CLRCR_INT_CLR1        (1 << 4)
  29 #define ZYNQ_MEMC_SR_RAW_INT_ST1        (1 << 6)
  30 #define ZYNQ_MEMC_SR_INT_ST1            (1 << 4)
  31 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK    0xC
  32
  33 /* Flash memory controller operating parameters */
  34 #define ZYNQ_NAND_CLR_CONFIG    ((0x1 << 1)  |  /* Disable interrupt */ \
  35                                 (0x1 << 4)   |  /* Clear interrupt */ \
  36                                 (0x1 << 6))     /* Disable ECC interrupt */
  37
  38 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  39 #define ZYNQ_NAND_SET_CYCLES    ((0x2 << 20) |  /* t_rr from nand_cycles */ \
  40                                 (0x2 << 17)  |  /* t_ar from nand_cycles */ \
  41                                 (0x1 << 14)  |  /* t_clr from nand_cycles */ \
  42                                 (0x3 << 11)  |  /* t_wp from nand_cycles */ \
  43                                 (0x2 << 8)   |  /* t_rea from nand_cycles */ \
  44                                 (0x5 << 4)   |  /* t_wc from nand_cycles */ \
  45                                 (0x5 << 0))     /* t_rc from nand_cycles */
  46
  47
  48 #define ZYNQ_NAND_DIRECT_CMD    ((0x4 << 23) |  /* Chip 0 from interface 1 */ \
  49                                 (0x2 << 21))    /* UpdateRegs operation */
  50
  51 #define ZYNQ_NAND_ECC_CONFIG    ((0x1 << 2)  |  /* ECC available on APB */ \
  52                                 (0x1 << 4)   |  /* ECC read at end of page */ \
  53                                 (0x0 << 5))     /* No Jumping */
  54
  55 #define ZYNQ_NAND_ECC_CMD1      ((0x80)      |  /* Write command */ \
  56                                 (0x00 << 8)  |  /* Read command */ \
  57                                 (0x30 << 16) |  /* Read End command */ \
  58                                 (0x1 << 24))    /* Read End command calid */
  59
  60 #define ZYNQ_NAND_ECC_CMD2      ((0x85)      |  /* Write col change cmd */ \
  61                                 (0x05 << 8)  |  /* Read col change cmd */ \
  62                                 (0xE0 << 16) |  /* Read col change end cmd */ \
  63                                 (0x1 << 24))    /* Read col change
  64                                                         end cmd valid */
  65 /* AXI Address definitions */
  66 #define START_CMD_SHIFT                 3
  67 #define END_CMD_SHIFT                   11
  68 #define END_CMD_VALID_SHIFT             20
  69 #define ADDR_CYCLES_SHIFT               21
  70 #define CLEAR_CS_SHIFT                  21
  71 #define ECC_LAST_SHIFT                  10
  72 #define COMMAND_PHASE                   (0 << 19)
  73 #define DATA_PHASE                      (1 << 19)
  74 #define ONDIE_ECC_FEATURE_ADDR          0x90
  75 #define ONDIE_ECC_FEATURE_ENABLE        0x08
  76
  77 #define ZYNQ_NAND_ECC_LAST      (1 << ECC_LAST_SHIFT)   /* Set ECC_Last */
  78 #define ZYNQ_NAND_CLEAR_CS      (1 << CLEAR_CS_SHIFT)   /* Clear chip select */
  79
  80 /* ECC block registers bit position and bit mask */
  81 #define ZYNQ_NAND_ECC_BUSY      (1 << 6)        /* ECC block is busy */
  82 #define ZYNQ_NAND_ECC_MASK      0x00FFFFFF      /* ECC value mask */
  83
  84
  85 /* SMC register set */
  86 struct zynq_nand_smc_regs {
  87         u32 csr;                /* 0x00 */
  88         u32 reserved0[2];
  89         u32 cfr;                /* 0x0C */
  90         u32 dcr;                /* 0x10 */
  91         u32 scr;                /* 0x14 */
  92         u32 sor;                /* 0x18 */
  93         u32 reserved1[249];
  94         u32 esr;                /* 0x400 */
  95         u32 emcr;               /* 0x404 */
  96         u32 emcmd1r;            /* 0x408 */
  97         u32 emcmd2r;            /* 0x40C */
  98         u32 reserved2[2];
  99         u32 eval0r;             /* 0x418 */
 100 };
 101 #define zynq_nand_smc_base      ((struct zynq_nand_smc_regs __iomem *)\
 102                                 ZYNQ_SMC_BASEADDR)
 103
 104 /*
 105  * struct zynq_nand_info - Defines the NAND flash driver instance
 106  * @parts:              Pointer to the mtd_partition structure
 107  * @nand_base:          Virtual address of the NAND flash device
 108  * @end_cmd_pending:    End command is pending
 109  * @end_cmd:            End command
 110  */
 111 struct zynq_nand_info {
 112         void __iomem    *nand_base;
 113         u8              end_cmd_pending;
 114         u8              end_cmd;
 115 };
 116
 117 /*
 118  * struct zynq_nand_command_format - Defines NAND flash command format
 119  * @start_cmd:          First cycle command (Start command)
 120  * @end_cmd:            Second cycle command (Last command)
 121  * @addr_cycles:        Number of address cycles required to send the address
 122  * @end_cmd_valid:      The second cycle command is valid for cmd or data phase
 123  */
 124 struct zynq_nand_command_format {
 125         u8 start_cmd;
 126         u8 end_cmd;
 127         u8 addr_cycles;
 128         u8 end_cmd_valid;
 129 };
 130
 131 /*  The NAND flash operations command format */
 132 static const struct zynq_nand_command_format zynq_nand_commands[] = {
 133         {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
 134         {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
 135         {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
 136         {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
 137         {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
 138         {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
 139         {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
 140         {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
 141         {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
 142         {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
 143         {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
 144         {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
 145         /* Add all the flash commands supported by the flash device */
 146 };
 147
 148 /* Define default oob placement schemes for large and small page devices */
 149 static struct nand_ecclayout nand_oob_16 = {
 150         .eccbytes = 3,
 151         .eccpos = {0, 1, 2},
 152         .oobfree = {
 153                 { .offset = 8, .length = 8 }
 154         }
 155 };
 156
 157 static struct nand_ecclayout nand_oob_64 = {
 158         .eccbytes = 12,
 159         .eccpos = {
 160                    52, 53, 54, 55, 56, 57,
 161                    58, 59, 60, 61, 62, 63},
 162         .oobfree = {
 163                 { .offset = 2, .length = 50 }
 164         }
 165 };
 166
 167 static struct nand_ecclayout ondie_nand_oob_64 = {
 168         .eccbytes = 32,
 169
 170         .eccpos = {
 171                 8, 9, 10, 11, 12, 13, 14, 15,
 172                 24, 25, 26, 27, 28, 29, 30, 31,
 173                 40, 41, 42, 43, 44, 45, 46, 47,
 174                 56, 57, 58, 59, 60, 61, 62, 63
 175         },
 176
 177         .oobfree = {
 178                 { .offset = 4, .length = 4 },
 179                 { .offset = 20, .length = 4 },
 180                 { .offset = 36, .length = 4 },
 181                 { .offset = 52, .length = 4 }
 182         }
 183 };
 184
 185 /* bbt decriptors for chips with on-die ECC and
 186    chips with 64-byte OOB */
 187 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 188 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 189
 190 static struct nand_bbt_descr bbt_main_descr = {
 191         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 192                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 193         .offs = 4,
 194         .len = 4,
 195         .veroffs = 20,
 196         .maxblocks = 4,
 197         .pattern = bbt_pattern
 198 };
 199
 200 static struct nand_bbt_descr bbt_mirror_descr = {
 201         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 202                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 203         .offs = 4,
 204         .len = 4,
 205         .veroffs = 20,
 206         .maxblocks = 4,
 207         .pattern = mirror_pattern
 208 };
 209
 210 /*
 211  * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
 212  *
 213  * returns: status for command completion, -1 for Timeout
 214  */
 215 static int zynq_nand_waitfor_ecc_completion(void)
 216 {
 217         unsigned long timeout;
 218         u32 status;
 219
 220         /* Wait max 10us */
 221         timeout = 10;
 222         status = readl(&zynq_nand_smc_base->esr);
 223         while (status & ZYNQ_NAND_ECC_BUSY) {
 224                 status = readl(&zynq_nand_smc_base->esr);
 225                 if (timeout == 0)
 226                         return -1;
 227                 timeout--;
 228                 udelay(1);
 229         }
 230
 231         return status;
 232 }
 233
 234 /*
 235  * zynq_nand_init_nand_flash - Initialize NAND controller
 236  * @option:     Device property flags
 237  *
 238  * This function initializes the NAND flash interface on the NAND controller.
 239  *
 240  * returns:     0 on success or error value on failure
 241  */
 242 static int zynq_nand_init_nand_flash(int option)
 243 {
 244         u32 status;
 245
 246         /* disable interrupts */
 247         writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
 248         /* Initialize the NAND interface by setting cycles and operation mode */
 249         writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
 250         if (option & NAND_BUSWIDTH_16)
 251                 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
 252         else
 253                 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
 254
 255         writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
 256
 257         /* Wait till the ECC operation is complete */
 258         status = zynq_nand_waitfor_ecc_completion();
 259         if (status < 0) {
 260                 printf("%s: Timeout\n", __func__);
 261                 return status;
 262         }
 263
 264         /* Set the command1 and command2 register */
 265         writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
 266         writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
 267
 268         return 0;
 269 }
 270
 271 /*
 272  * zynq_nand_calculate_hwecc - Calculate Hardware ECC
 273  * @mtd:        Pointer to the mtd_info structure
 274  * @data:       Pointer to the page data
 275  * @ecc_code:   Pointer to the ECC buffer where ECC data needs to be stored
 276  *
 277  * This function retrieves the Hardware ECC data from the controller and returns
 278  * ECC data back to the MTD subsystem.
 279  *
 280  * returns:     0 on success or error value on failure
 281  */
 282 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 283                 u8 *ecc_code)
 284 {
 285         u32 ecc_value = 0;
 286         u8 ecc_reg, ecc_byte;
 287         u32 ecc_status;
 288
 289         /* Wait till the ECC operation is complete */
 290         ecc_status = zynq_nand_waitfor_ecc_completion();
 291         if (ecc_status < 0) {
 292                 printf("%s: Timeout\n", __func__);
 293                 return ecc_status;
 294         }
 295
 296         for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
 297                 /* Read ECC value for each block */
 298                 ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
 299
 300                 /* Get the ecc status from ecc read value */
 301                 ecc_status = (ecc_value >> 24) & 0xFF;
 302
 303                 /* ECC value valid */
 304                 if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
 305                         for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
 306                                 /* Copy ECC bytes to MTD buffer */
 307                                 *ecc_code = ecc_value & 0xFF;
 308                                 ecc_value = ecc_value >> 8;
 309                                 ecc_code++;
 310                         }
 311                 } else {
 312                         debug("%s: ecc status failed\n", __func__);
 313                 }
 314         }
 315
 316         return 0;
 317 }
 318
 319 /*
 320  * onehot - onehot function
 321  * @value:      value to check for onehot
 322  *
 323  * This function checks whether a value is onehot or not.
 324  * onehot is if and only if one bit is set.
 325  *
 326  * FIXME: Try to move this in common.h
 327  */
 328 static bool onehot(unsigned short value)
 329 {
 330         bool onehot;
 331
 332         onehot = value && !(value & (value - 1));
 333         return onehot;
 334 }
 335
 336 /*
 337  * zynq_nand_correct_data - ECC correction function
 338  * @mtd:        Pointer to the mtd_info structure
 339  * @buf:        Pointer to the page data
 340  * @read_ecc:   Pointer to the ECC value read from spare data area
 341  * @calc_ecc:   Pointer to the calculated ECC value
 342  *
 343  * This function corrects the ECC single bit errors & detects 2-bit errors.
 344  *
 345  * returns:     0 if no ECC errors found
 346  *              1 if single bit error found and corrected.
 347  *              -1 if multiple ECC errors found.
 348  */
 349 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
 350                         unsigned char *read_ecc, unsigned char *calc_ecc)
 351 {
 352         unsigned char bit_addr;
 353         unsigned int byte_addr;
 354         unsigned short ecc_odd, ecc_even;
 355         unsigned short read_ecc_lower, read_ecc_upper;
 356         unsigned short calc_ecc_lower, calc_ecc_upper;
 357
 358         read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
 359         read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
 360
 361         calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
 362         calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
 363
 364         ecc_odd = read_ecc_lower ^ calc_ecc_lower;
 365         ecc_even = read_ecc_upper ^ calc_ecc_upper;
 366
 367         if ((ecc_odd == 0) && (ecc_even == 0))
 368                 return 0;       /* no error */
 369
 370         if (ecc_odd == (~ecc_even & 0xfff)) {
 371                 /* bits [11:3] of error code is byte offset */
 372                 byte_addr = (ecc_odd >> 3) & 0x1ff;
 373                 /* bits [2:0] of error code is bit offset */
 374                 bit_addr = ecc_odd & 0x7;
 375                 /* Toggling error bit */
 376                 buf[byte_addr] ^= (1 << bit_addr);
 377                 return 1;
 378         }
 379
 380         if (onehot(ecc_odd | ecc_even))
 381                 return 1; /* one error in parity */
 382
 383         return -1; /* Uncorrectable error */
 384 }
 385
 386 /*
 387  * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
 388  * @mtd:        mtd info structure
 389  * @chip:       nand chip info structure
 390  * @page:       page number to read
 391  * @sndcmd:     flag whether to issue read command or not
 392  */
 393 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 394                         int page)
 395 {
 396         unsigned long data_phase_addr = 0;
 397         int data_width = 4;
 398         u8 *p;
 399
 400         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 401
 402         p = chip->oob_poi;
 403         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 404         p += mtd->oobsize - data_width;
 405
 406         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 407         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 408         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 409         chip->read_buf(mtd, p, data_width);
 410
 411         return 0;
 412 }
 413
 414 /*
 415  * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
 416  * @mtd:        mtd info structure
 417  * @chip:       nand chip info structure
 418  * @page:       page number to write
 419  */
 420 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 421                              int page)
 422 {
 423         int status = 0, data_width = 4;
 424         const u8 *buf = chip->oob_poi;
 425         unsigned long data_phase_addr = 0;
 426
 427         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 428
 429         chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
 430         buf += mtd->oobsize - data_width;
 431
 432         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 433         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 434         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 435         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 436         chip->write_buf(mtd, buf, data_width);
 437
 438         /* Send command to program the OOB data */
 439         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 440         status = chip->waitfunc(mtd, chip);
 441
 442         return status & NAND_STATUS_FAIL ? -EIO : 0;
 443 }
 444
 445 /*
 446  * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
 447  * @mtd:        mtd info structure
 448  * @chip:       nand chip info structure
 449  * @buf:        buffer to store read data
 450  * @oob_required: must write chip->oob_poi to OOB
 451  * @page:       page number to read
 452  */
 453 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 454                                    u8 *buf,  int oob_required, int page)
 455 {
 456         unsigned long data_width = 4;
 457         unsigned long data_phase_addr = 0;
 458         u8 *p;
 459
 460         chip->read_buf(mtd, buf, mtd->writesize);
 461
 462         p = chip->oob_poi;
 463         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 464         p += (mtd->oobsize - data_width);
 465
 466         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 467         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 468         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 469
 470         chip->read_buf(mtd, p, data_width);
 471         return 0;
 472 }
 473
 474 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
 475                 struct nand_chip *chip, u8 *buf, int oob_required, int page)
 476 {
 477         chip->read_buf(mtd, buf, mtd->writesize);
 478         return 0;
 479 }
 480
 481 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
 482                                     struct nand_chip *chip, u32 data_offs,
 483                                     u32 readlen, u8 *buf, int page)
 484 {
 485         if (data_offs != 0) {
 486                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
 487                 buf += data_offs;
 488         }
 489         chip->read_buf(mtd, buf, readlen);
 490
 491         return 0;
 492 }
 493
 494 /*
 495  * zynq_nand_write_page_raw - [Intern] raw page write function
 496  * @mtd:        mtd info structure
 497  * @chip:       nand chip info structure
 498  * @buf:        data buffer
 499  * @oob_required: must write chip->oob_poi to OOB
 500  */
 501 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
 502         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 503 {
 504         unsigned long data_width = 4;
 505         unsigned long data_phase_addr = 0;
 506         u8 *p;
 507
 508         chip->write_buf(mtd, buf, mtd->writesize);
 509
 510         p = chip->oob_poi;
 511         chip->write_buf(mtd, p, (mtd->oobsize - data_width));
 512         p += (mtd->oobsize - data_width);
 513
 514         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 515         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 516         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 517         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 518
 519         chip->write_buf(mtd, p, data_width);
 520
 521         return 0;
 522 }
 523
 524 /*
 525  * nand_write_page_hwecc - Hardware ECC based page write function
 526  * @mtd:        Pointer to the mtd info structure
 527  * @chip:       Pointer to the NAND chip info structure
 528  * @buf:        Pointer to the data buffer
 529  * @oob_required: must write chip->oob_poi to OOB
 530  *
 531  * This functions writes data and hardware generated ECC values in to the page.
 532  */
 533 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
 534         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 535 {
 536         int i, eccsteps, eccsize = chip->ecc.size;
 537         u8 *ecc_calc = chip->buffers->ecccalc;
 538         const u8 *p = buf;
 539         u32 *eccpos = chip->ecc.layout->eccpos;
 540         unsigned long data_phase_addr = 0;
 541         unsigned long data_width = 4;
 542         u8 *oob_ptr;
 543
 544         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 545                 chip->write_buf(mtd, p, eccsize);
 546                 p += eccsize;
 547         }
 548         chip->write_buf(mtd, p, (eccsize - data_width));
 549         p += eccsize - data_width;
 550
 551         /* Set ECC Last bit to 1 */
 552         data_phase_addr = (unsigned long) chip->IO_ADDR_W;
 553         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 554         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 555         chip->write_buf(mtd, p, data_width);
 556
 557         /* Wait for ECC to be calculated and read the error values */
 558         p = buf;
 559         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 560
 561         for (i = 0; i < chip->ecc.total; i++)
 562                 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
 563
 564         /* Clear ECC last bit */
 565         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 566         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 567         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 568
 569         /* Write the spare area with ECC bytes */
 570         oob_ptr = chip->oob_poi;
 571         chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 572
 573         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 574         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 575         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 576         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 577         oob_ptr += (mtd->oobsize - data_width);
 578         chip->write_buf(mtd, oob_ptr, data_width);
 579
 580         return 0;
 581 }
 582
 583 /*
 584  * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
 585  * write function
 586  * @mtd:        mtd info structure
 587  * @chip:       nand chip info structure
 588  * @buf:        data buffer
 589  * @oob_required: must write chip->oob_poi to OOB
 590  */
 591 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
 592         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 593 {
 594         int i, eccsize = chip->ecc.size;
 595         int eccbytes = chip->ecc.bytes;
 596         int eccsteps = chip->ecc.steps;
 597         u8 *ecc_calc = chip->buffers->ecccalc;
 598         const u8 *p = buf;
 599         u32 *eccpos = chip->ecc.layout->eccpos;
 600
 601         /* Software ecc calculation */
 602         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 603                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 604
 605         for (i = 0; i < chip->ecc.total; i++)
 606                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
 607
 608         return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
 609 }
 610
 611 /*
 612  * nand_read_page_hwecc - Hardware ECC based page read function
 613  * @mtd:        Pointer to the mtd info structure
 614  * @chip:       Pointer to the NAND chip info structure
 615  * @buf:        Pointer to the buffer to store read data
 616  * @oob_required: must write chip->oob_poi to OOB
 617  * @page:       page number to read
 618  *
 619  * This functions reads data and checks the data integrity by comparing hardware
 620  * generated ECC values and read ECC values from spare area.
 621  *
 622  * returns:     0 always and updates ECC operation status in to MTD structure
 623  */
 624 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
 625         struct nand_chip *chip, u8 *buf, int oob_required, int page)
 626 {
 627         int i, stat, eccsteps, eccsize = chip->ecc.size;
 628         int eccbytes = chip->ecc.bytes;
 629         u8 *p = buf;
 630         u8 *ecc_calc = chip->buffers->ecccalc;
 631         u8 *ecc_code = chip->buffers->ecccode;
 632         u32 *eccpos = chip->ecc.layout->eccpos;
 633         unsigned long data_phase_addr = 0;
 634         unsigned long data_width = 4;
 635         u8 *oob_ptr;
 636
 637         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 638                 chip->read_buf(mtd, p, eccsize);
 639                 p += eccsize;
 640         }
 641         chip->read_buf(mtd, p, (eccsize - data_width));
 642         p += eccsize - data_width;
 643
 644         /* Set ECC Last bit to 1 */
 645         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 646         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 647         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 648         chip->read_buf(mtd, p, data_width);
 649
 650         /* Read the calculated ECC value */
 651         p = buf;
 652         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 653
 654         /* Clear ECC last bit */
 655         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 656         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 657         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 658
 659         /* Read the stored ECC value */
 660         oob_ptr = chip->oob_poi;
 661         chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 662
 663         /* de-assert chip select */
 664         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 665         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 666         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 667
 668         oob_ptr += (mtd->oobsize - data_width);
 669         chip->read_buf(mtd, oob_ptr, data_width);
 670
 671         for (i = 0; i < chip->ecc.total; i++)
 672                 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
 673
 674         eccsteps = chip->ecc.steps;
 675         p = buf;
 676
 677         /* Check ECC error for all blocks and correct if it is correctable */
 678         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 679                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 680                 if (stat < 0)
 681                         mtd->ecc_stats.failed++;
 682                 else
 683                         mtd->ecc_stats.corrected += stat;
 684         }
 685         return 0;
 686 }
 687
 688 /*
 689  * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
 690  * read function
 691  * @mtd:        mtd info structure
 692  * @chip:       nand chip info structure
 693  * @buf:        buffer to store read data
 694  * @page:       page number to read
 695  */
 696 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
 697         struct nand_chip *chip, u8 *buf, int oob_required,  int page)
 698 {
 699         int i, eccsize = chip->ecc.size;
 700         int eccbytes = chip->ecc.bytes;
 701         int eccsteps = chip->ecc.steps;
 702         u8 *p = buf;
 703         u8 *ecc_calc = chip->buffers->ecccalc;
 704         u8 *ecc_code = chip->buffers->ecccode;
 705         u32 *eccpos = chip->ecc.layout->eccpos;
 706
 707         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 708
 709         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 710                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 711
 712         for (i = 0; i < chip->ecc.total; i++)
 713                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 714
 715         eccsteps = chip->ecc.steps;
 716         p = buf;
 717
 718         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 719                 int stat;
 720
 721                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 722                 if (stat < 0)
 723                         mtd->ecc_stats.failed++;
 724                 else
 725                         mtd->ecc_stats.corrected += stat;
 726         }
 727         return 0;
 728 }
 729
 730 /*
 731  * zynq_nand_select_chip - Select the flash device
 732  * @mtd:        Pointer to the mtd_info structure
 733  * @chip:       Chip number to be selected
 734  *
 735  * This function is empty as the NAND controller handles chip select line
 736  * internally based on the chip address passed in command and data phase.
 737  */
 738 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
 739 {
 740         /* Not support multiple chips yet */
 741 }
 742
 743 /*
 744  * zynq_nand_cmd_function - Send command to NAND device
 745  * @mtd:        Pointer to the mtd_info structure
 746  * @command:    The command to be sent to the flash device
 747  * @column:     The column address for this command, -1 if none
 748  * @page_addr:  The page address for this command, -1 if none
 749  */
 750 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 751                                  int column, int page_addr)
 752 {
 753         struct nand_chip *chip = mtd->priv;
 754         const struct zynq_nand_command_format *curr_cmd = NULL;
 755         struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
 756         void *cmd_addr;
 757         unsigned long cmd_data = 0;
 758         unsigned long cmd_phase_addr = 0;
 759         unsigned long data_phase_addr = 0;
 760         u8 end_cmd = 0;
 761         u8 end_cmd_valid = 0;
 762         u32 index;
 763
 764         if (xnand->end_cmd_pending) {
 765                 /* Check for end command if this command request is same as the
 766                  * pending command then return
 767                  */
 768                 if (xnand->end_cmd == command) {
 769                         xnand->end_cmd = 0;
 770                         xnand->end_cmd_pending = 0;
 771                         return;
 772                 }
 773         }
 774
 775         /* Emulate NAND_CMD_READOOB for large page device */
 776         if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
 777             (command == NAND_CMD_READOOB)) {
 778                 column += mtd->writesize;
 779                 command = NAND_CMD_READ0;
 780         }
 781
 782         /* Get the command format */
 783         for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
 784                 if (command == zynq_nand_commands[index].start_cmd)
 785                         break;
 786
 787         if (index == ARRAY_SIZE(zynq_nand_commands)) {
 788                 printf("%s: Unsupported start cmd %02x\n", __func__, command);
 789                 return;
 790         }
 791         curr_cmd = &zynq_nand_commands[index];
 792
 793         /* Clear interrupt */
 794         writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
 795
 796         /* Get the command phase address */
 797         if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
 798                 end_cmd_valid = 1;
 799
 800         if (curr_cmd->end_cmd == NAND_CMD_NONE)
 801                 end_cmd = 0x0;
 802         else
 803                 end_cmd = curr_cmd->end_cmd;
 804
 805         cmd_phase_addr = (unsigned long)xnand->nand_base        |
 806                         (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT)    |
 807                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 808                         (COMMAND_PHASE)                                 |
 809                         (end_cmd << END_CMD_SHIFT)                      |
 810                         (curr_cmd->start_cmd << START_CMD_SHIFT);
 811
 812         cmd_addr = (void __iomem *)cmd_phase_addr;
 813
 814         /* Get the data phase address */
 815         end_cmd_valid = 0;
 816
 817         data_phase_addr = (unsigned long)xnand->nand_base       |
 818                         (0x0 << CLEAR_CS_SHIFT)                         |
 819                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 820                         (DATA_PHASE)                                    |
 821                         (end_cmd << END_CMD_SHIFT)                      |
 822                         (0x0 << ECC_LAST_SHIFT);
 823
 824         chip->IO_ADDR_R = (void  __iomem *)data_phase_addr;
 825         chip->IO_ADDR_W = chip->IO_ADDR_R;
 826
 827         /* Command phase AXI Read & Write */
 828         if (column != -1 && page_addr != -1) {
 829                 /* Adjust columns for 16 bit bus width */
 830                 if (chip->options & NAND_BUSWIDTH_16)
 831                         column >>= 1;
 832                 cmd_data = column;
 833                 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
 834                         cmd_data |= page_addr << 16;
 835                         /* Another address cycle for devices > 128MiB */
 836                         if (chip->chipsize > (128 << 20)) {
 837                                 writel(cmd_data, cmd_addr);
 838                                 cmd_data = (page_addr >> 16);
 839                         }
 840                 } else {
 841                         cmd_data |= page_addr << 8;
 842                 }
 843         } else if (page_addr != -1)  { /* Erase */
 844                 cmd_data = page_addr;
 845         } else if (column != -1) { /* Change read/write column, read id etc */
 846                 /* Adjust columns for 16 bit bus width */
 847                 if ((chip->options & NAND_BUSWIDTH_16) &&
 848                     ((command == NAND_CMD_READ0) ||
 849                      (command == NAND_CMD_SEQIN) ||
 850                      (command == NAND_CMD_RNDOUT) ||
 851                      (command == NAND_CMD_RNDIN)))
 852                         column >>= 1;
 853                 cmd_data = column;
 854         }
 855
 856         writel(cmd_data, cmd_addr);
 857
 858         if (curr_cmd->end_cmd_valid) {
 859                 xnand->end_cmd = curr_cmd->end_cmd;
 860                 xnand->end_cmd_pending = 1;
 861         }
 862
 863         ndelay(100);
 864
 865         if ((command == NAND_CMD_READ0) ||
 866             (command == NAND_CMD_RESET) ||
 867             (command == NAND_CMD_PARAM) ||
 868             (command == NAND_CMD_GET_FEATURES))
 869                 /* wait until command is processed */
 870                 nand_wait_ready(mtd);
 871 }
 872
 873 /*
 874  * zynq_nand_read_buf - read chip data into buffer
 875  * @mtd:        MTD device structure
 876  * @buf:        buffer to store date
 877  * @len:        number of bytes to read
 878  */
 879 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 880 {
 881         struct nand_chip *chip = mtd->priv;
 882
 883         /* Make sure that buf is 32 bit aligned */
 884         if (((unsigned long)buf & 0x3) != 0) {
 885                 if (((unsigned long)buf & 0x1) != 0) {
 886                         if (len) {
 887                                 *buf = readb(chip->IO_ADDR_R);
 888                                 buf += 1;
 889                                 len--;
 890                         }
 891                 }
 892
 893                 if (((unsigned long)buf & 0x3) != 0) {
 894                         if (len >= 2) {
 895                                 *(u16 *)buf = readw(chip->IO_ADDR_R);
 896                                 buf += 2;
 897                                 len -= 2;
 898                         }
 899                 }
 900         }
 901
 902         /* copy aligned data */
 903         while (len >= 4) {
 904                 *(u32 *)buf = readl(chip->IO_ADDR_R);
 905                 buf += 4;
 906                 len -= 4;
 907         }
 908
 909         /* mop up any remaining bytes */
 910         if (len) {
 911                 if (len >= 2) {
 912                         *(u16 *)buf = readw(chip->IO_ADDR_R);
 913                         buf += 2;
 914                         len -= 2;
 915                 }
 916                 if (len)
 917                         *buf = readb(chip->IO_ADDR_R);
 918         }
 919 }
 920
 921 /*
 922  * zynq_nand_write_buf - write buffer to chip
 923  * @mtd:        MTD device structure
 924  * @buf:        data buffer
 925  * @len:        number of bytes to write
 926  */
 927 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 928 {
 929         struct nand_chip *chip = mtd->priv;
 930         const u32 *nand = chip->IO_ADDR_W;
 931
 932         /* Make sure that buf is 32 bit aligned */
 933         if (((unsigned long)buf & 0x3) != 0) {
 934                 if (((unsigned long)buf & 0x1) != 0) {
 935                         if (len) {
 936                                 writeb(*buf, nand);
 937                                 buf += 1;
 938                                 len--;
 939                         }
 940                 }
 941
 942                 if (((unsigned long)buf & 0x3) != 0) {
 943                         if (len >= 2) {
 944                                 writew(*(u16 *)buf, nand);
 945                                 buf += 2;
 946                                 len -= 2;
 947                         }
 948                 }
 949         }
 950
 951         /* copy aligned data */
 952         while (len >= 4) {
 953                 writel(*(u32 *)buf, nand);
 954                 buf += 4;
 955                 len -= 4;
 956         }
 957
 958         /* mop up any remaining bytes */
 959         if (len) {
 960                 if (len >= 2) {
 961                         writew(*(u16 *)buf, nand);
 962                         buf += 2;
 963                         len -= 2;
 964                 }
 965
 966                 if (len)
 967                         writeb(*buf, nand);
 968         }
 969 }
 970
 971 /*
 972  * zynq_nand_device_ready - Check device ready/busy line
 973  * @mtd:        Pointer to the mtd_info structure
 974  *
 975  * returns:     0 on busy or 1 on ready state
 976  */
 977 static int zynq_nand_device_ready(struct mtd_info *mtd)
 978 {
 979         u32 csr_val;
 980
 981         csr_val = readl(&zynq_nand_smc_base->csr);
 982         /* Check the raw_int_status1 bit */
 983         if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
 984                 /* Clear the interrupt condition */
 985                 writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
 986                 return 1;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 993 {
 994         struct zynq_nand_info *xnand;
 995         struct mtd_info *mtd;
 996         unsigned long ecc_page_size;
 997         u8 maf_id, dev_id, i;
 998         u8 get_feature[4];
 999         u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1000         unsigned long ecc_cfg;
1001         int ondie_ecc_enabled = 0;
1002         int err = -1;
1003
1004         xnand = calloc(1, sizeof(struct zynq_nand_info));
1005         if (!xnand) {
1006                 printf("%s: failed to allocate\n", __func__);
1007                 goto fail;
1008         }
1009
1010         xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
1011         mtd = (struct mtd_info *)&nand_info[0];
1012
1013         nand_chip->priv = xnand;
1014         mtd->priv = nand_chip;
1015
1016         /* Set address of NAND IO lines */
1017         nand_chip->IO_ADDR_R = xnand->nand_base;
1018         nand_chip->IO_ADDR_W = xnand->nand_base;
1019
1020         /* Set the driver entry points for MTD */
1021         nand_chip->cmdfunc = zynq_nand_cmd_function;
1022         nand_chip->dev_ready = zynq_nand_device_ready;
1023         nand_chip->select_chip = zynq_nand_select_chip;
1024
1025         /* If we don't set this delay driver sets 20us by default */
1026         nand_chip->chip_delay = 30;
1027
1028         /* Buffer read/write routines */
1029         nand_chip->read_buf = zynq_nand_read_buf;
1030         nand_chip->write_buf = zynq_nand_write_buf;
1031
1032         nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1033
1034         /* Initialize the NAND flash interface on NAND controller */
1035         if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
1036                 printf("%s: nand flash init failed\n", __func__);
1037                 goto fail;
1038         }
1039
1040         /* first scan to find the device and get the page size */
1041         if (nand_scan_ident(mtd, 1, NULL)) {
1042                 printf("%s: nand_scan_ident failed\n", __func__);
1043                 goto fail;
1044         }
1045         /* Send the command for reading device ID */
1046         nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1047         nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1048
1049         /* Read manufacturer and device IDs */
1050         maf_id = nand_chip->read_byte(mtd);
1051         dev_id = nand_chip->read_byte(mtd);
1052
1053         if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1054                                  (dev_id == 0xa1) || (dev_id == 0xb1) ||
1055                                  (dev_id == 0xaa) || (dev_id == 0xba) ||
1056                                  (dev_id == 0xda) || (dev_id == 0xca) ||
1057                                  (dev_id == 0xac) || (dev_id == 0xbc) ||
1058                                  (dev_id == 0xdc) || (dev_id == 0xcc) ||
1059                                  (dev_id == 0xa3) || (dev_id == 0xb3) ||
1060                                  (dev_id == 0xd3) || (dev_id == 0xc3))) {
1061                 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1062                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1063                 for (i = 0; i < 4; i++)
1064                         writeb(set_feature[i], nand_chip->IO_ADDR_W);
1065
1066                 /* Wait for 1us after writing data with SET_FEATURES command */
1067                 ndelay(1000);
1068
1069                 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1070                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1071                 nand_chip->read_buf(mtd, get_feature, 4);
1072
1073                 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1074                         debug("%s: OnDie ECC flash\n", __func__);
1075                         ondie_ecc_enabled = 1;
1076                 } else {
1077                         printf("%s: Unable to detect OnDie ECC\n", __func__);
1078                 }
1079         }
1080
1081         if (ondie_ecc_enabled) {
1082                 /* Bypass the controller ECC block */
1083                 ecc_cfg = readl(&zynq_nand_smc_base->emcr);
1084                 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1085                 writel(ecc_cfg, &zynq_nand_smc_base->emcr);
1086
1087                 /* The software ECC routines won't work
1088                  * with the SMC controller
1089                  */
1090                 nand_chip->ecc.mode = NAND_ECC_HW;
1091                 nand_chip->ecc.strength = 1;
1092                 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1093                 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1094                 nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1095                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1096                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1097                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1098                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1099                 nand_chip->ecc.size = mtd->writesize;
1100                 nand_chip->ecc.bytes = 0;
1101
1102                 /* NAND with on-die ECC supports subpage reads */
1103                 nand_chip->options |= NAND_SUBPAGE_READ;
1104
1105                 /* On-Die ECC spare bytes offset 8 is used for ECC codes */
1106                 if (ondie_ecc_enabled) {
1107                         nand_chip->ecc.layout = &ondie_nand_oob_64;
1108                         /* Use the BBT pattern descriptors */
1109                         nand_chip->bbt_td = &bbt_main_descr;
1110                         nand_chip->bbt_md = &bbt_mirror_descr;
1111                 }
1112         } else {
1113                 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1114                 nand_chip->ecc.mode = NAND_ECC_HW;
1115                 nand_chip->ecc.strength = 1;
1116                 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1117                 nand_chip->ecc.bytes = 3;
1118                 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1119                 nand_chip->ecc.correct = zynq_nand_correct_data;
1120                 nand_chip->ecc.hwctl = NULL;
1121                 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1122                 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1123                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1124                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1125                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1126                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1127
1128                 switch (mtd->writesize) {
1129                 case 512:
1130                         ecc_page_size = 0x1;
1131                         /* Set the ECC memory config register */
1132                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1133                                &zynq_nand_smc_base->emcr);
1134                         break;
1135                 case 1024:
1136                         ecc_page_size = 0x2;
1137                         /* Set the ECC memory config register */
1138                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1139                                &zynq_nand_smc_base->emcr);
1140                         break;
1141                 case 2048:
1142                         ecc_page_size = 0x3;
1143                         /* Set the ECC memory config register */
1144                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1145                                &zynq_nand_smc_base->emcr);
1146                         break;
1147                 default:
1148                         nand_chip->ecc.mode = NAND_ECC_SOFT;
1149                         nand_chip->ecc.calculate = nand_calculate_ecc;
1150                         nand_chip->ecc.correct = nand_correct_data;
1151                         nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1152                         nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1153                         nand_chip->ecc.size = 256;
1154                         break;
1155                 }
1156
1157                 if (mtd->oobsize == 16)
1158                         nand_chip->ecc.layout = &nand_oob_16;
1159                 else if (mtd->oobsize == 64)
1160                         nand_chip->ecc.layout = &nand_oob_64;
1161                 else
1162                         printf("%s: No oob layout found\n", __func__);
1163         }
1164
1165         /* Second phase scan */
1166         if (nand_scan_tail(mtd)) {
1167                 printf("%s: nand_scan_tail failed\n", __func__);
1168                 goto fail;
1169         }
1170         if (nand_register(devnum, mtd))
1171                 goto fail;
1172         return 0;
1173 fail:
1174         free(xnand);
1175         return err;
1176 }
1177
1178 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1179
1180 void board_nand_init(void)
1181 {
1182         struct nand_chip *nand = &nand_chip[0];
1183
1184         if (zynq_nand_init(nand, 0))
1185                 puts("ZYNQ NAND init failed\n");
1186 }