2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
96 #define MVPP2_RXQ_POOL_LONG_OFFS 24
97 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
98 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
99 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
100 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
101 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
103 /* Parser Registers */
104 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
105 #define MVPP2_PRS_PORT_LU_MAX 0xf
106 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
107 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
108 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
109 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
110 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
112 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
113 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
114 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
115 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
116 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
117 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
118 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
119 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
120 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
122 /* Classifier Registers */
123 #define MVPP2_CLS_MODE_REG 0x1800
124 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
125 #define MVPP2_CLS_PORT_WAY_REG 0x1810
126 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
127 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
128 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
129 #define MVPP2_CLS_LKP_TBL_REG 0x1818
130 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
131 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
132 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
133 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
134 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
135 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
137 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
139 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
140 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
141 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
143 /* Descriptor Manager Top Registers */
144 #define MVPP2_RXQ_NUM_REG 0x2040
145 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
146 #define MVPP22_DESC_ADDR_OFFS 8
147 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
148 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
149 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
150 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
151 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
152 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
153 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
154 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
155 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
156 #define MVPP2_RXQ_THRESH_REG 0x204c
157 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
158 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
159 #define MVPP2_RXQ_INDEX_REG 0x2050
160 #define MVPP2_TXQ_NUM_REG 0x2080
161 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
162 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
163 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
164 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
165 #define MVPP2_TXQ_THRESH_REG 0x2094
166 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
167 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
168 #define MVPP2_TXQ_INDEX_REG 0x2098
169 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
170 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
171 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
172 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
173 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
174 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
175 #define MVPP2_TXQ_PENDING_REG 0x20a0
176 #define MVPP2_TXQ_PENDING_MASK 0x3fff
177 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
178 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
179 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
180 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
181 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
182 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
183 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
184 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
185 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
186 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
187 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
188 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
189 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
190 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
191 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
192 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
193 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
195 /* MBUS bridge registers */
196 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
197 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
198 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
199 #define MVPP2_BASE_ADDR_ENABLE 0x4060
201 /* AXI Bridge Registers */
202 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
203 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
204 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
205 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
206 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
207 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
208 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
209 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
210 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
211 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
212 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
213 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
215 /* Values for AXI Bridge registers */
216 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
217 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
219 #define MVPP22_AXI_CODE_CACHE_OFFS 0
220 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
222 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
223 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
224 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
226 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
227 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
229 /* Interrupt Cause and Mask registers */
230 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
231 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
233 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
234 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
235 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
236 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
238 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
239 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
241 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
242 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
243 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
244 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
246 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
247 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
248 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
249 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
250 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
251 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
252 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
253 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
254 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
255 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
256 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
257 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
258 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
259 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
260 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
261 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
262 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
263 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
265 /* Buffer Manager registers */
266 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
267 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
268 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
269 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
270 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
271 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
272 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
273 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
274 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
275 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
276 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
277 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
278 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
279 #define MVPP2_BM_START_MASK BIT(0)
280 #define MVPP2_BM_STOP_MASK BIT(1)
281 #define MVPP2_BM_STATE_MASK BIT(4)
282 #define MVPP2_BM_LOW_THRESH_OFFS 8
283 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
284 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
285 MVPP2_BM_LOW_THRESH_OFFS)
286 #define MVPP2_BM_HIGH_THRESH_OFFS 16
287 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
288 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
289 MVPP2_BM_HIGH_THRESH_OFFS)
290 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
291 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
292 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
293 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
294 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
295 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
296 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
297 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
298 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
299 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
300 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
301 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
302 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
303 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
304 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
305 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
306 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
307 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
308 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
309 #define MVPP21_BM_MC_RLS_REG 0x64c4
310 #define MVPP2_BM_MC_ID_MASK 0xfff
311 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
312 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
313 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
314 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
315 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
316 #define MVPP22_BM_MC_RLS_REG 0x64d4
318 /* TX Scheduler registers */
319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
320 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
322 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
323 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
324 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
325 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
326 #define MVPP2_TXP_MTU_MAX 0x7FFFF
327 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
328 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
329 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
330 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
331 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
332 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
333 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
334 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
335 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
336 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
337 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
338 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
339 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
340 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
342 /* TX general registers */
343 #define MVPP2_TX_SNOOP_REG 0x8800
344 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
345 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
348 #define MVPP2_SRC_ADDR_MIDDLE 0x24
349 #define MVPP2_SRC_ADDR_HIGH 0x28
350 #define MVPP2_PHY_AN_CFG0_REG 0x34
351 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
352 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
353 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
355 /* Per-port registers */
356 #define MVPP2_GMAC_CTRL_0_REG 0x0
357 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
358 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
359 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
360 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
361 #define MVPP2_GMAC_CTRL_1_REG 0x4
362 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
363 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
364 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
365 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
366 #define MVPP2_GMAC_SA_LOW_OFFS 7
367 #define MVPP2_GMAC_CTRL_2_REG 0x8
368 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
369 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
370 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
371 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
372 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
373 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
374 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
375 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
376 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
377 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
378 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
379 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
380 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
381 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
382 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
383 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
384 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
385 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
387 #define MVPP22_SMI_MISC_CFG_REG 0x1204
388 #define MVPP22_SMI_POLLING_EN BIT(10)
390 #define MVPP22_PORT_BASE 0x30e00
391 #define MVPP22_PORT_OFFSET 0x1000
393 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
395 /* Descriptor ring Macros */
396 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
397 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
399 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
400 #define MVPP21_SMI 0x0054
401 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
402 #define MVPP22_SMI 0x1200
403 #define MVPP2_PHY_REG_MASK 0x1f
404 /* SMI register fields */
405 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
406 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
407 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
408 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
409 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
410 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
411 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
412 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
414 #define MVPP2_PHY_ADDR_MASK 0x1f
415 #define MVPP2_PHY_REG_MASK 0x1f
417 /* Various constants */
420 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
421 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
422 #define MVPP2_RX_COAL_PKTS 32
423 #define MVPP2_RX_COAL_USEC 100
425 /* The two bytes Marvell header. Either contains a special value used
426 * by Marvell switches when a specific hardware mode is enabled (not
427 * supported by this driver) or is filled automatically by zeroes on
428 * the RX side. Those two bytes being at the front of the Ethernet
429 * header, they allow to have the IP header aligned on a 4 bytes
430 * boundary automatically: the hardware skips those two bytes on its
433 #define MVPP2_MH_SIZE 2
434 #define MVPP2_ETH_TYPE_LEN 2
435 #define MVPP2_PPPOE_HDR_SIZE 8
436 #define MVPP2_VLAN_TAG_LEN 4
438 /* Lbtd 802.3 type */
439 #define MVPP2_IP_LBDT_TYPE 0xfffa
441 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
442 #define MVPP2_TX_CSUM_MAX_SIZE 9800
444 /* Timeout constants */
445 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
446 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
448 #define MVPP2_TX_MTU_MAX 0x7ffff
450 /* Maximum number of T-CONTs of PON port */
451 #define MVPP2_MAX_TCONT 16
453 /* Maximum number of supported ports */
454 #define MVPP2_MAX_PORTS 4
456 /* Maximum number of TXQs used by single port */
457 #define MVPP2_MAX_TXQ 8
459 /* Default number of TXQs in use */
460 #define MVPP2_DEFAULT_TXQ 1
462 /* Dfault number of RXQs in use */
463 #define MVPP2_DEFAULT_RXQ 1
464 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
466 /* Max number of Rx descriptors */
467 #define MVPP2_MAX_RXD 16
469 /* Max number of Tx descriptors */
470 #define MVPP2_MAX_TXD 16
472 /* Amount of Tx descriptors that can be reserved at once by CPU */
473 #define MVPP2_CPU_DESC_CHUNK 64
475 /* Max number of Tx descriptors in each aggregated queue */
476 #define MVPP2_AGGR_TXQ_SIZE 256
478 /* Descriptor aligned size */
479 #define MVPP2_DESC_ALIGNED_SIZE 32
481 /* Descriptor alignment mask */
482 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
484 /* RX FIFO constants */
485 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
486 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
487 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
489 /* RX buffer constants */
490 #define MVPP2_SKB_SHINFO_SIZE \
493 #define MVPP2_RX_PKT_SIZE(mtu) \
494 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
495 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
497 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
498 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
499 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
500 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
502 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
504 /* IPv6 max L3 address size */
505 #define MVPP2_MAX_L3_ADDR_SIZE 16
508 #define MVPP2_F_LOOPBACK BIT(0)
510 /* Marvell tag types */
511 enum mvpp2_tag_type {
512 MVPP2_TAG_TYPE_NONE = 0,
513 MVPP2_TAG_TYPE_MH = 1,
514 MVPP2_TAG_TYPE_DSA = 2,
515 MVPP2_TAG_TYPE_EDSA = 3,
516 MVPP2_TAG_TYPE_VLAN = 4,
517 MVPP2_TAG_TYPE_LAST = 5
520 /* Parser constants */
521 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
522 #define MVPP2_PRS_TCAM_WORDS 6
523 #define MVPP2_PRS_SRAM_WORDS 4
524 #define MVPP2_PRS_FLOW_ID_SIZE 64
525 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
526 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
527 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
528 #define MVPP2_PRS_IPV4_HEAD 0x40
529 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
530 #define MVPP2_PRS_IPV4_MC 0xe0
531 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
532 #define MVPP2_PRS_IPV4_BC_MASK 0xff
533 #define MVPP2_PRS_IPV4_IHL 0x5
534 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
535 #define MVPP2_PRS_IPV6_MC 0xff
536 #define MVPP2_PRS_IPV6_MC_MASK 0xff
537 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
538 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
539 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
540 #define MVPP2_PRS_DBL_VLANS_MAX 100
543 * - lookup ID - 4 bits
545 * - additional information - 1 byte
546 * - header data - 8 bytes
547 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
549 #define MVPP2_PRS_AI_BITS 8
550 #define MVPP2_PRS_PORT_MASK 0xff
551 #define MVPP2_PRS_LU_MASK 0xf
552 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
553 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
554 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
555 (((offs) * 2) - ((offs) % 2) + 2)
556 #define MVPP2_PRS_TCAM_AI_BYTE 16
557 #define MVPP2_PRS_TCAM_PORT_BYTE 17
558 #define MVPP2_PRS_TCAM_LU_BYTE 20
559 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
560 #define MVPP2_PRS_TCAM_INV_WORD 5
561 /* Tcam entries ID */
562 #define MVPP2_PE_DROP_ALL 0
563 #define MVPP2_PE_FIRST_FREE_TID 1
564 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
565 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
566 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
567 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
568 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
569 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
570 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
571 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
572 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
573 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
574 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
575 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
576 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
577 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
578 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
579 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
580 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
581 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
582 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
583 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
584 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
585 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
586 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
587 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
588 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
591 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
593 #define MVPP2_PRS_SRAM_RI_OFFS 0
594 #define MVPP2_PRS_SRAM_RI_WORD 0
595 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
596 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
597 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
598 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
599 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
600 #define MVPP2_PRS_SRAM_UDF_OFFS 73
601 #define MVPP2_PRS_SRAM_UDF_BITS 8
602 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
603 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
604 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
605 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
606 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
607 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
608 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
609 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
610 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
611 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
612 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
613 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
614 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
615 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
616 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
617 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
618 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
619 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
620 #define MVPP2_PRS_SRAM_AI_OFFS 90
621 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
622 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
623 #define MVPP2_PRS_SRAM_AI_MASK 0xff
624 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
625 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
626 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
627 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
629 /* Sram result info bits assignment */
630 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
631 #define MVPP2_PRS_RI_DSA_MASK 0x2
632 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
633 #define MVPP2_PRS_RI_VLAN_NONE 0x0
634 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
635 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
636 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
637 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
638 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
639 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
640 #define MVPP2_PRS_RI_L2_UCAST 0x0
641 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
642 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
643 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
644 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
645 #define MVPP2_PRS_RI_L3_UN 0x0
646 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
647 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
648 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
649 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
650 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
651 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
652 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
653 #define MVPP2_PRS_RI_L3_UCAST 0x0
654 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
655 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
656 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
657 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
658 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
659 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
660 #define MVPP2_PRS_RI_L4_TCP BIT(22)
661 #define MVPP2_PRS_RI_L4_UDP BIT(23)
662 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
663 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
664 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
665 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
667 /* Sram additional info bits assignment */
668 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
669 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
670 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
671 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
672 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
673 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
674 #define MVPP2_PRS_SINGLE_VLAN_AI 0
675 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
678 #define MVPP2_PRS_TAGGED true
679 #define MVPP2_PRS_UNTAGGED false
680 #define MVPP2_PRS_EDSA true
681 #define MVPP2_PRS_DSA false
683 /* MAC entries, shadow udf */
685 MVPP2_PRS_UDF_MAC_DEF,
686 MVPP2_PRS_UDF_MAC_RANGE,
687 MVPP2_PRS_UDF_L2_DEF,
688 MVPP2_PRS_UDF_L2_DEF_COPY,
689 MVPP2_PRS_UDF_L2_USER,
693 enum mvpp2_prs_lookup {
707 enum mvpp2_prs_l3_cast {
708 MVPP2_PRS_L3_UNI_CAST,
709 MVPP2_PRS_L3_MULTI_CAST,
710 MVPP2_PRS_L3_BROAD_CAST
713 /* Classifier constants */
714 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
715 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
716 #define MVPP2_CLS_LKP_TBL_SIZE 64
719 #define MVPP2_BM_POOLS_NUM 1
720 #define MVPP2_BM_LONG_BUF_NUM 16
721 #define MVPP2_BM_SHORT_BUF_NUM 16
722 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
723 #define MVPP2_BM_POOL_PTR_ALIGN 128
724 #define MVPP2_BM_SWF_LONG_POOL(port) 0
726 /* BM cookie (32 bits) definition */
727 #define MVPP2_BM_COOKIE_POOL_OFFS 8
728 #define MVPP2_BM_COOKIE_CPU_OFFS 24
730 /* BM short pool packet size
731 * These value assure that for SWF the total number
732 * of bytes allocated for each buffer will be 512
734 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
744 /* Shared Packet Processor resources */
746 /* Shared registers' base addresses */
748 void __iomem *lms_base;
749 void __iomem *iface_base;
750 void __iomem *mdio_base;
752 /* List of pointers to port structures */
753 struct mvpp2_port **port_list;
755 /* Aggregated TXQs */
756 struct mvpp2_tx_queue *aggr_txqs;
759 struct mvpp2_bm_pool *bm_pools;
761 /* PRS shadow table */
762 struct mvpp2_prs_shadow *prs_shadow;
763 /* PRS auxiliary table for double vlan entries control */
764 bool *prs_double_vlans;
770 enum { MVPP21, MVPP22 } hw_version;
772 /* Maximum number of RXQs per port */
773 unsigned int max_port_rxqs;
780 struct mvpp2_pcpu_stats {
790 /* Index of the port from the "group of ports" complex point
799 /* Per-port registers' base address */
802 struct mvpp2_rx_queue **rxqs;
803 struct mvpp2_tx_queue **txqs;
807 u32 pending_cause_rx;
809 /* Per-CPU port control */
810 struct mvpp2_port_pcpu __percpu *pcpu;
817 struct mvpp2_pcpu_stats __percpu *stats;
819 struct phy_device *phy_dev;
820 phy_interface_t phy_interface;
828 struct mvpp2_bm_pool *pool_long;
829 struct mvpp2_bm_pool *pool_short;
831 /* Index of first port's physical RXQ */
834 u8 dev_addr[ETH_ALEN];
837 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
838 * layout of the transmit and reception DMA descriptors, and their
839 * layout is therefore defined by the hardware design
842 #define MVPP2_TXD_L3_OFF_SHIFT 0
843 #define MVPP2_TXD_IP_HLEN_SHIFT 8
844 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
845 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
846 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
847 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
848 #define MVPP2_TXD_L4_UDP BIT(24)
849 #define MVPP2_TXD_L3_IP6 BIT(26)
850 #define MVPP2_TXD_L_DESC BIT(28)
851 #define MVPP2_TXD_F_DESC BIT(29)
853 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
854 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
855 #define MVPP2_RXD_ERR_CRC 0x0
856 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
857 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
858 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
859 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
860 #define MVPP2_RXD_HWF_SYNC BIT(21)
861 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
862 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
863 #define MVPP2_RXD_L4_TCP BIT(25)
864 #define MVPP2_RXD_L4_UDP BIT(26)
865 #define MVPP2_RXD_L3_IP4 BIT(28)
866 #define MVPP2_RXD_L3_IP6 BIT(30)
867 #define MVPP2_RXD_BUF_HDR BIT(31)
869 /* HW TX descriptor for PPv2.1 */
870 struct mvpp21_tx_desc {
871 u32 command; /* Options used by HW for packet transmitting.*/
872 u8 packet_offset; /* the offset from the buffer beginning */
873 u8 phys_txq; /* destination queue ID */
874 u16 data_size; /* data size of transmitted packet in bytes */
875 u32 buf_dma_addr; /* physical addr of transmitted buffer */
876 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
877 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
878 u32 reserved2; /* reserved (for future use) */
881 /* HW RX descriptor for PPv2.1 */
882 struct mvpp21_rx_desc {
883 u32 status; /* info about received packet */
884 u16 reserved1; /* parser_info (for future use, PnC) */
885 u16 data_size; /* size of received packet in bytes */
886 u32 buf_dma_addr; /* physical address of the buffer */
887 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
888 u16 reserved2; /* gem_port_id (for future use, PON) */
889 u16 reserved3; /* csum_l4 (for future use, PnC) */
890 u8 reserved4; /* bm_qset (for future use, BM) */
892 u16 reserved6; /* classify_info (for future use, PnC) */
893 u32 reserved7; /* flow_id (for future use, PnC) */
897 /* HW TX descriptor for PPv2.2 */
898 struct mvpp22_tx_desc {
904 u64 buf_dma_addr_ptp;
908 /* HW RX descriptor for PPv2.2 */
909 struct mvpp22_rx_desc {
915 u64 buf_dma_addr_key_hash;
919 /* Opaque type used by the driver to manipulate the HW TX and RX
922 struct mvpp2_tx_desc {
924 struct mvpp21_tx_desc pp21;
925 struct mvpp22_tx_desc pp22;
929 struct mvpp2_rx_desc {
931 struct mvpp21_rx_desc pp21;
932 struct mvpp22_rx_desc pp22;
936 /* Per-CPU Tx queue control */
937 struct mvpp2_txq_pcpu {
940 /* Number of Tx DMA descriptors in the descriptor ring */
943 /* Number of currently used Tx DMA descriptor in the
948 /* Number of Tx DMA descriptors reserved for each CPU */
951 /* Index of last TX DMA descriptor that was inserted */
954 /* Index of the TX DMA descriptor to be cleaned up */
958 struct mvpp2_tx_queue {
959 /* Physical number of this Tx queue */
962 /* Logical number of this Tx queue */
965 /* Number of Tx DMA descriptors in the descriptor ring */
968 /* Number of currently used Tx DMA descriptor in the descriptor ring */
971 /* Per-CPU control of physical Tx queues */
972 struct mvpp2_txq_pcpu __percpu *pcpu;
976 /* Virtual address of thex Tx DMA descriptors array */
977 struct mvpp2_tx_desc *descs;
979 /* DMA address of the Tx DMA descriptors array */
980 dma_addr_t descs_dma;
982 /* Index of the last Tx DMA descriptor */
985 /* Index of the next Tx DMA descriptor to process */
986 int next_desc_to_proc;
989 struct mvpp2_rx_queue {
990 /* RX queue number, in the range 0-31 for physical RXQs */
993 /* Num of rx descriptors in the rx descriptor ring */
999 /* Virtual address of the RX DMA descriptors array */
1000 struct mvpp2_rx_desc *descs;
1002 /* DMA address of the RX DMA descriptors array */
1003 dma_addr_t descs_dma;
1005 /* Index of the last RX DMA descriptor */
1008 /* Index of the next RX DMA descriptor to process */
1009 int next_desc_to_proc;
1011 /* ID of port to which physical RXQ is mapped */
1014 /* Port's logic RXQ number to which physical RXQ is mapped */
1018 union mvpp2_prs_tcam_entry {
1019 u32 word[MVPP2_PRS_TCAM_WORDS];
1020 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1023 union mvpp2_prs_sram_entry {
1024 u32 word[MVPP2_PRS_SRAM_WORDS];
1025 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1028 struct mvpp2_prs_entry {
1030 union mvpp2_prs_tcam_entry tcam;
1031 union mvpp2_prs_sram_entry sram;
1034 struct mvpp2_prs_shadow {
1041 /* User defined offset */
1049 struct mvpp2_cls_flow_entry {
1051 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1054 struct mvpp2_cls_lookup_entry {
1060 struct mvpp2_bm_pool {
1061 /* Pool number in the range 0-7 */
1063 enum mvpp2_bm_type type;
1065 /* Buffer Pointers Pool External (BPPE) size */
1067 /* Number of buffers for this pool */
1069 /* Pool buffer size */
1074 /* BPPE virtual base address */
1075 unsigned long *virt_addr;
1076 /* BPPE DMA base address */
1077 dma_addr_t dma_addr;
1079 /* Ports using BM pool */
1082 /* Occupied buffers indicator */
1086 /* Static declaractions */
1088 /* Number of RXQs used by single port */
1089 static int rxq_number = MVPP2_DEFAULT_RXQ;
1090 /* Number of TXQs used by single port */
1091 static int txq_number = MVPP2_DEFAULT_TXQ;
1095 #define MVPP2_DRIVER_NAME "mvpp2"
1096 #define MVPP2_DRIVER_VERSION "1.0"
1099 * U-Boot internal data, mostly uncached buffers for descriptors and data
1101 struct buffer_location {
1102 struct mvpp2_tx_desc *aggr_tx_descs;
1103 struct mvpp2_tx_desc *tx_descs;
1104 struct mvpp2_rx_desc *rx_descs;
1105 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1106 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1111 * All 4 interfaces use the same global buffer, since only one interface
1112 * can be enabled at once
1114 static struct buffer_location buffer_loc;
1117 * Page table entries are set to 1MB, or multiples of 1MB
1118 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1120 #define BD_SPACE (1 << 20)
1122 /* Utility/helper methods */
1124 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1126 writel(data, priv->base + offset);
1129 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1131 return readl(priv->base + offset);
1134 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1135 struct mvpp2_tx_desc *tx_desc,
1136 dma_addr_t dma_addr)
1138 if (port->priv->hw_version == MVPP21) {
1139 tx_desc->pp21.buf_dma_addr = dma_addr;
1141 u64 val = (u64)dma_addr;
1143 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1144 tx_desc->pp22.buf_dma_addr_ptp |= val;
1148 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1149 struct mvpp2_tx_desc *tx_desc,
1152 if (port->priv->hw_version == MVPP21)
1153 tx_desc->pp21.data_size = size;
1155 tx_desc->pp22.data_size = size;
1158 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1159 struct mvpp2_tx_desc *tx_desc,
1162 if (port->priv->hw_version == MVPP21)
1163 tx_desc->pp21.phys_txq = txq;
1165 tx_desc->pp22.phys_txq = txq;
1168 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1169 struct mvpp2_tx_desc *tx_desc,
1170 unsigned int command)
1172 if (port->priv->hw_version == MVPP21)
1173 tx_desc->pp21.command = command;
1175 tx_desc->pp22.command = command;
1178 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1179 struct mvpp2_tx_desc *tx_desc,
1180 unsigned int offset)
1182 if (port->priv->hw_version == MVPP21)
1183 tx_desc->pp21.packet_offset = offset;
1185 tx_desc->pp22.packet_offset = offset;
1188 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1189 struct mvpp2_rx_desc *rx_desc)
1191 if (port->priv->hw_version == MVPP21)
1192 return rx_desc->pp21.buf_dma_addr;
1194 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1197 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1198 struct mvpp2_rx_desc *rx_desc)
1200 if (port->priv->hw_version == MVPP21)
1201 return rx_desc->pp21.buf_cookie;
1203 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1206 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1207 struct mvpp2_rx_desc *rx_desc)
1209 if (port->priv->hw_version == MVPP21)
1210 return rx_desc->pp21.data_size;
1212 return rx_desc->pp22.data_size;
1215 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1216 struct mvpp2_rx_desc *rx_desc)
1218 if (port->priv->hw_version == MVPP21)
1219 return rx_desc->pp21.status;
1221 return rx_desc->pp22.status;
1224 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1226 txq_pcpu->txq_get_index++;
1227 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1228 txq_pcpu->txq_get_index = 0;
1231 /* Get number of physical egress port */
1232 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1234 return MVPP2_MAX_TCONT + port->id;
1237 /* Get number of physical TXQ */
1238 static inline int mvpp2_txq_phys(int port, int txq)
1240 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1243 /* Parser configuration routines */
1245 /* Update parser tcam and sram hw entries */
1246 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1250 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1253 /* Clear entry invalidation bit */
1254 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1256 /* Write tcam index - indirect access */
1257 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1258 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1259 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1261 /* Write sram index - indirect access */
1262 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1263 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1264 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1269 /* Read tcam entry from hw */
1270 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1274 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1277 /* Write tcam index - indirect access */
1278 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1280 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1281 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1282 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1283 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1285 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1286 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1288 /* Write sram index - indirect access */
1289 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1290 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1291 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1296 /* Invalidate tcam hw entry */
1297 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1299 /* Write index - indirect access */
1300 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1301 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1302 MVPP2_PRS_TCAM_INV_MASK);
1305 /* Enable shadow table entry and set its lookup ID */
1306 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1308 priv->prs_shadow[index].valid = true;
1309 priv->prs_shadow[index].lu = lu;
1312 /* Update ri fields in shadow table entry */
1313 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1314 unsigned int ri, unsigned int ri_mask)
1316 priv->prs_shadow[index].ri_mask = ri_mask;
1317 priv->prs_shadow[index].ri = ri;
1320 /* Update lookup field in tcam sw entry */
1321 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1323 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1325 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1326 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1329 /* Update mask for single port in tcam sw entry */
1330 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1331 unsigned int port, bool add)
1333 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1336 pe->tcam.byte[enable_off] &= ~(1 << port);
1338 pe->tcam.byte[enable_off] |= 1 << port;
1341 /* Update port map in tcam sw entry */
1342 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1345 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1346 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1348 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1349 pe->tcam.byte[enable_off] &= ~port_mask;
1350 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1353 /* Obtain port map from tcam sw entry */
1354 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1356 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1358 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1361 /* Set byte of data and its enable bits in tcam sw entry */
1362 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1363 unsigned int offs, unsigned char byte,
1364 unsigned char enable)
1366 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1367 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1370 /* Get byte of data and its enable bits from tcam sw entry */
1371 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1372 unsigned int offs, unsigned char *byte,
1373 unsigned char *enable)
1375 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1376 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1379 /* Set ethertype in tcam sw entry */
1380 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1381 unsigned short ethertype)
1383 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1384 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1387 /* Set bits in sram sw entry */
1388 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1391 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1394 /* Clear bits in sram sw entry */
1395 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1398 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1401 /* Update ri bits in sram sw entry */
1402 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1403 unsigned int bits, unsigned int mask)
1407 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1408 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1410 if (!(mask & BIT(i)))
1414 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1416 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1418 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1422 /* Update ai bits in sram sw entry */
1423 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1424 unsigned int bits, unsigned int mask)
1427 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1429 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1431 if (!(mask & BIT(i)))
1435 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1437 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1439 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1443 /* Read ai bits from sram sw entry */
1444 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1447 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1448 int ai_en_off = ai_off + 1;
1449 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1451 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1452 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1457 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1460 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1463 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1465 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1466 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1467 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1470 /* In the sram sw entry set sign and value of the next lookup offset
1471 * and the offset value generated to the classifier
1473 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1478 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1481 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1485 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1486 (unsigned char)shift;
1488 /* Reset and set operation */
1489 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1490 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1491 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1493 /* Set base offset as current */
1494 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1497 /* In the sram sw entry set sign and value of the user defined offset
1498 * generated to the classifier
1500 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1501 unsigned int type, int offset,
1506 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1507 offset = 0 - offset;
1509 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1513 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1514 MVPP2_PRS_SRAM_UDF_MASK);
1515 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1516 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1517 MVPP2_PRS_SRAM_UDF_BITS)] &=
1518 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1519 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1520 MVPP2_PRS_SRAM_UDF_BITS)] |=
1521 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1523 /* Set offset type */
1524 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1525 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1526 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1528 /* Set offset operation */
1529 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1530 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1531 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1533 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1534 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1535 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1536 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1538 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1539 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1540 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1542 /* Set base offset as current */
1543 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1546 /* Find parser flow entry */
1547 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1549 struct mvpp2_prs_entry *pe;
1552 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1555 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1557 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1558 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1561 if (!priv->prs_shadow[tid].valid ||
1562 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1566 mvpp2_prs_hw_read(priv, pe);
1567 bits = mvpp2_prs_sram_ai_get(pe);
1569 /* Sram store classification lookup ID in AI bits [5:0] */
1570 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1578 /* Return first free tcam index, seeking from start to end */
1579 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1587 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1588 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1590 for (tid = start; tid <= end; tid++) {
1591 if (!priv->prs_shadow[tid].valid)
1598 /* Enable/disable dropping all mac da's */
1599 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1601 struct mvpp2_prs_entry pe;
1603 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1604 /* Entry exist - update port only */
1605 pe.index = MVPP2_PE_DROP_ALL;
1606 mvpp2_prs_hw_read(priv, &pe);
1608 /* Entry doesn't exist - create new */
1609 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1610 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1611 pe.index = MVPP2_PE_DROP_ALL;
1613 /* Non-promiscuous mode for all ports - DROP unknown packets */
1614 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1615 MVPP2_PRS_RI_DROP_MASK);
1617 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1618 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1620 /* Update shadow table */
1621 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1623 /* Mask all ports */
1624 mvpp2_prs_tcam_port_map_set(&pe, 0);
1627 /* Update port mask */
1628 mvpp2_prs_tcam_port_set(&pe, port, add);
1630 mvpp2_prs_hw_write(priv, &pe);
1633 /* Set port to promiscuous mode */
1634 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1636 struct mvpp2_prs_entry pe;
1638 /* Promiscuous mode - Accept unknown packets */
1640 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1641 /* Entry exist - update port only */
1642 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1643 mvpp2_prs_hw_read(priv, &pe);
1645 /* Entry doesn't exist - create new */
1646 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1647 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1648 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1650 /* Continue - set next lookup */
1651 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1653 /* Set result info bits */
1654 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1655 MVPP2_PRS_RI_L2_CAST_MASK);
1657 /* Shift to ethertype */
1658 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1659 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1661 /* Mask all ports */
1662 mvpp2_prs_tcam_port_map_set(&pe, 0);
1664 /* Update shadow table */
1665 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1668 /* Update port mask */
1669 mvpp2_prs_tcam_port_set(&pe, port, add);
1671 mvpp2_prs_hw_write(priv, &pe);
1674 /* Accept multicast */
1675 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1678 struct mvpp2_prs_entry pe;
1679 unsigned char da_mc;
1681 /* Ethernet multicast address first byte is
1682 * 0x01 for IPv4 and 0x33 for IPv6
1684 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1686 if (priv->prs_shadow[index].valid) {
1687 /* Entry exist - update port only */
1689 mvpp2_prs_hw_read(priv, &pe);
1691 /* Entry doesn't exist - create new */
1692 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1693 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1696 /* Continue - set next lookup */
1697 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1699 /* Set result info bits */
1700 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1701 MVPP2_PRS_RI_L2_CAST_MASK);
1703 /* Update tcam entry data first byte */
1704 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1706 /* Shift to ethertype */
1707 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1708 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1710 /* Mask all ports */
1711 mvpp2_prs_tcam_port_map_set(&pe, 0);
1713 /* Update shadow table */
1714 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1717 /* Update port mask */
1718 mvpp2_prs_tcam_port_set(&pe, port, add);
1720 mvpp2_prs_hw_write(priv, &pe);
1723 /* Parser per-port initialization */
1724 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1725 int lu_max, int offset)
1730 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1731 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1732 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1733 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1735 /* Set maximum number of loops for packet received from port */
1736 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1737 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1738 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1739 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1741 /* Set initial offset for packet header extraction for the first
1744 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1745 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1746 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1747 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1750 /* Default flow entries initialization for all ports */
1751 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1753 struct mvpp2_prs_entry pe;
1756 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1757 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1758 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1759 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1761 /* Mask all ports */
1762 mvpp2_prs_tcam_port_map_set(&pe, 0);
1765 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1766 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1768 /* Update shadow table and hw entry */
1769 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1770 mvpp2_prs_hw_write(priv, &pe);
1774 /* Set default entry for Marvell Header field */
1775 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1777 struct mvpp2_prs_entry pe;
1779 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1781 pe.index = MVPP2_PE_MH_DEFAULT;
1782 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1783 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1784 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1785 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1787 /* Unmask all ports */
1788 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1790 /* Update shadow table and hw entry */
1791 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1792 mvpp2_prs_hw_write(priv, &pe);
1795 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1796 * multicast MAC addresses
1798 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1800 struct mvpp2_prs_entry pe;
1802 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1804 /* Non-promiscuous mode for all ports - DROP unknown packets */
1805 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1806 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1808 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1809 MVPP2_PRS_RI_DROP_MASK);
1810 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1811 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1813 /* Unmask all ports */
1814 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1816 /* Update shadow table and hw entry */
1817 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1818 mvpp2_prs_hw_write(priv, &pe);
1820 /* place holders only - no ports */
1821 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1822 mvpp2_prs_mac_promisc_set(priv, 0, false);
1823 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1824 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1827 /* Match basic ethertypes */
1828 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1830 struct mvpp2_prs_entry pe;
1833 /* Ethertype: PPPoE */
1834 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1835 MVPP2_PE_LAST_FREE_TID);
1839 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1840 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1843 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1845 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1846 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1847 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1848 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1849 MVPP2_PRS_RI_PPPOE_MASK);
1851 /* Update shadow table and hw entry */
1852 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1853 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1854 priv->prs_shadow[pe.index].finish = false;
1855 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1856 MVPP2_PRS_RI_PPPOE_MASK);
1857 mvpp2_prs_hw_write(priv, &pe);
1859 /* Ethertype: ARP */
1860 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1861 MVPP2_PE_LAST_FREE_TID);
1865 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1866 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1869 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
1871 /* Generate flow in the next iteration*/
1872 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1873 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1874 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1875 MVPP2_PRS_RI_L3_PROTO_MASK);
1877 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1879 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1881 /* Update shadow table and hw entry */
1882 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1883 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1884 priv->prs_shadow[pe.index].finish = true;
1885 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1886 MVPP2_PRS_RI_L3_PROTO_MASK);
1887 mvpp2_prs_hw_write(priv, &pe);
1889 /* Ethertype: LBTD */
1890 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1891 MVPP2_PE_LAST_FREE_TID);
1895 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1896 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1899 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1901 /* Generate flow in the next iteration*/
1902 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1903 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1904 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1905 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1906 MVPP2_PRS_RI_CPU_CODE_MASK |
1907 MVPP2_PRS_RI_UDF3_MASK);
1909 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1911 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1913 /* Update shadow table and hw entry */
1914 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1915 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1916 priv->prs_shadow[pe.index].finish = true;
1917 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1918 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1919 MVPP2_PRS_RI_CPU_CODE_MASK |
1920 MVPP2_PRS_RI_UDF3_MASK);
1921 mvpp2_prs_hw_write(priv, &pe);
1923 /* Ethertype: IPv4 without options */
1924 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1925 MVPP2_PE_LAST_FREE_TID);
1929 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1930 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1933 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
1934 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1935 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
1936 MVPP2_PRS_IPV4_HEAD_MASK |
1937 MVPP2_PRS_IPV4_IHL_MASK);
1939 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1940 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1941 MVPP2_PRS_RI_L3_PROTO_MASK);
1942 /* Skip eth_type + 4 bytes of IP header */
1943 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
1944 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1946 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1948 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1950 /* Update shadow table and hw entry */
1951 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1952 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1953 priv->prs_shadow[pe.index].finish = false;
1954 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1955 MVPP2_PRS_RI_L3_PROTO_MASK);
1956 mvpp2_prs_hw_write(priv, &pe);
1958 /* Ethertype: IPv4 with options */
1959 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1960 MVPP2_PE_LAST_FREE_TID);
1966 /* Clear tcam data before updating */
1967 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
1968 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
1970 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1971 MVPP2_PRS_IPV4_HEAD,
1972 MVPP2_PRS_IPV4_HEAD_MASK);
1974 /* Clear ri before updating */
1975 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1976 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1977 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
1978 MVPP2_PRS_RI_L3_PROTO_MASK);
1980 /* Update shadow table and hw entry */
1981 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1982 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1983 priv->prs_shadow[pe.index].finish = false;
1984 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
1985 MVPP2_PRS_RI_L3_PROTO_MASK);
1986 mvpp2_prs_hw_write(priv, &pe);
1988 /* Ethertype: IPv6 without options */
1989 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1990 MVPP2_PE_LAST_FREE_TID);
1994 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1995 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1998 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2000 /* Skip DIP of IPV6 header */
2001 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2002 MVPP2_MAX_L3_ADDR_SIZE,
2003 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2004 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2005 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2006 MVPP2_PRS_RI_L3_PROTO_MASK);
2008 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2010 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2012 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2013 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2014 priv->prs_shadow[pe.index].finish = false;
2015 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2016 MVPP2_PRS_RI_L3_PROTO_MASK);
2017 mvpp2_prs_hw_write(priv, &pe);
2019 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2020 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2021 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2022 pe.index = MVPP2_PE_ETH_TYPE_UN;
2024 /* Unmask all ports */
2025 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2027 /* Generate flow in the next iteration*/
2028 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2029 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2030 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2031 MVPP2_PRS_RI_L3_PROTO_MASK);
2032 /* Set L3 offset even it's unknown L3 */
2033 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2035 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2037 /* Update shadow table and hw entry */
2038 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2039 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2040 priv->prs_shadow[pe.index].finish = true;
2041 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2042 MVPP2_PRS_RI_L3_PROTO_MASK);
2043 mvpp2_prs_hw_write(priv, &pe);
2048 /* Parser default initialization */
2049 static int mvpp2_prs_default_init(struct udevice *dev,
2054 /* Enable tcam table */
2055 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2057 /* Clear all tcam and sram entries */
2058 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2059 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2060 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2061 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2063 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2064 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2065 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2068 /* Invalidate all tcam entries */
2069 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2070 mvpp2_prs_hw_inv(priv, index);
2072 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2073 sizeof(struct mvpp2_prs_shadow),
2075 if (!priv->prs_shadow)
2078 /* Always start from lookup = 0 */
2079 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2080 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2081 MVPP2_PRS_PORT_LU_MAX, 0);
2083 mvpp2_prs_def_flow_init(priv);
2085 mvpp2_prs_mh_init(priv);
2087 mvpp2_prs_mac_init(priv);
2089 err = mvpp2_prs_etype_init(priv);
2096 /* Compare MAC DA with tcam entry data */
2097 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2098 const u8 *da, unsigned char *mask)
2100 unsigned char tcam_byte, tcam_mask;
2103 for (index = 0; index < ETH_ALEN; index++) {
2104 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2105 if (tcam_mask != mask[index])
2108 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2115 /* Find tcam entry with matched pair <MAC DA, port> */
2116 static struct mvpp2_prs_entry *
2117 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2118 unsigned char *mask, int udf_type)
2120 struct mvpp2_prs_entry *pe;
2123 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2126 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2128 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2129 for (tid = MVPP2_PE_FIRST_FREE_TID;
2130 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2131 unsigned int entry_pmap;
2133 if (!priv->prs_shadow[tid].valid ||
2134 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2135 (priv->prs_shadow[tid].udf != udf_type))
2139 mvpp2_prs_hw_read(priv, pe);
2140 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2142 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2151 /* Update parser's mac da entry */
2152 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2153 const u8 *da, bool add)
2155 struct mvpp2_prs_entry *pe;
2156 unsigned int pmap, len, ri;
2157 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2160 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2161 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2162 MVPP2_PRS_UDF_MAC_DEF);
2169 /* Create new TCAM entry */
2170 /* Find first range mac entry*/
2171 for (tid = MVPP2_PE_FIRST_FREE_TID;
2172 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2173 if (priv->prs_shadow[tid].valid &&
2174 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2175 (priv->prs_shadow[tid].udf ==
2176 MVPP2_PRS_UDF_MAC_RANGE))
2179 /* Go through the all entries from first to last */
2180 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2185 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2188 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2191 /* Mask all ports */
2192 mvpp2_prs_tcam_port_map_set(pe, 0);
2195 /* Update port mask */
2196 mvpp2_prs_tcam_port_set(pe, port, add);
2198 /* Invalidate the entry if no ports are left enabled */
2199 pmap = mvpp2_prs_tcam_port_map_get(pe);
2205 mvpp2_prs_hw_inv(priv, pe->index);
2206 priv->prs_shadow[pe->index].valid = false;
2211 /* Continue - set next lookup */
2212 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2214 /* Set match on DA */
2217 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2219 /* Set result info bits */
2220 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2222 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2223 MVPP2_PRS_RI_MAC_ME_MASK);
2224 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2225 MVPP2_PRS_RI_MAC_ME_MASK);
2227 /* Shift to ethertype */
2228 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2229 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2231 /* Update shadow table and hw entry */
2232 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2233 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2234 mvpp2_prs_hw_write(priv, pe);
2241 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2245 /* Remove old parser entry */
2246 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2251 /* Add new parser entry */
2252 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2256 /* Set addr in the device */
2257 memcpy(port->dev_addr, da, ETH_ALEN);
2262 /* Set prs flow for the port */
2263 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2265 struct mvpp2_prs_entry *pe;
2268 pe = mvpp2_prs_flow_find(port->priv, port->id);
2270 /* Such entry not exist */
2272 /* Go through the all entires from last to first */
2273 tid = mvpp2_prs_tcam_first_free(port->priv,
2274 MVPP2_PE_LAST_FREE_TID,
2275 MVPP2_PE_FIRST_FREE_TID);
2279 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2283 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2287 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2288 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2290 /* Update shadow table */
2291 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2294 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2295 mvpp2_prs_hw_write(port->priv, pe);
2301 /* Classifier configuration routines */
2303 /* Update classification flow table registers */
2304 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2305 struct mvpp2_cls_flow_entry *fe)
2307 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2308 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2309 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2310 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2313 /* Update classification lookup table register */
2314 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2315 struct mvpp2_cls_lookup_entry *le)
2319 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2320 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2321 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2324 /* Classifier default initialization */
2325 static void mvpp2_cls_init(struct mvpp2 *priv)
2327 struct mvpp2_cls_lookup_entry le;
2328 struct mvpp2_cls_flow_entry fe;
2331 /* Enable classifier */
2332 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2334 /* Clear classifier flow table */
2335 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2336 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2338 mvpp2_cls_flow_write(priv, &fe);
2341 /* Clear classifier lookup table */
2343 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2346 mvpp2_cls_lookup_write(priv, &le);
2349 mvpp2_cls_lookup_write(priv, &le);
2353 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2355 struct mvpp2_cls_lookup_entry le;
2358 /* Set way for the port */
2359 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2360 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2361 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2363 /* Pick the entry to be accessed in lookup ID decoding table
2364 * according to the way and lkpid.
2366 le.lkpid = port->id;
2370 /* Set initial CPU queue for receiving packets */
2371 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2372 le.data |= port->first_rxq;
2374 /* Disable classification engines */
2375 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2377 /* Update lookup ID table entry */
2378 mvpp2_cls_lookup_write(port->priv, &le);
2381 /* Set CPU queue number for oversize packets */
2382 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2386 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2387 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2389 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2390 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2392 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2393 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2394 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2397 /* Buffer Manager configuration routines */
2400 static int mvpp2_bm_pool_create(struct udevice *dev,
2402 struct mvpp2_bm_pool *bm_pool, int size)
2406 /* Number of buffer pointers must be a multiple of 16, as per
2407 * hardware constraints
2409 if (!IS_ALIGNED(size, 16))
2412 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2413 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2414 if (!bm_pool->virt_addr)
2417 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2418 MVPP2_BM_POOL_PTR_ALIGN)) {
2419 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2420 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2424 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2425 lower_32_bits(bm_pool->dma_addr));
2426 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2428 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2429 val |= MVPP2_BM_START_MASK;
2430 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2432 bm_pool->type = MVPP2_BM_FREE;
2433 bm_pool->size = size;
2434 bm_pool->pkt_size = 0;
2435 bm_pool->buf_num = 0;
2440 /* Set pool buffer size */
2441 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2442 struct mvpp2_bm_pool *bm_pool,
2447 bm_pool->buf_size = buf_size;
2449 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2450 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2453 /* Free all buffers from the pool */
2454 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2455 struct mvpp2_bm_pool *bm_pool)
2457 bm_pool->buf_num = 0;
2461 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2463 struct mvpp2_bm_pool *bm_pool)
2467 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2468 if (bm_pool->buf_num) {
2469 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2473 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2474 val |= MVPP2_BM_STOP_MASK;
2475 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2480 static int mvpp2_bm_pools_init(struct udevice *dev,
2484 struct mvpp2_bm_pool *bm_pool;
2486 /* Create all pools with maximum size */
2487 size = MVPP2_BM_POOL_SIZE_MAX;
2488 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2489 bm_pool = &priv->bm_pools[i];
2491 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2493 goto err_unroll_pools;
2494 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2499 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2500 for (i = i - 1; i >= 0; i--)
2501 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2505 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2509 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2510 /* Mask BM all interrupts */
2511 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2512 /* Clear BM cause register */
2513 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2516 /* Allocate and initialize BM pools */
2517 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2518 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2519 if (!priv->bm_pools)
2522 err = mvpp2_bm_pools_init(dev, priv);
2528 /* Attach long pool to rxq */
2529 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2530 int lrxq, int long_pool)
2535 /* Get queue physical ID */
2536 prxq = port->rxqs[lrxq]->id;
2538 if (port->priv->hw_version == MVPP21)
2539 mask = MVPP21_RXQ_POOL_LONG_MASK;
2541 mask = MVPP22_RXQ_POOL_LONG_MASK;
2543 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2545 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2546 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2549 /* Set pool number in a BM cookie */
2550 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2554 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2555 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2560 /* Get pool number from a BM cookie */
2561 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2563 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2566 /* Release buffer to BM */
2567 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2568 dma_addr_t buf_dma_addr,
2569 unsigned long buf_phys_addr)
2571 if (port->priv->hw_version == MVPP22) {
2574 if (sizeof(dma_addr_t) == 8)
2575 val |= upper_32_bits(buf_dma_addr) &
2576 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2578 if (sizeof(phys_addr_t) == 8)
2579 val |= (upper_32_bits(buf_phys_addr)
2580 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2581 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2583 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2586 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2587 * returned in the "cookie" field of the RX
2588 * descriptor. Instead of storing the virtual address, we
2589 * store the physical address
2591 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2592 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2595 /* Refill BM pool */
2596 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2597 dma_addr_t dma_addr,
2598 phys_addr_t phys_addr)
2600 int pool = mvpp2_bm_cookie_pool_get(bm);
2602 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2605 /* Allocate buffers for the pool */
2606 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2607 struct mvpp2_bm_pool *bm_pool, int buf_num)
2612 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2613 netdev_err(port->dev,
2614 "cannot allocate %d buffers for pool %d\n",
2615 buf_num, bm_pool->id);
2619 for (i = 0; i < buf_num; i++) {
2620 mvpp2_bm_pool_put(port, bm_pool->id,
2621 (dma_addr_t)buffer_loc.rx_buffer[i],
2622 (unsigned long)buffer_loc.rx_buffer[i]);
2626 /* Update BM driver with number of buffers added to pool */
2627 bm_pool->buf_num += i;
2628 bm_pool->in_use_thresh = bm_pool->buf_num / 4;
2633 /* Notify the driver that BM pool is being used as specific type and return the
2634 * pool pointer on success
2636 static struct mvpp2_bm_pool *
2637 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2640 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2643 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2644 netdev_err(port->dev, "mixing pool types is forbidden\n");
2648 if (new_pool->type == MVPP2_BM_FREE)
2649 new_pool->type = type;
2651 /* Allocate buffers in case BM pool is used as long pool, but packet
2652 * size doesn't match MTU or BM pool hasn't being used yet
2654 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2655 (new_pool->pkt_size == 0)) {
2658 /* Set default buffer number or free all the buffers in case
2659 * the pool is not empty
2661 pkts_num = new_pool->buf_num;
2663 pkts_num = type == MVPP2_BM_SWF_LONG ?
2664 MVPP2_BM_LONG_BUF_NUM :
2665 MVPP2_BM_SHORT_BUF_NUM;
2667 mvpp2_bm_bufs_free(NULL,
2668 port->priv, new_pool);
2670 new_pool->pkt_size = pkt_size;
2672 /* Allocate buffers for this pool */
2673 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2674 if (num != pkts_num) {
2675 dev_err(dev, "pool %d: %d of %d allocated\n",
2676 new_pool->id, num, pkts_num);
2681 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2682 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2687 /* Initialize pools for swf */
2688 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2692 if (!port->pool_long) {
2694 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2697 if (!port->pool_long)
2700 port->pool_long->port_map |= (1 << port->id);
2702 for (rxq = 0; rxq < rxq_number; rxq++)
2703 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2709 /* Port configuration routines */
2711 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2715 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2717 switch (port->phy_interface) {
2718 case PHY_INTERFACE_MODE_SGMII:
2719 val |= MVPP2_GMAC_INBAND_AN_MASK;
2721 case PHY_INTERFACE_MODE_RGMII:
2722 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2724 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2727 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2730 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2734 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2735 val |= MVPP2_GMAC_FC_ADV_EN;
2736 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2739 static void mvpp2_port_enable(struct mvpp2_port *port)
2743 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2744 val |= MVPP2_GMAC_PORT_EN_MASK;
2745 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2746 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2749 static void mvpp2_port_disable(struct mvpp2_port *port)
2753 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2754 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2755 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2758 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2759 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2763 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2764 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2765 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2768 /* Configure loopback port */
2769 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2773 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2775 if (port->speed == 1000)
2776 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2778 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2780 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2781 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2783 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2785 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2788 static void mvpp2_port_reset(struct mvpp2_port *port)
2792 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2793 ~MVPP2_GMAC_PORT_RESET_MASK;
2794 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2796 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2797 MVPP2_GMAC_PORT_RESET_MASK)
2801 /* Change maximum receive size of the port */
2802 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2806 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2807 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2808 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2809 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2810 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2813 /* Set defaults to the MVPP2 port */
2814 static void mvpp2_defaults_set(struct mvpp2_port *port)
2816 int tx_port_num, val, queue, ptxq, lrxq;
2818 if (port->priv->hw_version == MVPP21) {
2819 /* Configure port to loopback if needed */
2820 if (port->flags & MVPP2_F_LOOPBACK)
2821 mvpp2_port_loopback_set(port);
2823 /* Update TX FIFO MIN Threshold */
2824 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2825 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2826 /* Min. TX threshold must be less than minimal packet length */
2827 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2828 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2831 /* Disable Legacy WRR, Disable EJP, Release from reset */
2832 tx_port_num = mvpp2_egress_port(port);
2833 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2835 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2837 /* Close bandwidth for all queues */
2838 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
2839 ptxq = mvpp2_txq_phys(port->id, queue);
2840 mvpp2_write(port->priv,
2841 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
2844 /* Set refill period to 1 usec, refill tokens
2845 * and bucket size to maximum
2847 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
2848 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2849 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2850 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2851 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2852 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2853 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2854 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2856 /* Set MaximumLowLatencyPacketSize value to 256 */
2857 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2858 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2859 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2861 /* Enable Rx cache snoop */
2862 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2863 queue = port->rxqs[lrxq]->id;
2864 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2865 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2866 MVPP2_SNOOP_BUF_HDR_MASK;
2867 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2871 /* Enable/disable receiving packets */
2872 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2877 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2878 queue = port->rxqs[lrxq]->id;
2879 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2880 val &= ~MVPP2_RXQ_DISABLE_MASK;
2881 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2885 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2890 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2891 queue = port->rxqs[lrxq]->id;
2892 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2893 val |= MVPP2_RXQ_DISABLE_MASK;
2894 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2898 /* Enable transmit via physical egress queue
2899 * - HW starts take descriptors from DRAM
2901 static void mvpp2_egress_enable(struct mvpp2_port *port)
2905 int tx_port_num = mvpp2_egress_port(port);
2907 /* Enable all initialized TXs. */
2909 for (queue = 0; queue < txq_number; queue++) {
2910 struct mvpp2_tx_queue *txq = port->txqs[queue];
2912 if (txq->descs != NULL)
2913 qmap |= (1 << queue);
2916 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2917 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2920 /* Disable transmit via physical egress queue
2921 * - HW doesn't take descriptors from DRAM
2923 static void mvpp2_egress_disable(struct mvpp2_port *port)
2927 int tx_port_num = mvpp2_egress_port(port);
2929 /* Issue stop command for active channels only */
2930 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2931 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2932 MVPP2_TXP_SCHED_ENQ_MASK;
2934 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2935 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2937 /* Wait for all Tx activity to terminate. */
2940 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2941 netdev_warn(port->dev,
2942 "Tx stop timed out, status=0x%08x\n",
2949 /* Check port TX Command register that all
2950 * Tx queues are stopped
2952 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2953 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2956 /* Rx descriptors helper methods */
2958 /* Get number of Rx descriptors occupied by received packets */
2960 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2962 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2964 return val & MVPP2_RXQ_OCCUPIED_MASK;
2967 /* Update Rx queue status with the number of occupied and available
2968 * Rx descriptor slots.
2971 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2972 int used_count, int free_count)
2974 /* Decrement the number of used descriptors and increment count
2975 * increment the number of free descriptors.
2977 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2979 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2982 /* Get pointer to next RX descriptor to be processed by SW */
2983 static inline struct mvpp2_rx_desc *
2984 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2986 int rx_desc = rxq->next_desc_to_proc;
2988 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2989 prefetch(rxq->descs + rxq->next_desc_to_proc);
2990 return rxq->descs + rx_desc;
2993 /* Set rx queue offset */
2994 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2995 int prxq, int offset)
2999 /* Convert offset from bytes to units of 32 bytes */
3000 offset = offset >> 5;
3002 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3003 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3006 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3007 MVPP2_RXQ_PACKET_OFFSET_MASK);
3009 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3012 /* Obtain BM cookie information from descriptor */
3013 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3014 struct mvpp2_rx_desc *rx_desc)
3016 int cpu = smp_processor_id();
3019 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3020 MVPP2_RXD_BM_POOL_ID_MASK) >>
3021 MVPP2_RXD_BM_POOL_ID_OFFS;
3023 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3024 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3027 /* Tx descriptors helper methods */
3029 /* Get number of Tx descriptors waiting to be transmitted by HW */
3030 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3031 struct mvpp2_tx_queue *txq)
3035 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3036 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3038 return val & MVPP2_TXQ_PENDING_MASK;
3041 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3042 static struct mvpp2_tx_desc *
3043 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3045 int tx_desc = txq->next_desc_to_proc;
3047 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3048 return txq->descs + tx_desc;
3051 /* Update HW with number of aggregated Tx descriptors to be sent */
3052 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3054 /* aggregated access - relevant TXQ number is written in TX desc */
3055 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3058 /* Get number of sent descriptors and decrement counter.
3059 * The number of sent descriptors is returned.
3062 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3063 struct mvpp2_tx_queue *txq)
3067 /* Reading status reg resets transmitted descriptor counter */
3068 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3070 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3071 MVPP2_TRANSMITTED_COUNT_OFFSET;
3074 static void mvpp2_txq_sent_counter_clear(void *arg)
3076 struct mvpp2_port *port = arg;
3079 for (queue = 0; queue < txq_number; queue++) {
3080 int id = port->txqs[queue]->id;
3082 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3086 /* Set max sizes for Tx queues */
3087 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3090 int txq, tx_port_num;
3092 mtu = port->pkt_size * 8;
3093 if (mtu > MVPP2_TXP_MTU_MAX)
3094 mtu = MVPP2_TXP_MTU_MAX;
3096 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3099 /* Indirect access to registers */
3100 tx_port_num = mvpp2_egress_port(port);
3101 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3104 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3105 val &= ~MVPP2_TXP_MTU_MAX;
3107 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3109 /* TXP token size and all TXQs token size must be larger that MTU */
3110 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3111 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3114 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3116 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3119 for (txq = 0; txq < txq_number; txq++) {
3120 val = mvpp2_read(port->priv,
3121 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3122 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3126 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3128 mvpp2_write(port->priv,
3129 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
3135 /* Free Tx queue skbuffs */
3136 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
3137 struct mvpp2_tx_queue *txq,
3138 struct mvpp2_txq_pcpu *txq_pcpu, int num)
3142 for (i = 0; i < num; i++)
3143 mvpp2_txq_inc_get(txq_pcpu);
3146 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
3149 int queue = fls(cause) - 1;
3151 return port->rxqs[queue];
3154 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
3157 int queue = fls(cause) - 1;
3159 return port->txqs[queue];
3162 /* Rx/Tx queue initialization/cleanup methods */
3164 /* Allocate and initialize descriptors for aggr TXQ */
3165 static int mvpp2_aggr_txq_init(struct udevice *dev,
3166 struct mvpp2_tx_queue *aggr_txq,
3167 int desc_num, int cpu,
3172 /* Allocate memory for TX descriptors */
3173 aggr_txq->descs = buffer_loc.aggr_tx_descs;
3174 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
3175 if (!aggr_txq->descs)
3178 /* Make sure descriptor address is cache line size aligned */
3179 BUG_ON(aggr_txq->descs !=
3180 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3182 aggr_txq->last_desc = aggr_txq->size - 1;
3184 /* Aggr TXQ no reset WA */
3185 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
3186 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
3188 /* Set Tx descriptors queue starting address indirect
3191 if (priv->hw_version == MVPP21)
3192 txq_dma = aggr_txq->descs_dma;
3194 txq_dma = aggr_txq->descs_dma >>
3195 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
3197 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
3198 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
3203 /* Create a specified Rx queue */
3204 static int mvpp2_rxq_init(struct mvpp2_port *port,
3205 struct mvpp2_rx_queue *rxq)
3210 rxq->size = port->rx_ring_size;
3212 /* Allocate memory for RX descriptors */
3213 rxq->descs = buffer_loc.rx_descs;
3214 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
3218 BUG_ON(rxq->descs !=
3219 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3221 rxq->last_desc = rxq->size - 1;
3223 /* Zero occupied and non-occupied counters - direct access */
3224 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3226 /* Set Rx descriptors queue starting address - indirect access */
3227 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3228 if (port->priv->hw_version == MVPP21)
3229 rxq_dma = rxq->descs_dma;
3231 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
3232 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
3233 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
3234 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
3237 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
3239 /* Add number of descriptors ready for receiving packets */
3240 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
3245 /* Push packets received by the RXQ to BM pool */
3246 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3247 struct mvpp2_rx_queue *rxq)
3251 rx_received = mvpp2_rxq_received(port, rxq->id);
3255 for (i = 0; i < rx_received; i++) {
3256 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3257 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
3259 mvpp2_pool_refill(port, bm,
3260 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3261 mvpp2_rxdesc_cookie_get(port, rx_desc));
3263 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3266 /* Cleanup Rx queue */
3267 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3268 struct mvpp2_rx_queue *rxq)
3270 mvpp2_rxq_drop_pkts(port, rxq);
3274 rxq->next_desc_to_proc = 0;
3277 /* Clear Rx descriptors queue starting address and size;
3278 * free descriptor number
3280 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3281 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3282 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
3283 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
3286 /* Create and initialize a Tx queue */
3287 static int mvpp2_txq_init(struct mvpp2_port *port,
3288 struct mvpp2_tx_queue *txq)
3291 int cpu, desc, desc_per_txq, tx_port_num;
3292 struct mvpp2_txq_pcpu *txq_pcpu;
3294 txq->size = port->tx_ring_size;
3296 /* Allocate memory for Tx descriptors */
3297 txq->descs = buffer_loc.tx_descs;
3298 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
3302 /* Make sure descriptor address is cache line size aligned */
3303 BUG_ON(txq->descs !=
3304 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3306 txq->last_desc = txq->size - 1;
3308 /* Set Tx descriptors queue starting address - indirect access */
3309 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3310 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
3311 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
3312 MVPP2_TXQ_DESC_SIZE_MASK);
3313 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
3314 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
3315 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3316 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3317 val &= ~MVPP2_TXQ_PENDING_MASK;
3318 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
3320 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3321 * for each existing TXQ.
3322 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3323 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3326 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3327 (txq->log_id * desc_per_txq);
3329 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
3330 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3331 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3333 /* WRR / EJP configuration - indirect access */
3334 tx_port_num = mvpp2_egress_port(port);
3335 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3337 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3338 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3339 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3340 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3341 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3343 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3344 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3347 for_each_present_cpu(cpu) {
3348 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3349 txq_pcpu->size = txq->size;
3355 /* Free allocated TXQ resources */
3356 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3357 struct mvpp2_tx_queue *txq)
3361 txq->next_desc_to_proc = 0;
3364 /* Set minimum bandwidth for disabled TXQs */
3365 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
3367 /* Set Tx descriptors queue starting address and size */
3368 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3369 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
3370 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
3373 /* Cleanup Tx ports */
3374 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3376 struct mvpp2_txq_pcpu *txq_pcpu;
3377 int delay, pending, cpu;
3380 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3381 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
3382 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3383 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3385 /* The napi queue has been stopped so wait for all packets
3386 * to be transmitted.
3390 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3391 netdev_warn(port->dev,
3392 "port %d: cleaning queue %d timed out\n",
3393 port->id, txq->log_id);
3399 pending = mvpp2_txq_pend_desc_num_get(port, txq);
3402 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3403 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3405 for_each_present_cpu(cpu) {
3406 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3408 /* Release all packets */
3409 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3412 txq_pcpu->count = 0;
3413 txq_pcpu->txq_put_index = 0;
3414 txq_pcpu->txq_get_index = 0;
3418 /* Cleanup all Tx queues */
3419 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3421 struct mvpp2_tx_queue *txq;
3425 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3427 /* Reset Tx ports and delete Tx queues */
3428 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3429 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3431 for (queue = 0; queue < txq_number; queue++) {
3432 txq = port->txqs[queue];
3433 mvpp2_txq_clean(port, txq);
3434 mvpp2_txq_deinit(port, txq);
3437 mvpp2_txq_sent_counter_clear(port);
3439 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3440 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3443 /* Cleanup all Rx queues */
3444 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3448 for (queue = 0; queue < rxq_number; queue++)
3449 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3452 /* Init all Rx queues for port */
3453 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3457 for (queue = 0; queue < rxq_number; queue++) {
3458 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3465 mvpp2_cleanup_rxqs(port);
3469 /* Init all tx queues for port */
3470 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3472 struct mvpp2_tx_queue *txq;
3475 for (queue = 0; queue < txq_number; queue++) {
3476 txq = port->txqs[queue];
3477 err = mvpp2_txq_init(port, txq);
3482 mvpp2_txq_sent_counter_clear(port);
3486 mvpp2_cleanup_txqs(port);
3491 static void mvpp2_link_event(struct mvpp2_port *port)
3493 struct phy_device *phydev = port->phy_dev;
3494 int status_change = 0;
3498 if ((port->speed != phydev->speed) ||
3499 (port->duplex != phydev->duplex)) {
3502 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3503 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
3504 MVPP2_GMAC_CONFIG_GMII_SPEED |
3505 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3506 MVPP2_GMAC_AN_SPEED_EN |
3507 MVPP2_GMAC_AN_DUPLEX_EN);
3510 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
3512 if (phydev->speed == SPEED_1000)
3513 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
3514 else if (phydev->speed == SPEED_100)
3515 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
3517 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3519 port->duplex = phydev->duplex;
3520 port->speed = phydev->speed;
3524 if (phydev->link != port->link) {
3525 if (!phydev->link) {
3530 port->link = phydev->link;
3534 if (status_change) {
3536 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3537 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
3538 MVPP2_GMAC_FORCE_LINK_DOWN);
3539 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3540 mvpp2_egress_enable(port);
3541 mvpp2_ingress_enable(port);
3543 mvpp2_ingress_disable(port);
3544 mvpp2_egress_disable(port);
3549 /* Main RX/TX processing routines */
3551 /* Display more error info */
3552 static void mvpp2_rx_error(struct mvpp2_port *port,
3553 struct mvpp2_rx_desc *rx_desc)
3555 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3556 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3558 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3559 case MVPP2_RXD_ERR_CRC:
3560 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
3563 case MVPP2_RXD_ERR_OVERRUN:
3564 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
3567 case MVPP2_RXD_ERR_RESOURCE:
3568 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
3574 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3575 static int mvpp2_rx_refill(struct mvpp2_port *port,
3576 struct mvpp2_bm_pool *bm_pool,
3577 u32 bm, dma_addr_t dma_addr)
3579 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
3583 /* Set hw internals when starting port */
3584 static void mvpp2_start_dev(struct mvpp2_port *port)
3586 mvpp2_gmac_max_rx_size_set(port);
3587 mvpp2_txp_max_tx_size_set(port);
3589 mvpp2_port_enable(port);
3592 /* Set hw internals when stopping port */
3593 static void mvpp2_stop_dev(struct mvpp2_port *port)
3595 /* Stop new packets from arriving to RXQs */
3596 mvpp2_ingress_disable(port);
3598 mvpp2_egress_disable(port);
3599 mvpp2_port_disable(port);
3602 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
3604 struct phy_device *phy_dev;
3606 if (!port->init || port->link == 0) {
3607 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
3608 port->phy_interface);
3609 port->phy_dev = phy_dev;
3611 netdev_err(port->dev, "cannot connect to phy\n");
3614 phy_dev->supported &= PHY_GBIT_FEATURES;
3615 phy_dev->advertising = phy_dev->supported;
3617 port->phy_dev = phy_dev;
3622 phy_config(phy_dev);
3623 phy_startup(phy_dev);
3624 if (!phy_dev->link) {
3625 printf("%s: No link\n", phy_dev->dev->name);
3631 mvpp2_egress_enable(port);
3632 mvpp2_ingress_enable(port);
3638 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
3640 unsigned char mac_bcast[ETH_ALEN] = {
3641 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3644 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
3646 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3649 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
3650 port->dev_addr, true);
3652 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
3655 err = mvpp2_prs_def_flow(port);
3657 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3661 /* Allocate the Rx/Tx queues */
3662 err = mvpp2_setup_rxqs(port);
3664 netdev_err(port->dev, "cannot allocate Rx queues\n");
3668 err = mvpp2_setup_txqs(port);
3670 netdev_err(port->dev, "cannot allocate Tx queues\n");
3674 err = mvpp2_phy_connect(dev, port);
3678 mvpp2_link_event(port);
3680 mvpp2_start_dev(port);
3685 /* No Device ops here in U-Boot */
3687 /* Driver initialization */
3689 static void mvpp2_port_power_up(struct mvpp2_port *port)
3691 struct mvpp2 *priv = port->priv;
3693 mvpp2_port_mii_set(port);
3694 mvpp2_port_periodic_xon_disable(port);
3695 if (priv->hw_version == MVPP21)
3696 mvpp2_port_fc_adv_enable(port);
3697 mvpp2_port_reset(port);
3700 /* Initialize port HW */
3701 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
3703 struct mvpp2 *priv = port->priv;
3704 struct mvpp2_txq_pcpu *txq_pcpu;
3705 int queue, cpu, err;
3707 if (port->first_rxq + rxq_number >
3708 MVPP2_MAX_PORTS * priv->max_port_rxqs)
3712 mvpp2_egress_disable(port);
3713 mvpp2_port_disable(port);
3715 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
3720 /* Associate physical Tx queues to this port and initialize.
3721 * The mapping is predefined.
3723 for (queue = 0; queue < txq_number; queue++) {
3724 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
3725 struct mvpp2_tx_queue *txq;
3727 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
3731 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
3736 txq->id = queue_phy_id;
3737 txq->log_id = queue;
3738 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
3739 for_each_present_cpu(cpu) {
3740 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3741 txq_pcpu->cpu = cpu;
3744 port->txqs[queue] = txq;
3747 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
3752 /* Allocate and initialize Rx queue for this port */
3753 for (queue = 0; queue < rxq_number; queue++) {
3754 struct mvpp2_rx_queue *rxq;
3756 /* Map physical Rx queue to port's logical Rx queue */
3757 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
3760 /* Map this Rx queue to a physical queue */
3761 rxq->id = port->first_rxq + queue;
3762 rxq->port = port->id;
3763 rxq->logic_rxq = queue;
3765 port->rxqs[queue] = rxq;
3768 /* Configure Rx queue group interrupt for this port */
3769 if (priv->hw_version == MVPP21) {
3770 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
3775 val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
3776 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
3778 val = (CONFIG_MV_ETH_RXQ <<
3779 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
3780 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
3783 /* Create Rx descriptor rings */
3784 for (queue = 0; queue < rxq_number; queue++) {
3785 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3787 rxq->size = port->rx_ring_size;
3788 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
3789 rxq->time_coal = MVPP2_RX_COAL_USEC;
3792 mvpp2_ingress_disable(port);
3794 /* Port default configuration */
3795 mvpp2_defaults_set(port);
3797 /* Port's classifier configuration */
3798 mvpp2_cls_oversize_rxq_set(port);
3799 mvpp2_cls_port_config(port);
3801 /* Provide an initial Rx packet size */
3802 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
3804 /* Initialize pools for swf */
3805 err = mvpp2_swf_bm_pool_init(port);
3812 /* Ports initialization */
3813 static int mvpp2_port_probe(struct udevice *dev,
3814 struct mvpp2_port *port,
3821 const char *phy_mode_str;
3823 int priv_common_regs_num = 2;
3826 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
3828 dev_err(&pdev->dev, "missing phy\n");
3832 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
3834 phy_mode = phy_get_interface_by_name(phy_mode_str);
3835 if (phy_mode == -1) {
3836 dev_err(&pdev->dev, "incorrect phy mode\n");
3840 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
3842 dev_err(&pdev->dev, "missing port-id value\n");
3846 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
3850 if (priv->hw_version == MVPP21)
3851 port->first_rxq = port->id * rxq_number;
3853 port->first_rxq = port->id * priv->max_port_rxqs;
3854 port->phy_node = phy_node;
3855 port->phy_interface = phy_mode;
3856 port->phyaddr = phyaddr;
3858 if (priv->hw_version == MVPP21) {
3859 port->base = (void __iomem *)dev_get_addr_index(
3860 dev->parent, priv_common_regs_num + id);
3861 if (IS_ERR(port->base))
3862 return PTR_ERR(port->base);
3866 gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
3869 dev_err(&pdev->dev, "missing gop-port-id value\n");
3873 port->base = priv->iface_base + MVPP22_PORT_BASE +
3874 gop_id * MVPP22_PORT_OFFSET;
3877 port->tx_ring_size = MVPP2_MAX_TXD;
3878 port->rx_ring_size = MVPP2_MAX_RXD;
3880 err = mvpp2_port_init(dev, port);
3882 dev_err(&pdev->dev, "failed to init port %d\n", id);
3885 mvpp2_port_power_up(port);
3887 priv->port_list[id] = port;
3891 /* Initialize decoding windows */
3892 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
3898 for (i = 0; i < 6; i++) {
3899 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
3900 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
3903 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
3908 for (i = 0; i < dram->num_cs; i++) {
3909 const struct mbus_dram_window *cs = dram->cs + i;
3911 mvpp2_write(priv, MVPP2_WIN_BASE(i),
3912 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
3913 dram->mbus_dram_target_id);
3915 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
3916 (cs->size - 1) & 0xffff0000);
3918 win_enable |= (1 << i);
3921 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
3924 /* Initialize Rx FIFO's */
3925 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
3929 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
3930 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3931 MVPP2_RX_FIFO_PORT_DATA_SIZE);
3932 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3933 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
3936 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
3937 MVPP2_RX_FIFO_PORT_MIN_PKT);
3938 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
3941 static void mvpp2_axi_init(struct mvpp2 *priv)
3943 u32 val, rdval, wrval;
3945 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
3947 /* AXI Bridge Configuration */
3949 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
3950 << MVPP22_AXI_ATTR_CACHE_OFFS;
3951 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3952 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
3954 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
3955 << MVPP22_AXI_ATTR_CACHE_OFFS;
3956 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3957 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
3960 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
3961 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
3964 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
3965 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
3966 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
3967 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
3970 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
3971 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
3973 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
3974 << MVPP22_AXI_CODE_CACHE_OFFS;
3975 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
3976 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3977 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
3978 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
3980 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
3981 << MVPP22_AXI_CODE_CACHE_OFFS;
3982 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3983 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3985 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
3987 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
3988 << MVPP22_AXI_CODE_CACHE_OFFS;
3989 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3990 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3992 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
3995 /* Initialize network controller common part HW */
3996 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
3998 const struct mbus_dram_target_info *dram_target_info;
4002 /* Checks for hardware constraints (U-Boot uses only one rxq) */
4003 if ((rxq_number > priv->max_port_rxqs) ||
4004 (txq_number > MVPP2_MAX_TXQ)) {
4005 dev_err(&pdev->dev, "invalid queue size parameter\n");
4009 /* MBUS windows configuration */
4010 dram_target_info = mvebu_mbus_dram_info();
4011 if (dram_target_info)
4012 mvpp2_conf_mbus_windows(dram_target_info, priv);
4014 if (priv->hw_version == MVPP22)
4015 mvpp2_axi_init(priv);
4017 /* Disable HW PHY polling */
4018 if (priv->hw_version == MVPP21) {
4019 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4020 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4021 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4023 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4024 val &= ~MVPP22_SMI_POLLING_EN;
4025 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4028 /* Allocate and initialize aggregated TXQs */
4029 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
4030 sizeof(struct mvpp2_tx_queue),
4032 if (!priv->aggr_txqs)
4035 for_each_present_cpu(i) {
4036 priv->aggr_txqs[i].id = i;
4037 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
4038 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
4039 MVPP2_AGGR_TXQ_SIZE, i, priv);
4045 mvpp2_rx_fifo_init(priv);
4047 /* Reset Rx queue group interrupt configuration */
4048 for (i = 0; i < MVPP2_MAX_PORTS; i++) {
4049 if (priv->hw_version == MVPP21) {
4050 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
4056 val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
4057 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4059 val = (CONFIG_MV_ETH_RXQ <<
4060 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
4062 MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4066 if (priv->hw_version == MVPP21)
4067 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
4068 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
4070 /* Allow cache snoop when transmiting packets */
4071 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
4073 /* Buffer Manager initialization */
4074 err = mvpp2_bm_init(dev, priv);
4078 /* Parser default initialization */
4079 err = mvpp2_prs_default_init(dev, priv);
4083 /* Classifier default initialization */
4084 mvpp2_cls_init(priv);
4089 /* SMI / MDIO functions */
4091 static int smi_wait_ready(struct mvpp2 *priv)
4093 u32 timeout = MVPP2_SMI_TIMEOUT;
4096 /* wait till the SMI is not busy */
4098 /* read smi register */
4099 smi_reg = readl(priv->mdio_base);
4100 if (timeout-- == 0) {
4101 printf("Error: SMI busy timeout\n");
4104 } while (smi_reg & MVPP2_SMI_BUSY);
4110 * mpp2_mdio_read - miiphy_read callback function.
4112 * Returns 16bit phy register value, or 0xffff on error
4114 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
4116 struct mvpp2 *priv = bus->priv;
4120 /* check parameters */
4121 if (addr > MVPP2_PHY_ADDR_MASK) {
4122 printf("Error: Invalid PHY address %d\n", addr);
4126 if (reg > MVPP2_PHY_REG_MASK) {
4127 printf("Err: Invalid register offset %d\n", reg);
4131 /* wait till the SMI is not busy */
4132 if (smi_wait_ready(priv) < 0)
4135 /* fill the phy address and regiser offset and read opcode */
4136 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4137 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
4138 | MVPP2_SMI_OPCODE_READ;
4140 /* write the smi register */
4141 writel(smi_reg, priv->mdio_base);
4143 /* wait till read value is ready */
4144 timeout = MVPP2_SMI_TIMEOUT;
4147 /* read smi register */
4148 smi_reg = readl(priv->mdio_base);
4149 if (timeout-- == 0) {
4150 printf("Err: SMI read ready timeout\n");
4153 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
4155 /* Wait for the data to update in the SMI register */
4156 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
4159 return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
4163 * mpp2_mdio_write - miiphy_write callback function.
4165 * Returns 0 if write succeed, -EINVAL on bad parameters
4168 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
4171 struct mvpp2 *priv = bus->priv;
4174 /* check parameters */
4175 if (addr > MVPP2_PHY_ADDR_MASK) {
4176 printf("Error: Invalid PHY address %d\n", addr);
4180 if (reg > MVPP2_PHY_REG_MASK) {
4181 printf("Err: Invalid register offset %d\n", reg);
4185 /* wait till the SMI is not busy */
4186 if (smi_wait_ready(priv) < 0)
4189 /* fill the phy addr and reg offset and write opcode and data */
4190 smi_reg = value << MVPP2_SMI_DATA_OFFS;
4191 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4192 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
4193 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
4195 /* write the smi register */
4196 writel(smi_reg, priv->mdio_base);
4201 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
4203 struct mvpp2_port *port = dev_get_priv(dev);
4204 struct mvpp2_rx_desc *rx_desc;
4205 struct mvpp2_bm_pool *bm_pool;
4206 dma_addr_t dma_addr;
4208 int pool, rx_bytes, err;
4210 struct mvpp2_rx_queue *rxq;
4211 u32 cause_rx_tx, cause_rx, cause_misc;
4214 cause_rx_tx = mvpp2_read(port->priv,
4215 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4216 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4217 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4218 if (!cause_rx_tx && !cause_misc)
4221 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
4223 /* Process RX packets */
4224 cause_rx |= port->pending_cause_rx;
4225 rxq = mvpp2_get_rx_queue(port, cause_rx);
4227 /* Get number of received packets and clamp the to-do */
4228 rx_received = mvpp2_rxq_received(port, rxq->id);
4230 /* Return if no packets are received */
4234 rx_desc = mvpp2_rxq_next_desc_get(rxq);
4235 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
4236 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
4237 rx_bytes -= MVPP2_MH_SIZE;
4238 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
4240 bm = mvpp2_bm_cookie_build(port, rx_desc);
4241 pool = mvpp2_bm_cookie_pool_get(bm);
4242 bm_pool = &port->priv->bm_pools[pool];
4244 /* In case of an error, release the requested buffer pointer
4245 * to the Buffer Manager. This request process is controlled
4246 * by the hardware, and the information about the buffer is
4247 * comprised by the RX descriptor.
4249 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
4250 mvpp2_rx_error(port, rx_desc);
4251 /* Return the buffer to the pool */
4252 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
4256 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
4258 netdev_err(port->dev, "failed to refill BM pools\n");
4262 /* Update Rx queue management counters */
4264 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
4266 /* give packet to stack - skip on first n bytes */
4267 data = (u8 *)dma_addr + 2 + 32;
4273 * No cache invalidation needed here, since the rx_buffer's are
4274 * located in a uncached memory region
4282 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4287 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4288 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4290 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4292 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4293 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4296 static int mvpp2_send(struct udevice *dev, void *packet, int length)
4298 struct mvpp2_port *port = dev_get_priv(dev);
4299 struct mvpp2_tx_queue *txq, *aggr_txq;
4300 struct mvpp2_tx_desc *tx_desc;
4304 txq = port->txqs[0];
4305 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
4307 /* Get a descriptor for the first part of the packet */
4308 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4309 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4310 mvpp2_txdesc_size_set(port, tx_desc, length);
4311 mvpp2_txdesc_offset_set(port, tx_desc,
4312 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
4313 mvpp2_txdesc_dma_addr_set(port, tx_desc,
4314 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
4315 /* First and Last descriptor */
4316 mvpp2_txdesc_cmd_set(port, tx_desc,
4317 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
4318 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
4321 flush_dcache_range((unsigned long)packet,
4322 (unsigned long)packet + ALIGN(length, PKTALIGN));
4324 /* Enable transmit */
4326 mvpp2_aggr_txq_pend_desc_add(port, 1);
4328 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4332 if (timeout++ > 10000) {
4333 printf("timeout: packet not sent from aggregated to phys TXQ\n");
4336 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
4339 /* Enable TXQ drain */
4340 mvpp2_txq_drain(port, txq, 1);
4344 if (timeout++ > 10000) {
4345 printf("timeout: packet not sent\n");
4348 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4351 /* Disable TXQ drain */
4352 mvpp2_txq_drain(port, txq, 0);
4357 static int mvpp2_start(struct udevice *dev)
4359 struct eth_pdata *pdata = dev_get_platdata(dev);
4360 struct mvpp2_port *port = dev_get_priv(dev);
4362 /* Load current MAC address */
4363 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
4365 /* Reconfigure parser accept the original MAC address */
4366 mvpp2_prs_update_mac_da(port, port->dev_addr);
4368 mvpp2_port_power_up(port);
4370 mvpp2_open(dev, port);
4375 static void mvpp2_stop(struct udevice *dev)
4377 struct mvpp2_port *port = dev_get_priv(dev);
4379 mvpp2_stop_dev(port);
4380 mvpp2_cleanup_rxqs(port);
4381 mvpp2_cleanup_txqs(port);
4384 static int mvpp2_base_probe(struct udevice *dev)
4386 struct mvpp2 *priv = dev_get_priv(dev);
4387 struct mii_dev *bus;
4392 /* Save hw-version */
4393 priv->hw_version = dev_get_driver_data(dev);
4396 * U-Boot special buffer handling:
4398 * Allocate buffer area for descs and rx_buffers. This is only
4399 * done once for all interfaces. As only one interface can
4400 * be active. Make this area DMA-safe by disabling the D-cache
4403 /* Align buffer area for descs and rx_buffers to 1MiB */
4404 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
4405 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
4406 BD_SPACE, DCACHE_OFF);
4408 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
4409 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
4411 buffer_loc.tx_descs =
4412 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
4413 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
4415 buffer_loc.rx_descs =
4416 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
4417 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
4419 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
4420 buffer_loc.bm_pool[i] =
4421 (unsigned long *)((unsigned long)bd_space + size);
4422 if (priv->hw_version == MVPP21)
4423 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
4425 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
4428 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
4429 buffer_loc.rx_buffer[i] =
4430 (unsigned long *)((unsigned long)bd_space + size);
4431 size += RX_BUFFER_SIZE;
4434 /* Clear the complete area so that all descriptors are cleared */
4435 memset(bd_space, 0, size);
4437 /* Save base addresses for later use */
4438 priv->base = (void *)dev_get_addr_index(dev, 0);
4439 if (IS_ERR(priv->base))
4440 return PTR_ERR(priv->base);
4442 if (priv->hw_version == MVPP21) {
4443 priv->lms_base = (void *)dev_get_addr_index(dev, 1);
4444 if (IS_ERR(priv->lms_base))
4445 return PTR_ERR(priv->lms_base);
4447 priv->mdio_base = priv->lms_base + MVPP21_SMI;
4449 priv->iface_base = (void *)dev_get_addr_index(dev, 1);
4450 if (IS_ERR(priv->iface_base))
4451 return PTR_ERR(priv->iface_base);
4453 priv->mdio_base = priv->iface_base + MVPP22_SMI;
4456 if (priv->hw_version == MVPP21)
4457 priv->max_port_rxqs = 8;
4459 priv->max_port_rxqs = 32;
4461 /* Finally create and register the MDIO bus driver */
4464 printf("Failed to allocate MDIO bus\n");
4468 bus->read = mpp2_mdio_read;
4469 bus->write = mpp2_mdio_write;
4470 snprintf(bus->name, sizeof(bus->name), dev->name);
4471 bus->priv = (void *)priv;
4474 return mdio_register(bus);
4477 static int mvpp2_probe(struct udevice *dev)
4479 struct mvpp2_port *port = dev_get_priv(dev);
4480 struct mvpp2 *priv = dev_get_priv(dev->parent);
4483 /* Only call the probe function for the parent once */
4484 if (!priv->probe_done) {
4485 err = mvpp2_base_probe(dev->parent);
4486 priv->probe_done = 1;
4488 /* Initialize network controller */
4489 err = mvpp2_init(dev, priv);
4491 dev_err(&pdev->dev, "failed to initialize controller\n");
4495 return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
4498 static const struct eth_ops mvpp2_ops = {
4499 .start = mvpp2_start,
4505 static struct driver mvpp2_driver = {
4508 .probe = mvpp2_probe,
4510 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
4511 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
4515 * Use a MISC device to bind the n instances (child nodes) of the
4516 * network base controller in UCLASS_ETH.
4518 static int mvpp2_base_bind(struct udevice *parent)
4520 const void *blob = gd->fdt_blob;
4521 int node = dev_of_offset(parent);
4522 struct uclass_driver *drv;
4523 struct udevice *dev;
4524 struct eth_pdata *plat;
4530 /* Lookup eth driver */
4531 drv = lists_uclass_lookup(UCLASS_ETH);
4533 puts("Cannot find eth driver\n");
4537 base_id_add = base_id;
4539 fdt_for_each_subnode(subnode, blob, node) {
4540 /* Increment base_id for all subnodes, also the disabled ones */
4543 /* Skip disabled ports */
4544 if (!fdtdec_get_is_enabled(blob, subnode))
4547 plat = calloc(1, sizeof(*plat));
4551 id = fdtdec_get_int(blob, subnode, "port-id", -1);
4554 name = calloc(1, 16);
4555 sprintf(name, "mvpp2-%d", id);
4557 /* Create child device UCLASS_ETH and bind it */
4558 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
4559 dev_set_of_offset(dev, subnode);
4565 static const struct udevice_id mvpp2_ids[] = {
4567 .compatible = "marvell,armada-375-pp2",
4571 .compatible = "marvell,armada-7k-pp22",
4577 U_BOOT_DRIVER(mvpp2_base) = {
4578 .name = "mvpp2_base",
4580 .of_match = mvpp2_ids,
4581 .bind = mvpp2_base_bind,
4582 .priv_auto_alloc_size = sizeof(struct mvpp2),