git.sur5r.net Git - u-boot/blob - drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <dm/pinctrl.h>
  10 #include <linux/libfdt.h>
  11 #include <asm/io.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 struct single_pdata {
  16         fdt_addr_t base;        /* first configuration register */
  17         int offset;             /* index of last configuration register */
  18         u32 mask;               /* configuration-value mask bits */
  19         int width;              /* configuration register bit width */
  20 };
  21
  22 struct single_fdt_pin_cfg {
  23         fdt32_t reg;            /* configuration register offset */
  24         fdt32_t val;            /* configuration register value */
  25 };
  26
  27 /**
  28  * single_configure_pins() - Configure pins based on FDT data
  29  *
  30  * @dev: Pointer to single pin configuration device which is the parent of
  31  *       the pins node holding the pin configuration data.
  32  * @pins: Pointer to the first element of an array of register/value pairs
  33  *        of type 'struct single_fdt_pin_cfg'. Each such pair describes the
  34  *        the pin to be configured and the value to be used for configuration.
  35  *        This pointer points to a 'pinctrl-single,pins' property in the
  36  *        device-tree.
  37  * @size: Size of the 'pins' array in bytes.
  38  *        The number of register/value pairs in the 'pins' array therefore
  39  *        equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
  40  */
  41 static int single_configure_pins(struct udevice *dev,
  42                                  const struct single_fdt_pin_cfg *pins,
  43                                  int size)
  44 {
  45         struct single_pdata *pdata = dev->platdata;
  46         int count = size / sizeof(struct single_fdt_pin_cfg);
  47         int n, reg;
  48         u32 val;
  49
  50         for (n = 0; n < count; n++, pins++) {
  51                 reg = fdt32_to_cpu(pins->reg);
  52                 if ((reg < 0) || (reg > pdata->offset)) {
  53                         dev_dbg(dev, "  invalid register offset 0x%08x\n", reg);
  54                         continue;
  55                 }
  56                 reg += pdata->base;
  57                 val = fdt32_to_cpu(pins->val) & pdata->mask;
  58                 switch (pdata->width) {
  59                 case 16:
  60                         writew((readw(reg) & ~pdata->mask) | val, reg);
  61                         break;
  62                 case 32:
  63                         writel((readl(reg) & ~pdata->mask) | val, reg);
  64                         break;
  65                 default:
  66                         dev_warn(dev, "unsupported register width %i\n",
  67                                  pdata->width);
  68                         continue;
  69                 }
  70                 dev_dbg(dev, "  reg/val 0x%08x/0x%08x\n",reg, val);
  71         }
  72         return 0;
  73 }
  74
  75 static int single_set_state(struct udevice *dev,
  76                             struct udevice *config)
  77 {
  78         const void *fdt = gd->fdt_blob;
  79         const struct single_fdt_pin_cfg *prop;
  80         int len;
  81
  82         prop = fdt_getprop(fdt, dev_of_offset(config), "pinctrl-single,pins",
  83                            &len);
  84         if (prop) {
  85                 dev_dbg(dev, "configuring pins for %s\n", config->name);
  86                 if (len % sizeof(struct single_fdt_pin_cfg)) {
  87                         dev_dbg(dev, "  invalid pin configuration in fdt\n");
  88                         return -FDT_ERR_BADSTRUCTURE;
  89                 }
  90                 single_configure_pins(dev, prop, len);
  91                 len = 0;
  92         }
  93
  94         return len;
  95 }
  96
  97 static int single_ofdata_to_platdata(struct udevice *dev)
  98 {
  99         fdt_addr_t addr;
 100         u32 of_reg[2];
 101         int res;
 102         struct single_pdata *pdata = dev->platdata;
 103
 104         pdata->width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 105                                       "pinctrl-single,register-width", 0);
 106
 107         res = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
 108                                    "reg", of_reg, 2);
 109         if (res)
 110                 return res;
 111         pdata->offset = of_reg[1] - pdata->width / 8;
 112
 113         addr = devfdt_get_addr(dev);
 114         if (addr == FDT_ADDR_T_NONE) {
 115                 dev_dbg(dev, "no valid base register address\n");
 116                 return -EINVAL;
 117         }
 118         pdata->base = addr;
 119
 120         pdata->mask = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 121                                      "pinctrl-single,function-mask",
 122                                      0xffffffff);
 123         return 0;
 124 }
 125
 126 const struct pinctrl_ops single_pinctrl_ops = {
 127         .set_state = single_set_state,
 128 };
 129
 130 static const struct udevice_id single_pinctrl_match[] = {
 131         { .compatible = "pinctrl-single" },
 132         { /* sentinel */ }
 133 };
 134
 135 U_BOOT_DRIVER(single_pinctrl) = {
 136         .name = "single-pinctrl",
 137         .id = UCLASS_PINCTRL,
 138         .of_match = single_pinctrl_match,
 139         .ops = &single_pinctrl_ops,
 140         .flags = DM_FLAG_PRE_RELOC,
 141         .platdata_auto_alloc_size = sizeof(struct single_pdata),
 142         .ofdata_to_platdata = single_ofdata_to_platdata,
 143 };