git.sur5r.net Git - u-boot/blob - drivers/pinctrl/renesas/pfc-r8a7796.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A7796 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  *
   7  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   8  *
   9  * R-Car Gen3 processor support - PFC hardware block.
  10  *
  11  * Copyright (C) 2015  Renesas Electronics Corporation
  12  */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/kernel.h>
  19
  20 #include "sh_pfc.h"
  21
  22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  23                    SH_PFC_PIN_CFG_PULL_UP | \
  24                    SH_PFC_PIN_CFG_PULL_DOWN)
  25
  26 #define CPU_ALL_PORT(fn, sfx)                                           \
  27         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  30         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  31         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  34         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  35         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  36         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  37         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  38         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  39 /*
  40  * F_() : just information
  41  * FM() : macro for FN_xxx / xxx_MARK
  42  */
  43
  44 /* GPSR0 */
  45 #define GPSR0_15        F_(D15,                 IP7_11_8)
  46 #define GPSR0_14        F_(D14,                 IP7_7_4)
  47 #define GPSR0_13        F_(D13,                 IP7_3_0)
  48 #define GPSR0_12        F_(D12,                 IP6_31_28)
  49 #define GPSR0_11        F_(D11,                 IP6_27_24)
  50 #define GPSR0_10        F_(D10,                 IP6_23_20)
  51 #define GPSR0_9         F_(D9,                  IP6_19_16)
  52 #define GPSR0_8         F_(D8,                  IP6_15_12)
  53 #define GPSR0_7         F_(D7,                  IP6_11_8)
  54 #define GPSR0_6         F_(D6,                  IP6_7_4)
  55 #define GPSR0_5         F_(D5,                  IP6_3_0)
  56 #define GPSR0_4         F_(D4,                  IP5_31_28)
  57 #define GPSR0_3         F_(D3,                  IP5_27_24)
  58 #define GPSR0_2         F_(D2,                  IP5_23_20)
  59 #define GPSR0_1         F_(D1,                  IP5_19_16)
  60 #define GPSR0_0         F_(D0,                  IP5_15_12)
  61
  62 /* GPSR1 */
  63 #define GPSR1_28        FM(CLKOUT)
  64 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  65 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  66 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  67 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  68 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  69 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  70 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  71 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  72 #define GPSR1_19        F_(A19,                 IP4_11_8)
  73 #define GPSR1_18        F_(A18,                 IP4_7_4)
  74 #define GPSR1_17        F_(A17,                 IP4_3_0)
  75 #define GPSR1_16        F_(A16,                 IP3_31_28)
  76 #define GPSR1_15        F_(A15,                 IP3_27_24)
  77 #define GPSR1_14        F_(A14,                 IP3_23_20)
  78 #define GPSR1_13        F_(A13,                 IP3_19_16)
  79 #define GPSR1_12        F_(A12,                 IP3_15_12)
  80 #define GPSR1_11        F_(A11,                 IP3_11_8)
  81 #define GPSR1_10        F_(A10,                 IP3_7_4)
  82 #define GPSR1_9         F_(A9,                  IP3_3_0)
  83 #define GPSR1_8         F_(A8,                  IP2_31_28)
  84 #define GPSR1_7         F_(A7,                  IP2_27_24)
  85 #define GPSR1_6         F_(A6,                  IP2_23_20)
  86 #define GPSR1_5         F_(A5,                  IP2_19_16)
  87 #define GPSR1_4         F_(A4,                  IP2_15_12)
  88 #define GPSR1_3         F_(A3,                  IP2_11_8)
  89 #define GPSR1_2         F_(A2,                  IP2_7_4)
  90 #define GPSR1_1         F_(A1,                  IP2_3_0)
  91 #define GPSR1_0         F_(A0,                  IP1_31_28)
  92
  93 /* GPSR2 */
  94 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  95 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  96 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  97 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  98 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  99 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
 100 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
 101 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 102 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 103 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 104 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 105 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 106 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 107 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 108 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 109
 110 /* GPSR3 */
 111 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 112 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 113 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 114 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 115 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 116 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 117 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 118 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 119 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 120 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 121 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 122 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 123 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 124 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 125 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 126 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 127
 128 /* GPSR4 */
 129 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 130 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 131 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 132 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 133 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 134 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 135 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 136 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 137 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 138 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 139 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 140 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 141 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 142 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 143 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 144 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 145 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 146 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 147
 148 /* GPSR5 */
 149 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 150 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 151 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 152 #define GPSR5_22        FM(MSIOF0_RXD)
 153 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 154 #define GPSR5_20        FM(MSIOF0_TXD)
 155 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 156 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 157 #define GPSR5_17        FM(MSIOF0_SCK)
 158 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 159 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 160 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 161 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 162 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 163 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 164 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 165 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 166 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 167 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 168 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 169 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 170 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 171 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 172 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 173 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 174 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 175
 176 /* GPSR6 */
 177 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 178 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 179 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 180 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 181 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 182 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 183 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 184 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 185 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 186 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 187 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 188 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 189 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 190 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 191 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 192 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 193 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 194 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 195 #define GPSR6_13        FM(SSI_SDATA5)
 196 #define GPSR6_12        FM(SSI_WS5)
 197 #define GPSR6_11        FM(SSI_SCK5)
 198 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 199 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 200 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 201 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 202 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 203 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 204 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 205 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 206 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 207 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 208 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 209
 210 /* GPSR7 */
 211 #define GPSR7_3         FM(GP7_03)
 212 #define GPSR7_2         FM(HDMI0_CEC)
 213 #define GPSR7_1         FM(AVS2)
 214 #define GPSR7_0         FM(AVS1)
 215
 216
 217 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 218 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245
 246 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 247 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276
 277 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 278 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312
 313 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 314 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 335 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342
 343 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 344 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 364 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 365 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 366 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 367 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 368 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 369 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 370 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 371
 372 #define PINMUX_GPSR     \
 373 \
 374                                                                                                 GPSR6_31 \
 375                                                                                                 GPSR6_30 \
 376                                                                                                 GPSR6_29 \
 377                 GPSR1_28                                                                        GPSR6_28 \
 378                 GPSR1_27                                                                        GPSR6_27 \
 379                 GPSR1_26                                                                        GPSR6_26 \
 380                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 381                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 382                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 383                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 384                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 385                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 386                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 387                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 388                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 389                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 390 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 391 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 392 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 393 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 394 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 395 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 396 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 397 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 398 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 399 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 400 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 401 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 402 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 403 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 404 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 405 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 406
 407 #define PINMUX_IPSR                             \
 408 \
 409 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 410 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 411 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 412 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 413 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 414 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 415 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 416 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 417 \
 418 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 419 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 420 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 421 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 422 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 423 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 424 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 425 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 426 \
 427 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 428 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 429 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 430 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 431 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 432 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 433 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 434 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 435 \
 436 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 437 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 438 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 439 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 440 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 441 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 442 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 443 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 444 \
 445 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 446 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 447 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 448 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 449 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 450 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 451 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 452 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 453
 454 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 455 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 456 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 457 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 458 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 459 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 460 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 461 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 462 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 463 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 464 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 465 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 466 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 467 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 468 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 469 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 470 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 471 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 472 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 473
 474 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 475 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 476 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 477 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 478 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 479 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 480 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 481 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 482 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 483 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 484 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 485 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 486 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 487 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 488 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 489 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 490 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 491 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 492 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 493 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 494 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 495 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 496 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 497
 498 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 499 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 500 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 501 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 502 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 503 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 504 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 505 #define MOD_SEL2_22             FM(SEL_NDFC_0)          FM(SEL_NDFC_1)
 506 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 507 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 508 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 509 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 510 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 511 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 512
 513 #define PINMUX_MOD_SELS \
 514 \
 515 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 516                                                 MOD_SEL2_30 \
 517                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 518 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 519 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 520                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 521 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 522 MOD_SEL0_22                                     MOD_SEL2_22 \
 523 MOD_SEL0_21                                     MOD_SEL2_21 \
 524 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 525 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 526 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 527                                                 MOD_SEL2_17 \
 528 MOD_SEL0_16             MOD_SEL1_16 \
 529                         MOD_SEL1_15_14 \
 530 MOD_SEL0_14_13 \
 531                         MOD_SEL1_13 \
 532 MOD_SEL0_12             MOD_SEL1_12 \
 533 MOD_SEL0_11             MOD_SEL1_11 \
 534 MOD_SEL0_10             MOD_SEL1_10 \
 535 MOD_SEL0_9_8            MOD_SEL1_9 \
 536 MOD_SEL0_7_6 \
 537                         MOD_SEL1_6 \
 538 MOD_SEL0_5              MOD_SEL1_5 \
 539 MOD_SEL0_4_3            MOD_SEL1_4 \
 540                         MOD_SEL1_3 \
 541                         MOD_SEL1_2 \
 542                         MOD_SEL1_1 \
 543                         MOD_SEL1_0              MOD_SEL2_0
 544
 545 /*
 546  * These pins are not able to be muxed but have other properties
 547  * that can be set, such as drive-strength or pull-up/pull-down enable.
 548  */
 549 #define PINMUX_STATIC \
 550         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 551         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 552         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 553         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 554         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 555         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 556         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 557         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 558         FM(PRESETOUT) \
 559         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 560         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 561
 562 enum {
 563         PINMUX_RESERVED = 0,
 564
 565         PINMUX_DATA_BEGIN,
 566         GP_ALL(DATA),
 567         PINMUX_DATA_END,
 568
 569 #define F_(x, y)
 570 #define FM(x)   FN_##x,
 571         PINMUX_FUNCTION_BEGIN,
 572         GP_ALL(FN),
 573         PINMUX_GPSR
 574         PINMUX_IPSR
 575         PINMUX_MOD_SELS
 576         PINMUX_FUNCTION_END,
 577 #undef F_
 578 #undef FM
 579
 580 #define F_(x, y)
 581 #define FM(x)   x##_MARK,
 582         PINMUX_MARK_BEGIN,
 583         PINMUX_GPSR
 584         PINMUX_IPSR
 585         PINMUX_MOD_SELS
 586         PINMUX_STATIC
 587         PINMUX_MARK_END,
 588 #undef F_
 589 #undef FM
 590 };
 591
 592 static const u16 pinmux_data[] = {
 593         PINMUX_DATA_GP_ALL(),
 594
 595         PINMUX_SINGLE(AVS1),
 596         PINMUX_SINGLE(AVS2),
 597         PINMUX_SINGLE(CLKOUT),
 598         PINMUX_SINGLE(GP7_03),
 599         PINMUX_SINGLE(HDMI0_CEC),
 600         PINMUX_SINGLE(MSIOF0_RXD),
 601         PINMUX_SINGLE(MSIOF0_SCK),
 602         PINMUX_SINGLE(MSIOF0_TXD),
 603         PINMUX_SINGLE(SSI_SCK5),
 604         PINMUX_SINGLE(SSI_SDATA5),
 605         PINMUX_SINGLE(SSI_WS5),
 606
 607         /* IPSR0 */
 608         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 609         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 610
 611         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 612         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 613         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 614
 615         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 616         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 617         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 618
 619         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 620         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 621         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 622
 623         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 624         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 625         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 626
 627         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 628         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 629         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_A,               SEL_SCIF4_0),
 630
 631         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 632         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 633         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 634         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 635         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 636         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 637         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 638
 639         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 640         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 641         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 642         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 643         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 644         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 645         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 646
 647         /* IPSR1 */
 648         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 649         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 650         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 651         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 652         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 653         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 654
 655         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 656         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 657         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 658         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 659         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 660         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 661
 662         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 663         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 664         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 665         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 666         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 667         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 668
 669         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 670         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 671         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 672         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 673         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 674         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 675
 676         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 677         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 678         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 679         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 680
 681         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 682         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 683         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 684         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 685
 686         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 687         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 688         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 689
 690         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 691         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 692         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 693         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 694         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 695         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 696
 697         /* IPSR2 */
 698         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 699         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 700         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 701         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 702         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 703         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 704
 705         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 706         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 707         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 708         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 709         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 710         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 711
 712         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 713         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 714         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 715         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 716         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 717         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 718
 719         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 720         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 721         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 722         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 723         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 724         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 725
 726         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 727         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 728         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 729         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 730         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 731         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 732         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 733
 734         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 735         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 736         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 737         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 738         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 739         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 740         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 741
 742         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 743         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 744         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 745         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 746         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 747         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 748         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 749
 750         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 751         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 752         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 753         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 754         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 755         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 756         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 757
 758         /* IPSR3 */
 759         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 760         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 761         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 762         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 763
 764         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 765         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 766         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 767         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 768
 769         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 770         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 771         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 772         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 773         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 774         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 775         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 776         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 777         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 778
 779         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 780         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 781         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 782         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 783         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 784         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 785
 786         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 787         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 788         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 789         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 790         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 791         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 792
 793         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 794         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 795         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 796         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 797         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 798         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 799
 800         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 801         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 802         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 803         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 804         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 805         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 806
 807         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 808         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 809         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 810         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 811
 812         /* IPSR4 */
 813         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 814         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 815         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 816         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 817
 818         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 819         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 820         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 821         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 822
 823         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 824         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 825         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 826         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 827
 828         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 829         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 830
 831         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 832         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 833         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 834
 835         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 836         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 837         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 838         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 839         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 840         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 841         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 842         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 843
 844         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 845         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 846         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 847         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 848         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 849         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 850
 851         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 852         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 853         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 854         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 855         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 856         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 857
 858         /* IPSR5 */
 859         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 860         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 861         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 862         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 863         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 864         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 865         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 866
 867         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 868         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 869         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 870         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 871         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 872         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 873         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 874         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 875
 876         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 877         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 878         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 879         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 880
 881         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 882         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 883         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 884         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 885         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 886
 887         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 888         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 889         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 890         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 891         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 892
 893         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 894         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 895         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 896         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 897
 898         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 899         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 900         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 901         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 902
 903         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 904         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 905         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 906         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 907
 908         /* IPSR6 */
 909         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 910         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 911         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 912         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 913
 914         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 915         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 916         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 917         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 918
 919         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 920         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 921         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 922         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 923
 924         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 925         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 926         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 927         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 928         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 929         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 930
 931         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 932         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 933         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 934         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 935         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 936
 937         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 938         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 939         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 940         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 941         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 942         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 943         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 944
 945         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 946         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 947         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 948         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 949         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 950         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 951         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 952
 953         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 954         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 955         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 956         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 957         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 958         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 959
 960         /* IPSR7 */
 961         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 962         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 963         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 964         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 965         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 966         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 967
 968         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 969         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 970         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 971         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 972         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 973         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 974         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 975
 976         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 977         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 978         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 979         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 980         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 981         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 982         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 983
 984         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 985         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 986         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 987
 988         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 989         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 990         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 991
 992         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 993         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 994         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 995         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 996
 997         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
 998         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
 999         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1000         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1001
1002         /* IPSR8 */
1003         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1004         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1005         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1006         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1007
1008         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1009         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1010         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1011         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1012
1013         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1014         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1015         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1016
1017         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1018         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1019         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDFC_1),
1020         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1021         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1022
1023         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1024         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1025         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1026         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDFC_1),
1027         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1028         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1029
1030         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1031         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1032         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1033         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDFC_1),
1034         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1035         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1036
1037         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1038         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1039         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1040         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDFC_1),
1041         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1042         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1043
1044         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1045         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1046         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1047         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDFC_1),
1048         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1049         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1050
1051         /* IPSR9 */
1052         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1053         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1054
1055         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1056         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1057
1058         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1059         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1060
1061         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1062         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1063
1064         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1065         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1066
1067         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1068         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1069
1070         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1071         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1072
1073         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1074         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1075
1076         /* IPSR10 */
1077         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1078         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1079
1080         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1081         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1082
1083         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1084         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1085
1086         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1087         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1088
1089         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1090         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1091
1092         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1093         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1094         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1095
1096         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1097         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1098         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1099
1100         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1101         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1102         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1103
1104         /* IPSR11 */
1105         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1106         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1107         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1108
1109         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1110         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1111
1112         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1113         PINMUX_IPSR_MSEL(IP11_11_8,     NFDATA14_A,             SEL_NDFC_0),
1114         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1115         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1116
1117         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1118         PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,             SEL_NDFC_0),
1119         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1120
1121         PINMUX_IPSR_GPSR(IP11_19_16,    SD1_CD),
1122         PINMUX_IPSR_MSEL(IP11_19_16,    NFRB_N_A,               SEL_NDFC_0),
1123         PINMUX_IPSR_MSEL(IP11_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1124
1125         PINMUX_IPSR_GPSR(IP11_23_20,    SD1_WP),
1126         PINMUX_IPSR_MSEL(IP11_23_20,    NFCE_N_A,               SEL_NDFC_0),
1127         PINMUX_IPSR_MSEL(IP11_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1128
1129         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1130         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1131         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1132         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1133         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1134         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1135         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1136         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1137         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1138         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1139
1140         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1141         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1142         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1143         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1144         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1145
1146         /* IPSR12 */
1147         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1148         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1149         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1150         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1151         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1152
1153         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1154         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1155         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1156         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1157         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1158         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1159         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1160         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1161
1162         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1163         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1164         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1165         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1166         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1167         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1168         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1169         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1170
1171         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1172         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1173         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1174         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1175         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1176
1177         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1178         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1179         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1180         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1181         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1182
1183         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1184         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1185         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1186         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1187         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1188         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1189         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1190
1191         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1192         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1193         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1194         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1195         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1196         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1197         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1198
1199         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1200         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1201         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1202         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1203         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1204         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1205         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1206
1207         /* IPSR13 */
1208         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1209         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1210         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1211         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1212         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1213         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1214
1215         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1216         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1217         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1218         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1219         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1220         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1221
1222         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1223         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1224         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1225         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1226         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1227         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1228         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1229         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1230
1231         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1232         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1233         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1234         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1235         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1237
1238         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1239         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1240         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1241         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1242         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1243         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1244
1245         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1246         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1247         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1248         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1249         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1250         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1251         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1252         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1253
1254         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1255         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1256         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1257         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1258         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1259         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1260         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1261
1262         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1263         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1264         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1265         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1266
1267         /* IPSR14 */
1268         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1269         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1270         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDFC_0),
1271         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1272         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1273         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1274         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1275         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1276
1277         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1278         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1279         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1280         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1281         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1282         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1283         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1284         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1285
1286         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1287         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1288         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1289
1290         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1291         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1292         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1293         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1294
1295         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1296         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1297         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1298
1299         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1300         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1301
1302         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1303         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1304
1305         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1306         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1307
1308         /* IPSR15 */
1309         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1310
1311         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1312         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1313
1314         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1315         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1316         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1317
1318         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1319         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1320         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1321         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1322
1323         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1324         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1325         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1328         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1329         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1330
1331         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1332         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1333         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1337         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1338
1339         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1340         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1341         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1342         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1345         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1346
1347         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1348         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1349         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1350         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1351         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1353         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1354
1355         /* IPSR16 */
1356         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1357         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1358
1359         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1360         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1361
1362         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1363         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1364
1365         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1366         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1367         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1368         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1369         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1370         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1371         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1372
1373         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1374         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1375         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1376         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1377         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1378         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1380
1381         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1382         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1383         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1384         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1385         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1386         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1387         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1389
1390         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1391         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1392         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1393         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1394         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1395         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1396         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1397
1398         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1399         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1400         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1401         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1402         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1403         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1404         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1405         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1406
1407         /* IPSR17 */
1408         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1409         PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
1410
1411         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1412         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1413         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1414         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1415         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1416
1417         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1418         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1419         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1420         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1421         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1422         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1423         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1424
1425         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1426         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1427         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1428         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1429         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1430         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1431
1432         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1433         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1434         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1435         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1436         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1437         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1438         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1439         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1440         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1441
1442         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1443         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1444         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1445         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1446         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1447         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1448         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1449         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1450         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1451
1452         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1453         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1454         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1455         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1456         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1457         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1458         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1459         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1460         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1461         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1462         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1463
1464         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1465         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1466         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1467         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1468         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1469         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1470         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1471         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1472         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1473
1474         /* IPSR18 */
1475         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1476         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1477         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1478         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1479         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1480         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1481         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1482         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1483         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1484
1485         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1486         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1487         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1488         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1489         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1490         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1491         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1492         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1493         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1494
1495         /* I2C */
1496         PINMUX_IPSR_NOGP(0,             I2C_SEL_0_1),
1497         PINMUX_IPSR_NOGP(0,             I2C_SEL_3_1),
1498         PINMUX_IPSR_NOGP(0,             I2C_SEL_5_1),
1499
1500 /*
1501  * Static pins can not be muxed between different functions but
1502  * still needs a mark entry in the pinmux list. Add each static
1503  * pin to the list without an associated function. The sh-pfc
1504  * core will do the right thing and skip trying to mux then pin
1505  * while still applying configuration to it
1506  */
1507 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1508         PINMUX_STATIC
1509 #undef FM
1510 };
1511
1512 /*
1513  * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1514  * Physical layout rows: A - AW, cols: 1 - 39.
1515  */
1516 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1517 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1518 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1519 #define PIN_NONE U16_MAX
1520
1521 static const struct sh_pfc_pin pinmux_pins[] = {
1522         PINMUX_GPIO_GP_ALL(),
1523
1524         /*
1525          * Pins not associated with a GPIO port.
1526          *
1527          * The pin positions are different between different r8a7796
1528          * packages, all that is needed for the pfc driver is a unique
1529          * number for each pin. To this end use the pin layout from
1530          * R-Car M3SiP to calculate a unique number for each pin.
1531          */
1532         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1533         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1534         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1535         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1536         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1574 };
1575
1576 /* - AUDIO CLOCK ------------------------------------------------------------ */
1577 static const unsigned int audio_clk_a_a_pins[] = {
1578         /* CLK A */
1579         RCAR_GP_PIN(6, 22),
1580 };
1581 static const unsigned int audio_clk_a_a_mux[] = {
1582         AUDIO_CLKA_A_MARK,
1583 };
1584 static const unsigned int audio_clk_a_b_pins[] = {
1585         /* CLK A */
1586         RCAR_GP_PIN(5, 4),
1587 };
1588 static const unsigned int audio_clk_a_b_mux[] = {
1589         AUDIO_CLKA_B_MARK,
1590 };
1591 static const unsigned int audio_clk_a_c_pins[] = {
1592         /* CLK A */
1593         RCAR_GP_PIN(5, 19),
1594 };
1595 static const unsigned int audio_clk_a_c_mux[] = {
1596         AUDIO_CLKA_C_MARK,
1597 };
1598 static const unsigned int audio_clk_b_a_pins[] = {
1599         /* CLK B */
1600         RCAR_GP_PIN(5, 12),
1601 };
1602 static const unsigned int audio_clk_b_a_mux[] = {
1603         AUDIO_CLKB_A_MARK,
1604 };
1605 static const unsigned int audio_clk_b_b_pins[] = {
1606         /* CLK B */
1607         RCAR_GP_PIN(6, 23),
1608 };
1609 static const unsigned int audio_clk_b_b_mux[] = {
1610         AUDIO_CLKB_B_MARK,
1611 };
1612 static const unsigned int audio_clk_c_a_pins[] = {
1613         /* CLK C */
1614         RCAR_GP_PIN(5, 21),
1615 };
1616 static const unsigned int audio_clk_c_a_mux[] = {
1617         AUDIO_CLKC_A_MARK,
1618 };
1619 static const unsigned int audio_clk_c_b_pins[] = {
1620         /* CLK C */
1621         RCAR_GP_PIN(5, 0),
1622 };
1623 static const unsigned int audio_clk_c_b_mux[] = {
1624         AUDIO_CLKC_B_MARK,
1625 };
1626 static const unsigned int audio_clkout_a_pins[] = {
1627         /* CLKOUT */
1628         RCAR_GP_PIN(5, 18),
1629 };
1630 static const unsigned int audio_clkout_a_mux[] = {
1631         AUDIO_CLKOUT_A_MARK,
1632 };
1633 static const unsigned int audio_clkout_b_pins[] = {
1634         /* CLKOUT */
1635         RCAR_GP_PIN(6, 28),
1636 };
1637 static const unsigned int audio_clkout_b_mux[] = {
1638         AUDIO_CLKOUT_B_MARK,
1639 };
1640 static const unsigned int audio_clkout_c_pins[] = {
1641         /* CLKOUT */
1642         RCAR_GP_PIN(5, 3),
1643 };
1644 static const unsigned int audio_clkout_c_mux[] = {
1645         AUDIO_CLKOUT_C_MARK,
1646 };
1647 static const unsigned int audio_clkout_d_pins[] = {
1648         /* CLKOUT */
1649         RCAR_GP_PIN(5, 21),
1650 };
1651 static const unsigned int audio_clkout_d_mux[] = {
1652         AUDIO_CLKOUT_D_MARK,
1653 };
1654 static const unsigned int audio_clkout1_a_pins[] = {
1655         /* CLKOUT1 */
1656         RCAR_GP_PIN(5, 15),
1657 };
1658 static const unsigned int audio_clkout1_a_mux[] = {
1659         AUDIO_CLKOUT1_A_MARK,
1660 };
1661 static const unsigned int audio_clkout1_b_pins[] = {
1662         /* CLKOUT1 */
1663         RCAR_GP_PIN(6, 29),
1664 };
1665 static const unsigned int audio_clkout1_b_mux[] = {
1666         AUDIO_CLKOUT1_B_MARK,
1667 };
1668 static const unsigned int audio_clkout2_a_pins[] = {
1669         /* CLKOUT2 */
1670         RCAR_GP_PIN(5, 16),
1671 };
1672 static const unsigned int audio_clkout2_a_mux[] = {
1673         AUDIO_CLKOUT2_A_MARK,
1674 };
1675 static const unsigned int audio_clkout2_b_pins[] = {
1676         /* CLKOUT2 */
1677         RCAR_GP_PIN(6, 30),
1678 };
1679 static const unsigned int audio_clkout2_b_mux[] = {
1680         AUDIO_CLKOUT2_B_MARK,
1681 };
1682
1683 static const unsigned int audio_clkout3_a_pins[] = {
1684         /* CLKOUT3 */
1685         RCAR_GP_PIN(5, 19),
1686 };
1687 static const unsigned int audio_clkout3_a_mux[] = {
1688         AUDIO_CLKOUT3_A_MARK,
1689 };
1690 static const unsigned int audio_clkout3_b_pins[] = {
1691         /* CLKOUT3 */
1692         RCAR_GP_PIN(6, 31),
1693 };
1694 static const unsigned int audio_clkout3_b_mux[] = {
1695         AUDIO_CLKOUT3_B_MARK,
1696 };
1697
1698 /* - EtherAVB --------------------------------------------------------------- */
1699 static const unsigned int avb_link_pins[] = {
1700         /* AVB_LINK */
1701         RCAR_GP_PIN(2, 12),
1702 };
1703 static const unsigned int avb_link_mux[] = {
1704         AVB_LINK_MARK,
1705 };
1706 static const unsigned int avb_magic_pins[] = {
1707         /* AVB_MAGIC_ */
1708         RCAR_GP_PIN(2, 10),
1709 };
1710 static const unsigned int avb_magic_mux[] = {
1711         AVB_MAGIC_MARK,
1712 };
1713 static const unsigned int avb_phy_int_pins[] = {
1714         /* AVB_PHY_INT */
1715         RCAR_GP_PIN(2, 11),
1716 };
1717 static const unsigned int avb_phy_int_mux[] = {
1718         AVB_PHY_INT_MARK,
1719 };
1720 static const unsigned int avb_mdio_pins[] = {
1721         /* AVB_MDC, AVB_MDIO */
1722         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1723 };
1724 static const unsigned int avb_mdio_mux[] = {
1725         AVB_MDC_MARK, AVB_MDIO_MARK,
1726 };
1727 static const unsigned int avb_mii_pins[] = {
1728         /*
1729          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1730          * AVB_TD1, AVB_TD2, AVB_TD3,
1731          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1732          * AVB_RD1, AVB_RD2, AVB_RD3,
1733          * AVB_TXCREFCLK
1734          */
1735         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1736         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1737         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1738         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1739         PIN_NUMBER('A', 12),
1740
1741 };
1742 static const unsigned int avb_mii_mux[] = {
1743         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1744         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1745         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1746         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1747         AVB_TXCREFCLK_MARK,
1748 };
1749 static const unsigned int avb_avtp_pps_pins[] = {
1750         /* AVB_AVTP_PPS */
1751         RCAR_GP_PIN(2, 6),
1752 };
1753 static const unsigned int avb_avtp_pps_mux[] = {
1754         AVB_AVTP_PPS_MARK,
1755 };
1756 static const unsigned int avb_avtp_match_a_pins[] = {
1757         /* AVB_AVTP_MATCH_A */
1758         RCAR_GP_PIN(2, 13),
1759 };
1760 static const unsigned int avb_avtp_match_a_mux[] = {
1761         AVB_AVTP_MATCH_A_MARK,
1762 };
1763 static const unsigned int avb_avtp_capture_a_pins[] = {
1764         /* AVB_AVTP_CAPTURE_A */
1765         RCAR_GP_PIN(2, 14),
1766 };
1767 static const unsigned int avb_avtp_capture_a_mux[] = {
1768         AVB_AVTP_CAPTURE_A_MARK,
1769 };
1770 static const unsigned int avb_avtp_match_b_pins[] = {
1771         /*  AVB_AVTP_MATCH_B */
1772         RCAR_GP_PIN(1, 8),
1773 };
1774 static const unsigned int avb_avtp_match_b_mux[] = {
1775         AVB_AVTP_MATCH_B_MARK,
1776 };
1777 static const unsigned int avb_avtp_capture_b_pins[] = {
1778         /* AVB_AVTP_CAPTURE_B */
1779         RCAR_GP_PIN(1, 11),
1780 };
1781 static const unsigned int avb_avtp_capture_b_mux[] = {
1782         AVB_AVTP_CAPTURE_B_MARK,
1783 };
1784
1785 /* - CAN ------------------------------------------------------------------ */
1786 static const unsigned int can0_data_a_pins[] = {
1787         /* TX, RX */
1788         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1789 };
1790 static const unsigned int can0_data_a_mux[] = {
1791         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1792 };
1793 static const unsigned int can0_data_b_pins[] = {
1794         /* TX, RX */
1795         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1796 };
1797 static const unsigned int can0_data_b_mux[] = {
1798         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1799 };
1800 static const unsigned int can1_data_pins[] = {
1801         /* TX, RX */
1802         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1803 };
1804 static const unsigned int can1_data_mux[] = {
1805         CAN1_TX_MARK,           CAN1_RX_MARK,
1806 };
1807
1808 /* - CAN Clock -------------------------------------------------------------- */
1809 static const unsigned int can_clk_pins[] = {
1810         /* CLK */
1811         RCAR_GP_PIN(1, 25),
1812 };
1813 static const unsigned int can_clk_mux[] = {
1814         CAN_CLK_MARK,
1815 };
1816
1817 /* - CAN FD --------------------------------------------------------------- */
1818 static const unsigned int canfd0_data_a_pins[] = {
1819         /* TX, RX */
1820         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1821 };
1822 static const unsigned int canfd0_data_a_mux[] = {
1823         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1824 };
1825 static const unsigned int canfd0_data_b_pins[] = {
1826         /* TX, RX */
1827         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1828 };
1829 static const unsigned int canfd0_data_b_mux[] = {
1830         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1831 };
1832 static const unsigned int canfd1_data_pins[] = {
1833         /* TX, RX */
1834         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1835 };
1836 static const unsigned int canfd1_data_mux[] = {
1837         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1838 };
1839
1840 /* - DRIF0 --------------------------------------------------------------- */
1841 static const unsigned int drif0_ctrl_a_pins[] = {
1842         /* CLK, SYNC */
1843         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1844 };
1845 static const unsigned int drif0_ctrl_a_mux[] = {
1846         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1847 };
1848 static const unsigned int drif0_data0_a_pins[] = {
1849         /* D0 */
1850         RCAR_GP_PIN(6, 10),
1851 };
1852 static const unsigned int drif0_data0_a_mux[] = {
1853         RIF0_D0_A_MARK,
1854 };
1855 static const unsigned int drif0_data1_a_pins[] = {
1856         /* D1 */
1857         RCAR_GP_PIN(6, 7),
1858 };
1859 static const unsigned int drif0_data1_a_mux[] = {
1860         RIF0_D1_A_MARK,
1861 };
1862 static const unsigned int drif0_ctrl_b_pins[] = {
1863         /* CLK, SYNC */
1864         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1865 };
1866 static const unsigned int drif0_ctrl_b_mux[] = {
1867         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1868 };
1869 static const unsigned int drif0_data0_b_pins[] = {
1870         /* D0 */
1871         RCAR_GP_PIN(5, 1),
1872 };
1873 static const unsigned int drif0_data0_b_mux[] = {
1874         RIF0_D0_B_MARK,
1875 };
1876 static const unsigned int drif0_data1_b_pins[] = {
1877         /* D1 */
1878         RCAR_GP_PIN(5, 2),
1879 };
1880 static const unsigned int drif0_data1_b_mux[] = {
1881         RIF0_D1_B_MARK,
1882 };
1883 static const unsigned int drif0_ctrl_c_pins[] = {
1884         /* CLK, SYNC */
1885         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1886 };
1887 static const unsigned int drif0_ctrl_c_mux[] = {
1888         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1889 };
1890 static const unsigned int drif0_data0_c_pins[] = {
1891         /* D0 */
1892         RCAR_GP_PIN(5, 13),
1893 };
1894 static const unsigned int drif0_data0_c_mux[] = {
1895         RIF0_D0_C_MARK,
1896 };
1897 static const unsigned int drif0_data1_c_pins[] = {
1898         /* D1 */
1899         RCAR_GP_PIN(5, 14),
1900 };
1901 static const unsigned int drif0_data1_c_mux[] = {
1902         RIF0_D1_C_MARK,
1903 };
1904 /* - DRIF1 --------------------------------------------------------------- */
1905 static const unsigned int drif1_ctrl_a_pins[] = {
1906         /* CLK, SYNC */
1907         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1908 };
1909 static const unsigned int drif1_ctrl_a_mux[] = {
1910         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1911 };
1912 static const unsigned int drif1_data0_a_pins[] = {
1913         /* D0 */
1914         RCAR_GP_PIN(6, 19),
1915 };
1916 static const unsigned int drif1_data0_a_mux[] = {
1917         RIF1_D0_A_MARK,
1918 };
1919 static const unsigned int drif1_data1_a_pins[] = {
1920         /* D1 */
1921         RCAR_GP_PIN(6, 20),
1922 };
1923 static const unsigned int drif1_data1_a_mux[] = {
1924         RIF1_D1_A_MARK,
1925 };
1926 static const unsigned int drif1_ctrl_b_pins[] = {
1927         /* CLK, SYNC */
1928         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1929 };
1930 static const unsigned int drif1_ctrl_b_mux[] = {
1931         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1932 };
1933 static const unsigned int drif1_data0_b_pins[] = {
1934         /* D0 */
1935         RCAR_GP_PIN(5, 7),
1936 };
1937 static const unsigned int drif1_data0_b_mux[] = {
1938         RIF1_D0_B_MARK,
1939 };
1940 static const unsigned int drif1_data1_b_pins[] = {
1941         /* D1 */
1942         RCAR_GP_PIN(5, 8),
1943 };
1944 static const unsigned int drif1_data1_b_mux[] = {
1945         RIF1_D1_B_MARK,
1946 };
1947 static const unsigned int drif1_ctrl_c_pins[] = {
1948         /* CLK, SYNC */
1949         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1950 };
1951 static const unsigned int drif1_ctrl_c_mux[] = {
1952         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1953 };
1954 static const unsigned int drif1_data0_c_pins[] = {
1955         /* D0 */
1956         RCAR_GP_PIN(5, 6),
1957 };
1958 static const unsigned int drif1_data0_c_mux[] = {
1959         RIF1_D0_C_MARK,
1960 };
1961 static const unsigned int drif1_data1_c_pins[] = {
1962         /* D1 */
1963         RCAR_GP_PIN(5, 10),
1964 };
1965 static const unsigned int drif1_data1_c_mux[] = {
1966         RIF1_D1_C_MARK,
1967 };
1968 /* - DRIF2 --------------------------------------------------------------- */
1969 static const unsigned int drif2_ctrl_a_pins[] = {
1970         /* CLK, SYNC */
1971         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1972 };
1973 static const unsigned int drif2_ctrl_a_mux[] = {
1974         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1975 };
1976 static const unsigned int drif2_data0_a_pins[] = {
1977         /* D0 */
1978         RCAR_GP_PIN(6, 7),
1979 };
1980 static const unsigned int drif2_data0_a_mux[] = {
1981         RIF2_D0_A_MARK,
1982 };
1983 static const unsigned int drif2_data1_a_pins[] = {
1984         /* D1 */
1985         RCAR_GP_PIN(6, 10),
1986 };
1987 static const unsigned int drif2_data1_a_mux[] = {
1988         RIF2_D1_A_MARK,
1989 };
1990 static const unsigned int drif2_ctrl_b_pins[] = {
1991         /* CLK, SYNC */
1992         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1993 };
1994 static const unsigned int drif2_ctrl_b_mux[] = {
1995         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1996 };
1997 static const unsigned int drif2_data0_b_pins[] = {
1998         /* D0 */
1999         RCAR_GP_PIN(6, 30),
2000 };
2001 static const unsigned int drif2_data0_b_mux[] = {
2002         RIF2_D0_B_MARK,
2003 };
2004 static const unsigned int drif2_data1_b_pins[] = {
2005         /* D1 */
2006         RCAR_GP_PIN(6, 31),
2007 };
2008 static const unsigned int drif2_data1_b_mux[] = {
2009         RIF2_D1_B_MARK,
2010 };
2011 /* - DRIF3 --------------------------------------------------------------- */
2012 static const unsigned int drif3_ctrl_a_pins[] = {
2013         /* CLK, SYNC */
2014         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2015 };
2016 static const unsigned int drif3_ctrl_a_mux[] = {
2017         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2018 };
2019 static const unsigned int drif3_data0_a_pins[] = {
2020         /* D0 */
2021         RCAR_GP_PIN(6, 19),
2022 };
2023 static const unsigned int drif3_data0_a_mux[] = {
2024         RIF3_D0_A_MARK,
2025 };
2026 static const unsigned int drif3_data1_a_pins[] = {
2027         /* D1 */
2028         RCAR_GP_PIN(6, 20),
2029 };
2030 static const unsigned int drif3_data1_a_mux[] = {
2031         RIF3_D1_A_MARK,
2032 };
2033 static const unsigned int drif3_ctrl_b_pins[] = {
2034         /* CLK, SYNC */
2035         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2036 };
2037 static const unsigned int drif3_ctrl_b_mux[] = {
2038         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2039 };
2040 static const unsigned int drif3_data0_b_pins[] = {
2041         /* D0 */
2042         RCAR_GP_PIN(6, 28),
2043 };
2044 static const unsigned int drif3_data0_b_mux[] = {
2045         RIF3_D0_B_MARK,
2046 };
2047 static const unsigned int drif3_data1_b_pins[] = {
2048         /* D1 */
2049         RCAR_GP_PIN(6, 29),
2050 };
2051 static const unsigned int drif3_data1_b_mux[] = {
2052         RIF3_D1_B_MARK,
2053 };
2054
2055 /* - DU --------------------------------------------------------------------- */
2056 static const unsigned int du_rgb666_pins[] = {
2057         /* R[7:2], G[7:2], B[7:2] */
2058         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2059         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2060         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2061         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2062         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2063         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2064 };
2065 static const unsigned int du_rgb666_mux[] = {
2066         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2067         DU_DR3_MARK, DU_DR2_MARK,
2068         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2069         DU_DG3_MARK, DU_DG2_MARK,
2070         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2071         DU_DB3_MARK, DU_DB2_MARK,
2072 };
2073 static const unsigned int du_rgb888_pins[] = {
2074         /* R[7:0], G[7:0], B[7:0] */
2075         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2076         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2077         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2078         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2079         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2080         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2081         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2082         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2083         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2084 };
2085 static const unsigned int du_rgb888_mux[] = {
2086         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2087         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2088         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2089         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2090         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2091         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2092 };
2093 static const unsigned int du_clk_out_0_pins[] = {
2094         /* CLKOUT */
2095         RCAR_GP_PIN(1, 27),
2096 };
2097 static const unsigned int du_clk_out_0_mux[] = {
2098         DU_DOTCLKOUT0_MARK
2099 };
2100 static const unsigned int du_clk_out_1_pins[] = {
2101         /* CLKOUT */
2102         RCAR_GP_PIN(2, 3),
2103 };
2104 static const unsigned int du_clk_out_1_mux[] = {
2105         DU_DOTCLKOUT1_MARK
2106 };
2107 static const unsigned int du_sync_pins[] = {
2108         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2109         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2110 };
2111 static const unsigned int du_sync_mux[] = {
2112         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2113 };
2114 static const unsigned int du_oddf_pins[] = {
2115         /* EXDISP/EXODDF/EXCDE */
2116         RCAR_GP_PIN(2, 2),
2117 };
2118 static const unsigned int du_oddf_mux[] = {
2119         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2120 };
2121 static const unsigned int du_cde_pins[] = {
2122         /* CDE */
2123         RCAR_GP_PIN(2, 0),
2124 };
2125 static const unsigned int du_cde_mux[] = {
2126         DU_CDE_MARK,
2127 };
2128 static const unsigned int du_disp_pins[] = {
2129         /* DISP */
2130         RCAR_GP_PIN(2, 1),
2131 };
2132 static const unsigned int du_disp_mux[] = {
2133         DU_DISP_MARK,
2134 };
2135
2136 /* - HDMI ------------------------------------------------------------------- */
2137 static const unsigned int hdmi0_cec_pins[] = {
2138         /* HDMI0_CEC */
2139         RCAR_GP_PIN(7, 2),
2140 };
2141 static const unsigned int hdmi0_cec_mux[] = {
2142         HDMI0_CEC_MARK,
2143 };
2144
2145 /* - HSCIF0 ----------------------------------------------------------------- */
2146 static const unsigned int hscif0_data_pins[] = {
2147         /* RX, TX */
2148         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2149 };
2150 static const unsigned int hscif0_data_mux[] = {
2151         HRX0_MARK, HTX0_MARK,
2152 };
2153 static const unsigned int hscif0_clk_pins[] = {
2154         /* SCK */
2155         RCAR_GP_PIN(5, 12),
2156 };
2157 static const unsigned int hscif0_clk_mux[] = {
2158         HSCK0_MARK,
2159 };
2160 static const unsigned int hscif0_ctrl_pins[] = {
2161         /* RTS, CTS */
2162         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2163 };
2164 static const unsigned int hscif0_ctrl_mux[] = {
2165         HRTS0_N_MARK, HCTS0_N_MARK,
2166 };
2167 /* - HSCIF1 ----------------------------------------------------------------- */
2168 static const unsigned int hscif1_data_a_pins[] = {
2169         /* RX, TX */
2170         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2171 };
2172 static const unsigned int hscif1_data_a_mux[] = {
2173         HRX1_A_MARK, HTX1_A_MARK,
2174 };
2175 static const unsigned int hscif1_clk_a_pins[] = {
2176         /* SCK */
2177         RCAR_GP_PIN(6, 21),
2178 };
2179 static const unsigned int hscif1_clk_a_mux[] = {
2180         HSCK1_A_MARK,
2181 };
2182 static const unsigned int hscif1_ctrl_a_pins[] = {
2183         /* RTS, CTS */
2184         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2185 };
2186 static const unsigned int hscif1_ctrl_a_mux[] = {
2187         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2188 };
2189
2190 static const unsigned int hscif1_data_b_pins[] = {
2191         /* RX, TX */
2192         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2193 };
2194 static const unsigned int hscif1_data_b_mux[] = {
2195         HRX1_B_MARK, HTX1_B_MARK,
2196 };
2197 static const unsigned int hscif1_clk_b_pins[] = {
2198         /* SCK */
2199         RCAR_GP_PIN(5, 0),
2200 };
2201 static const unsigned int hscif1_clk_b_mux[] = {
2202         HSCK1_B_MARK,
2203 };
2204 static const unsigned int hscif1_ctrl_b_pins[] = {
2205         /* RTS, CTS */
2206         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2207 };
2208 static const unsigned int hscif1_ctrl_b_mux[] = {
2209         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2210 };
2211 /* - HSCIF2 ----------------------------------------------------------------- */
2212 static const unsigned int hscif2_data_a_pins[] = {
2213         /* RX, TX */
2214         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2215 };
2216 static const unsigned int hscif2_data_a_mux[] = {
2217         HRX2_A_MARK, HTX2_A_MARK,
2218 };
2219 static const unsigned int hscif2_clk_a_pins[] = {
2220         /* SCK */
2221         RCAR_GP_PIN(6, 10),
2222 };
2223 static const unsigned int hscif2_clk_a_mux[] = {
2224         HSCK2_A_MARK,
2225 };
2226 static const unsigned int hscif2_ctrl_a_pins[] = {
2227         /* RTS, CTS */
2228         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2229 };
2230 static const unsigned int hscif2_ctrl_a_mux[] = {
2231         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2232 };
2233
2234 static const unsigned int hscif2_data_b_pins[] = {
2235         /* RX, TX */
2236         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2237 };
2238 static const unsigned int hscif2_data_b_mux[] = {
2239         HRX2_B_MARK, HTX2_B_MARK,
2240 };
2241 static const unsigned int hscif2_clk_b_pins[] = {
2242         /* SCK */
2243         RCAR_GP_PIN(6, 21),
2244 };
2245 static const unsigned int hscif2_clk_b_mux[] = {
2246         HSCK2_B_MARK,
2247 };
2248 static const unsigned int hscif2_ctrl_b_pins[] = {
2249         /* RTS, CTS */
2250         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2251 };
2252 static const unsigned int hscif2_ctrl_b_mux[] = {
2253         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2254 };
2255
2256 static const unsigned int hscif2_data_c_pins[] = {
2257         /* RX, TX */
2258         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2259 };
2260 static const unsigned int hscif2_data_c_mux[] = {
2261         HRX2_C_MARK, HTX2_C_MARK,
2262 };
2263 static const unsigned int hscif2_clk_c_pins[] = {
2264         /* SCK */
2265         RCAR_GP_PIN(6, 24),
2266 };
2267 static const unsigned int hscif2_clk_c_mux[] = {
2268         HSCK2_C_MARK,
2269 };
2270 static const unsigned int hscif2_ctrl_c_pins[] = {
2271         /* RTS, CTS */
2272         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2273 };
2274 static const unsigned int hscif2_ctrl_c_mux[] = {
2275         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2276 };
2277 /* - HSCIF3 ----------------------------------------------------------------- */
2278 static const unsigned int hscif3_data_a_pins[] = {
2279         /* RX, TX */
2280         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2281 };
2282 static const unsigned int hscif3_data_a_mux[] = {
2283         HRX3_A_MARK, HTX3_A_MARK,
2284 };
2285 static const unsigned int hscif3_clk_pins[] = {
2286         /* SCK */
2287         RCAR_GP_PIN(1, 22),
2288 };
2289 static const unsigned int hscif3_clk_mux[] = {
2290         HSCK3_MARK,
2291 };
2292 static const unsigned int hscif3_ctrl_pins[] = {
2293         /* RTS, CTS */
2294         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2295 };
2296 static const unsigned int hscif3_ctrl_mux[] = {
2297         HRTS3_N_MARK, HCTS3_N_MARK,
2298 };
2299
2300 static const unsigned int hscif3_data_b_pins[] = {
2301         /* RX, TX */
2302         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2303 };
2304 static const unsigned int hscif3_data_b_mux[] = {
2305         HRX3_B_MARK, HTX3_B_MARK,
2306 };
2307 static const unsigned int hscif3_data_c_pins[] = {
2308         /* RX, TX */
2309         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2310 };
2311 static const unsigned int hscif3_data_c_mux[] = {
2312         HRX3_C_MARK, HTX3_C_MARK,
2313 };
2314 static const unsigned int hscif3_data_d_pins[] = {
2315         /* RX, TX */
2316         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2317 };
2318 static const unsigned int hscif3_data_d_mux[] = {
2319         HRX3_D_MARK, HTX3_D_MARK,
2320 };
2321 /* - HSCIF4 ----------------------------------------------------------------- */
2322 static const unsigned int hscif4_data_a_pins[] = {
2323         /* RX, TX */
2324         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2325 };
2326 static const unsigned int hscif4_data_a_mux[] = {
2327         HRX4_A_MARK, HTX4_A_MARK,
2328 };
2329 static const unsigned int hscif4_clk_pins[] = {
2330         /* SCK */
2331         RCAR_GP_PIN(1, 11),
2332 };
2333 static const unsigned int hscif4_clk_mux[] = {
2334         HSCK4_MARK,
2335 };
2336 static const unsigned int hscif4_ctrl_pins[] = {
2337         /* RTS, CTS */
2338         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2339 };
2340 static const unsigned int hscif4_ctrl_mux[] = {
2341         HRTS4_N_MARK, HCTS4_N_MARK,
2342 };
2343
2344 static const unsigned int hscif4_data_b_pins[] = {
2345         /* RX, TX */
2346         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2347 };
2348 static const unsigned int hscif4_data_b_mux[] = {
2349         HRX4_B_MARK, HTX4_B_MARK,
2350 };
2351
2352 /* - I2C -------------------------------------------------------------------- */
2353 static const unsigned int i2c1_a_pins[] = {
2354         /* SDA, SCL */
2355         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2356 };
2357 static const unsigned int i2c1_a_mux[] = {
2358         SDA1_A_MARK, SCL1_A_MARK,
2359 };
2360 static const unsigned int i2c1_b_pins[] = {
2361         /* SDA, SCL */
2362         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2363 };
2364 static const unsigned int i2c1_b_mux[] = {
2365         SDA1_B_MARK, SCL1_B_MARK,
2366 };
2367 static const unsigned int i2c2_a_pins[] = {
2368         /* SDA, SCL */
2369         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2370 };
2371 static const unsigned int i2c2_a_mux[] = {
2372         SDA2_A_MARK, SCL2_A_MARK,
2373 };
2374 static const unsigned int i2c2_b_pins[] = {
2375         /* SDA, SCL */
2376         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2377 };
2378 static const unsigned int i2c2_b_mux[] = {
2379         SDA2_B_MARK, SCL2_B_MARK,
2380 };
2381 static const unsigned int i2c6_a_pins[] = {
2382         /* SDA, SCL */
2383         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2384 };
2385 static const unsigned int i2c6_a_mux[] = {
2386         SDA6_A_MARK, SCL6_A_MARK,
2387 };
2388 static const unsigned int i2c6_b_pins[] = {
2389         /* SDA, SCL */
2390         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2391 };
2392 static const unsigned int i2c6_b_mux[] = {
2393         SDA6_B_MARK, SCL6_B_MARK,
2394 };
2395 static const unsigned int i2c6_c_pins[] = {
2396         /* SDA, SCL */
2397         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2398 };
2399 static const unsigned int i2c6_c_mux[] = {
2400         SDA6_C_MARK, SCL6_C_MARK,
2401 };
2402
2403 /* - INTC-EX ---------------------------------------------------------------- */
2404 static const unsigned int intc_ex_irq0_pins[] = {
2405         /* IRQ0 */
2406         RCAR_GP_PIN(2, 0),
2407 };
2408 static const unsigned int intc_ex_irq0_mux[] = {
2409         IRQ0_MARK,
2410 };
2411 static const unsigned int intc_ex_irq1_pins[] = {
2412         /* IRQ1 */
2413         RCAR_GP_PIN(2, 1),
2414 };
2415 static const unsigned int intc_ex_irq1_mux[] = {
2416         IRQ1_MARK,
2417 };
2418 static const unsigned int intc_ex_irq2_pins[] = {
2419         /* IRQ2 */
2420         RCAR_GP_PIN(2, 2),
2421 };
2422 static const unsigned int intc_ex_irq2_mux[] = {
2423         IRQ2_MARK,
2424 };
2425 static const unsigned int intc_ex_irq3_pins[] = {
2426         /* IRQ3 */
2427         RCAR_GP_PIN(2, 3),
2428 };
2429 static const unsigned int intc_ex_irq3_mux[] = {
2430         IRQ3_MARK,
2431 };
2432 static const unsigned int intc_ex_irq4_pins[] = {
2433         /* IRQ4 */
2434         RCAR_GP_PIN(2, 4),
2435 };
2436 static const unsigned int intc_ex_irq4_mux[] = {
2437         IRQ4_MARK,
2438 };
2439 static const unsigned int intc_ex_irq5_pins[] = {
2440         /* IRQ5 */
2441         RCAR_GP_PIN(2, 5),
2442 };
2443 static const unsigned int intc_ex_irq5_mux[] = {
2444         IRQ5_MARK,
2445 };
2446
2447 /* - MSIOF0 ----------------------------------------------------------------- */
2448 static const unsigned int msiof0_clk_pins[] = {
2449         /* SCK */
2450         RCAR_GP_PIN(5, 17),
2451 };
2452 static const unsigned int msiof0_clk_mux[] = {
2453         MSIOF0_SCK_MARK,
2454 };
2455 static const unsigned int msiof0_sync_pins[] = {
2456         /* SYNC */
2457         RCAR_GP_PIN(5, 18),
2458 };
2459 static const unsigned int msiof0_sync_mux[] = {
2460         MSIOF0_SYNC_MARK,
2461 };
2462 static const unsigned int msiof0_ss1_pins[] = {
2463         /* SS1 */
2464         RCAR_GP_PIN(5, 19),
2465 };
2466 static const unsigned int msiof0_ss1_mux[] = {
2467         MSIOF0_SS1_MARK,
2468 };
2469 static const unsigned int msiof0_ss2_pins[] = {
2470         /* SS2 */
2471         RCAR_GP_PIN(5, 21),
2472 };
2473 static const unsigned int msiof0_ss2_mux[] = {
2474         MSIOF0_SS2_MARK,
2475 };
2476 static const unsigned int msiof0_txd_pins[] = {
2477         /* TXD */
2478         RCAR_GP_PIN(5, 20),
2479 };
2480 static const unsigned int msiof0_txd_mux[] = {
2481         MSIOF0_TXD_MARK,
2482 };
2483 static const unsigned int msiof0_rxd_pins[] = {
2484         /* RXD */
2485         RCAR_GP_PIN(5, 22),
2486 };
2487 static const unsigned int msiof0_rxd_mux[] = {
2488         MSIOF0_RXD_MARK,
2489 };
2490 /* - MSIOF1 ----------------------------------------------------------------- */
2491 static const unsigned int msiof1_clk_a_pins[] = {
2492         /* SCK */
2493         RCAR_GP_PIN(6, 8),
2494 };
2495 static const unsigned int msiof1_clk_a_mux[] = {
2496         MSIOF1_SCK_A_MARK,
2497 };
2498 static const unsigned int msiof1_sync_a_pins[] = {
2499         /* SYNC */
2500         RCAR_GP_PIN(6, 9),
2501 };
2502 static const unsigned int msiof1_sync_a_mux[] = {
2503         MSIOF1_SYNC_A_MARK,
2504 };
2505 static const unsigned int msiof1_ss1_a_pins[] = {
2506         /* SS1 */
2507         RCAR_GP_PIN(6, 5),
2508 };
2509 static const unsigned int msiof1_ss1_a_mux[] = {
2510         MSIOF1_SS1_A_MARK,
2511 };
2512 static const unsigned int msiof1_ss2_a_pins[] = {
2513         /* SS2 */
2514         RCAR_GP_PIN(6, 6),
2515 };
2516 static const unsigned int msiof1_ss2_a_mux[] = {
2517         MSIOF1_SS2_A_MARK,
2518 };
2519 static const unsigned int msiof1_txd_a_pins[] = {
2520         /* TXD */
2521         RCAR_GP_PIN(6, 7),
2522 };
2523 static const unsigned int msiof1_txd_a_mux[] = {
2524         MSIOF1_TXD_A_MARK,
2525 };
2526 static const unsigned int msiof1_rxd_a_pins[] = {
2527         /* RXD */
2528         RCAR_GP_PIN(6, 10),
2529 };
2530 static const unsigned int msiof1_rxd_a_mux[] = {
2531         MSIOF1_RXD_A_MARK,
2532 };
2533 static const unsigned int msiof1_clk_b_pins[] = {
2534         /* SCK */
2535         RCAR_GP_PIN(5, 9),
2536 };
2537 static const unsigned int msiof1_clk_b_mux[] = {
2538         MSIOF1_SCK_B_MARK,
2539 };
2540 static const unsigned int msiof1_sync_b_pins[] = {
2541         /* SYNC */
2542         RCAR_GP_PIN(5, 3),
2543 };
2544 static const unsigned int msiof1_sync_b_mux[] = {
2545         MSIOF1_SYNC_B_MARK,
2546 };
2547 static const unsigned int msiof1_ss1_b_pins[] = {
2548         /* SS1 */
2549         RCAR_GP_PIN(5, 4),
2550 };
2551 static const unsigned int msiof1_ss1_b_mux[] = {
2552         MSIOF1_SS1_B_MARK,
2553 };
2554 static const unsigned int msiof1_ss2_b_pins[] = {
2555         /* SS2 */
2556         RCAR_GP_PIN(5, 0),
2557 };
2558 static const unsigned int msiof1_ss2_b_mux[] = {
2559         MSIOF1_SS2_B_MARK,
2560 };
2561 static const unsigned int msiof1_txd_b_pins[] = {
2562         /* TXD */
2563         RCAR_GP_PIN(5, 8),
2564 };
2565 static const unsigned int msiof1_txd_b_mux[] = {
2566         MSIOF1_TXD_B_MARK,
2567 };
2568 static const unsigned int msiof1_rxd_b_pins[] = {
2569         /* RXD */
2570         RCAR_GP_PIN(5, 7),
2571 };
2572 static const unsigned int msiof1_rxd_b_mux[] = {
2573         MSIOF1_RXD_B_MARK,
2574 };
2575 static const unsigned int msiof1_clk_c_pins[] = {
2576         /* SCK */
2577         RCAR_GP_PIN(6, 17),
2578 };
2579 static const unsigned int msiof1_clk_c_mux[] = {
2580         MSIOF1_SCK_C_MARK,
2581 };
2582 static const unsigned int msiof1_sync_c_pins[] = {
2583         /* SYNC */
2584         RCAR_GP_PIN(6, 18),
2585 };
2586 static const unsigned int msiof1_sync_c_mux[] = {
2587         MSIOF1_SYNC_C_MARK,
2588 };
2589 static const unsigned int msiof1_ss1_c_pins[] = {
2590         /* SS1 */
2591         RCAR_GP_PIN(6, 21),
2592 };
2593 static const unsigned int msiof1_ss1_c_mux[] = {
2594         MSIOF1_SS1_C_MARK,
2595 };
2596 static const unsigned int msiof1_ss2_c_pins[] = {
2597         /* SS2 */
2598         RCAR_GP_PIN(6, 27),
2599 };
2600 static const unsigned int msiof1_ss2_c_mux[] = {
2601         MSIOF1_SS2_C_MARK,
2602 };
2603 static const unsigned int msiof1_txd_c_pins[] = {
2604         /* TXD */
2605         RCAR_GP_PIN(6, 20),
2606 };
2607 static const unsigned int msiof1_txd_c_mux[] = {
2608         MSIOF1_TXD_C_MARK,
2609 };
2610 static const unsigned int msiof1_rxd_c_pins[] = {
2611         /* RXD */
2612         RCAR_GP_PIN(6, 19),
2613 };
2614 static const unsigned int msiof1_rxd_c_mux[] = {
2615         MSIOF1_RXD_C_MARK,
2616 };
2617 static const unsigned int msiof1_clk_d_pins[] = {
2618         /* SCK */
2619         RCAR_GP_PIN(5, 12),
2620 };
2621 static const unsigned int msiof1_clk_d_mux[] = {
2622         MSIOF1_SCK_D_MARK,
2623 };
2624 static const unsigned int msiof1_sync_d_pins[] = {
2625         /* SYNC */
2626         RCAR_GP_PIN(5, 15),
2627 };
2628 static const unsigned int msiof1_sync_d_mux[] = {
2629         MSIOF1_SYNC_D_MARK,
2630 };
2631 static const unsigned int msiof1_ss1_d_pins[] = {
2632         /* SS1 */
2633         RCAR_GP_PIN(5, 16),
2634 };
2635 static const unsigned int msiof1_ss1_d_mux[] = {
2636         MSIOF1_SS1_D_MARK,
2637 };
2638 static const unsigned int msiof1_ss2_d_pins[] = {
2639         /* SS2 */
2640         RCAR_GP_PIN(5, 21),
2641 };
2642 static const unsigned int msiof1_ss2_d_mux[] = {
2643         MSIOF1_SS2_D_MARK,
2644 };
2645 static const unsigned int msiof1_txd_d_pins[] = {
2646         /* TXD */
2647         RCAR_GP_PIN(5, 14),
2648 };
2649 static const unsigned int msiof1_txd_d_mux[] = {
2650         MSIOF1_TXD_D_MARK,
2651 };
2652 static const unsigned int msiof1_rxd_d_pins[] = {
2653         /* RXD */
2654         RCAR_GP_PIN(5, 13),
2655 };
2656 static const unsigned int msiof1_rxd_d_mux[] = {
2657         MSIOF1_RXD_D_MARK,
2658 };
2659 static const unsigned int msiof1_clk_e_pins[] = {
2660         /* SCK */
2661         RCAR_GP_PIN(3, 0),
2662 };
2663 static const unsigned int msiof1_clk_e_mux[] = {
2664         MSIOF1_SCK_E_MARK,
2665 };
2666 static const unsigned int msiof1_sync_e_pins[] = {
2667         /* SYNC */
2668         RCAR_GP_PIN(3, 1),
2669 };
2670 static const unsigned int msiof1_sync_e_mux[] = {
2671         MSIOF1_SYNC_E_MARK,
2672 };
2673 static const unsigned int msiof1_ss1_e_pins[] = {
2674         /* SS1 */
2675         RCAR_GP_PIN(3, 4),
2676 };
2677 static const unsigned int msiof1_ss1_e_mux[] = {
2678         MSIOF1_SS1_E_MARK,
2679 };
2680 static const unsigned int msiof1_ss2_e_pins[] = {
2681         /* SS2 */
2682         RCAR_GP_PIN(3, 5),
2683 };
2684 static const unsigned int msiof1_ss2_e_mux[] = {
2685         MSIOF1_SS2_E_MARK,
2686 };
2687 static const unsigned int msiof1_txd_e_pins[] = {
2688         /* TXD */
2689         RCAR_GP_PIN(3, 3),
2690 };
2691 static const unsigned int msiof1_txd_e_mux[] = {
2692         MSIOF1_TXD_E_MARK,
2693 };
2694 static const unsigned int msiof1_rxd_e_pins[] = {
2695         /* RXD */
2696         RCAR_GP_PIN(3, 2),
2697 };
2698 static const unsigned int msiof1_rxd_e_mux[] = {
2699         MSIOF1_RXD_E_MARK,
2700 };
2701 static const unsigned int msiof1_clk_f_pins[] = {
2702         /* SCK */
2703         RCAR_GP_PIN(5, 23),
2704 };
2705 static const unsigned int msiof1_clk_f_mux[] = {
2706         MSIOF1_SCK_F_MARK,
2707 };
2708 static const unsigned int msiof1_sync_f_pins[] = {
2709         /* SYNC */
2710         RCAR_GP_PIN(5, 24),
2711 };
2712 static const unsigned int msiof1_sync_f_mux[] = {
2713         MSIOF1_SYNC_F_MARK,
2714 };
2715 static const unsigned int msiof1_ss1_f_pins[] = {
2716         /* SS1 */
2717         RCAR_GP_PIN(6, 1),
2718 };
2719 static const unsigned int msiof1_ss1_f_mux[] = {
2720         MSIOF1_SS1_F_MARK,
2721 };
2722 static const unsigned int msiof1_ss2_f_pins[] = {
2723         /* SS2 */
2724         RCAR_GP_PIN(6, 2),
2725 };
2726 static const unsigned int msiof1_ss2_f_mux[] = {
2727         MSIOF1_SS2_F_MARK,
2728 };
2729 static const unsigned int msiof1_txd_f_pins[] = {
2730         /* TXD */
2731         RCAR_GP_PIN(6, 0),
2732 };
2733 static const unsigned int msiof1_txd_f_mux[] = {
2734         MSIOF1_TXD_F_MARK,
2735 };
2736 static const unsigned int msiof1_rxd_f_pins[] = {
2737         /* RXD */
2738         RCAR_GP_PIN(5, 25),
2739 };
2740 static const unsigned int msiof1_rxd_f_mux[] = {
2741         MSIOF1_RXD_F_MARK,
2742 };
2743 static const unsigned int msiof1_clk_g_pins[] = {
2744         /* SCK */
2745         RCAR_GP_PIN(3, 6),
2746 };
2747 static const unsigned int msiof1_clk_g_mux[] = {
2748         MSIOF1_SCK_G_MARK,
2749 };
2750 static const unsigned int msiof1_sync_g_pins[] = {
2751         /* SYNC */
2752         RCAR_GP_PIN(3, 7),
2753 };
2754 static const unsigned int msiof1_sync_g_mux[] = {
2755         MSIOF1_SYNC_G_MARK,
2756 };
2757 static const unsigned int msiof1_ss1_g_pins[] = {
2758         /* SS1 */
2759         RCAR_GP_PIN(3, 10),
2760 };
2761 static const unsigned int msiof1_ss1_g_mux[] = {
2762         MSIOF1_SS1_G_MARK,
2763 };
2764 static const unsigned int msiof1_ss2_g_pins[] = {
2765         /* SS2 */
2766         RCAR_GP_PIN(3, 11),
2767 };
2768 static const unsigned int msiof1_ss2_g_mux[] = {
2769         MSIOF1_SS2_G_MARK,
2770 };
2771 static const unsigned int msiof1_txd_g_pins[] = {
2772         /* TXD */
2773         RCAR_GP_PIN(3, 9),
2774 };
2775 static const unsigned int msiof1_txd_g_mux[] = {
2776         MSIOF1_TXD_G_MARK,
2777 };
2778 static const unsigned int msiof1_rxd_g_pins[] = {
2779         /* RXD */
2780         RCAR_GP_PIN(3, 8),
2781 };
2782 static const unsigned int msiof1_rxd_g_mux[] = {
2783         MSIOF1_RXD_G_MARK,
2784 };
2785 /* - MSIOF2 ----------------------------------------------------------------- */
2786 static const unsigned int msiof2_clk_a_pins[] = {
2787         /* SCK */
2788         RCAR_GP_PIN(1, 9),
2789 };
2790 static const unsigned int msiof2_clk_a_mux[] = {
2791         MSIOF2_SCK_A_MARK,
2792 };
2793 static const unsigned int msiof2_sync_a_pins[] = {
2794         /* SYNC */
2795         RCAR_GP_PIN(1, 8),
2796 };
2797 static const unsigned int msiof2_sync_a_mux[] = {
2798         MSIOF2_SYNC_A_MARK,
2799 };
2800 static const unsigned int msiof2_ss1_a_pins[] = {
2801         /* SS1 */
2802         RCAR_GP_PIN(1, 6),
2803 };
2804 static const unsigned int msiof2_ss1_a_mux[] = {
2805         MSIOF2_SS1_A_MARK,
2806 };
2807 static const unsigned int msiof2_ss2_a_pins[] = {
2808         /* SS2 */
2809         RCAR_GP_PIN(1, 7),
2810 };
2811 static const unsigned int msiof2_ss2_a_mux[] = {
2812         MSIOF2_SS2_A_MARK,
2813 };
2814 static const unsigned int msiof2_txd_a_pins[] = {
2815         /* TXD */
2816         RCAR_GP_PIN(1, 11),
2817 };
2818 static const unsigned int msiof2_txd_a_mux[] = {
2819         MSIOF2_TXD_A_MARK,
2820 };
2821 static const unsigned int msiof2_rxd_a_pins[] = {
2822         /* RXD */
2823         RCAR_GP_PIN(1, 10),
2824 };
2825 static const unsigned int msiof2_rxd_a_mux[] = {
2826         MSIOF2_RXD_A_MARK,
2827 };
2828 static const unsigned int msiof2_clk_b_pins[] = {
2829         /* SCK */
2830         RCAR_GP_PIN(0, 4),
2831 };
2832 static const unsigned int msiof2_clk_b_mux[] = {
2833         MSIOF2_SCK_B_MARK,
2834 };
2835 static const unsigned int msiof2_sync_b_pins[] = {
2836         /* SYNC */
2837         RCAR_GP_PIN(0, 5),
2838 };
2839 static const unsigned int msiof2_sync_b_mux[] = {
2840         MSIOF2_SYNC_B_MARK,
2841 };
2842 static const unsigned int msiof2_ss1_b_pins[] = {
2843         /* SS1 */
2844         RCAR_GP_PIN(0, 0),
2845 };
2846 static const unsigned int msiof2_ss1_b_mux[] = {
2847         MSIOF2_SS1_B_MARK,
2848 };
2849 static const unsigned int msiof2_ss2_b_pins[] = {
2850         /* SS2 */
2851         RCAR_GP_PIN(0, 1),
2852 };
2853 static const unsigned int msiof2_ss2_b_mux[] = {
2854         MSIOF2_SS2_B_MARK,
2855 };
2856 static const unsigned int msiof2_txd_b_pins[] = {
2857         /* TXD */
2858         RCAR_GP_PIN(0, 7),
2859 };
2860 static const unsigned int msiof2_txd_b_mux[] = {
2861         MSIOF2_TXD_B_MARK,
2862 };
2863 static const unsigned int msiof2_rxd_b_pins[] = {
2864         /* RXD */
2865         RCAR_GP_PIN(0, 6),
2866 };
2867 static const unsigned int msiof2_rxd_b_mux[] = {
2868         MSIOF2_RXD_B_MARK,
2869 };
2870 static const unsigned int msiof2_clk_c_pins[] = {
2871         /* SCK */
2872         RCAR_GP_PIN(2, 12),
2873 };
2874 static const unsigned int msiof2_clk_c_mux[] = {
2875         MSIOF2_SCK_C_MARK,
2876 };
2877 static const unsigned int msiof2_sync_c_pins[] = {
2878         /* SYNC */
2879         RCAR_GP_PIN(2, 11),
2880 };
2881 static const unsigned int msiof2_sync_c_mux[] = {
2882         MSIOF2_SYNC_C_MARK,
2883 };
2884 static const unsigned int msiof2_ss1_c_pins[] = {
2885         /* SS1 */
2886         RCAR_GP_PIN(2, 10),
2887 };
2888 static const unsigned int msiof2_ss1_c_mux[] = {
2889         MSIOF2_SS1_C_MARK,
2890 };
2891 static const unsigned int msiof2_ss2_c_pins[] = {
2892         /* SS2 */
2893         RCAR_GP_PIN(2, 9),
2894 };
2895 static const unsigned int msiof2_ss2_c_mux[] = {
2896         MSIOF2_SS2_C_MARK,
2897 };
2898 static const unsigned int msiof2_txd_c_pins[] = {
2899         /* TXD */
2900         RCAR_GP_PIN(2, 14),
2901 };
2902 static const unsigned int msiof2_txd_c_mux[] = {
2903         MSIOF2_TXD_C_MARK,
2904 };
2905 static const unsigned int msiof2_rxd_c_pins[] = {
2906         /* RXD */
2907         RCAR_GP_PIN(2, 13),
2908 };
2909 static const unsigned int msiof2_rxd_c_mux[] = {
2910         MSIOF2_RXD_C_MARK,
2911 };
2912 static const unsigned int msiof2_clk_d_pins[] = {
2913         /* SCK */
2914         RCAR_GP_PIN(0, 8),
2915 };
2916 static const unsigned int msiof2_clk_d_mux[] = {
2917         MSIOF2_SCK_D_MARK,
2918 };
2919 static const unsigned int msiof2_sync_d_pins[] = {
2920         /* SYNC */
2921         RCAR_GP_PIN(0, 9),
2922 };
2923 static const unsigned int msiof2_sync_d_mux[] = {
2924         MSIOF2_SYNC_D_MARK,
2925 };
2926 static const unsigned int msiof2_ss1_d_pins[] = {
2927         /* SS1 */
2928         RCAR_GP_PIN(0, 12),
2929 };
2930 static const unsigned int msiof2_ss1_d_mux[] = {
2931         MSIOF2_SS1_D_MARK,
2932 };
2933 static const unsigned int msiof2_ss2_d_pins[] = {
2934         /* SS2 */
2935         RCAR_GP_PIN(0, 13),
2936 };
2937 static const unsigned int msiof2_ss2_d_mux[] = {
2938         MSIOF2_SS2_D_MARK,
2939 };
2940 static const unsigned int msiof2_txd_d_pins[] = {
2941         /* TXD */
2942         RCAR_GP_PIN(0, 11),
2943 };
2944 static const unsigned int msiof2_txd_d_mux[] = {
2945         MSIOF2_TXD_D_MARK,
2946 };
2947 static const unsigned int msiof2_rxd_d_pins[] = {
2948         /* RXD */
2949         RCAR_GP_PIN(0, 10),
2950 };
2951 static const unsigned int msiof2_rxd_d_mux[] = {
2952         MSIOF2_RXD_D_MARK,
2953 };
2954 /* - MSIOF3 ----------------------------------------------------------------- */
2955 static const unsigned int msiof3_clk_a_pins[] = {
2956         /* SCK */
2957         RCAR_GP_PIN(0, 0),
2958 };
2959 static const unsigned int msiof3_clk_a_mux[] = {
2960         MSIOF3_SCK_A_MARK,
2961 };
2962 static const unsigned int msiof3_sync_a_pins[] = {
2963         /* SYNC */
2964         RCAR_GP_PIN(0, 1),
2965 };
2966 static const unsigned int msiof3_sync_a_mux[] = {
2967         MSIOF3_SYNC_A_MARK,
2968 };
2969 static const unsigned int msiof3_ss1_a_pins[] = {
2970         /* SS1 */
2971         RCAR_GP_PIN(0, 14),
2972 };
2973 static const unsigned int msiof3_ss1_a_mux[] = {
2974         MSIOF3_SS1_A_MARK,
2975 };
2976 static const unsigned int msiof3_ss2_a_pins[] = {
2977         /* SS2 */
2978         RCAR_GP_PIN(0, 15),
2979 };
2980 static const unsigned int msiof3_ss2_a_mux[] = {
2981         MSIOF3_SS2_A_MARK,
2982 };
2983 static const unsigned int msiof3_txd_a_pins[] = {
2984         /* TXD */
2985         RCAR_GP_PIN(0, 3),
2986 };
2987 static const unsigned int msiof3_txd_a_mux[] = {
2988         MSIOF3_TXD_A_MARK,
2989 };
2990 static const unsigned int msiof3_rxd_a_pins[] = {
2991         /* RXD */
2992         RCAR_GP_PIN(0, 2),
2993 };
2994 static const unsigned int msiof3_rxd_a_mux[] = {
2995         MSIOF3_RXD_A_MARK,
2996 };
2997 static const unsigned int msiof3_clk_b_pins[] = {
2998         /* SCK */
2999         RCAR_GP_PIN(1, 2),
3000 };
3001 static const unsigned int msiof3_clk_b_mux[] = {
3002         MSIOF3_SCK_B_MARK,
3003 };
3004 static const unsigned int msiof3_sync_b_pins[] = {
3005         /* SYNC */
3006         RCAR_GP_PIN(1, 0),
3007 };
3008 static const unsigned int msiof3_sync_b_mux[] = {
3009         MSIOF3_SYNC_B_MARK,
3010 };
3011 static const unsigned int msiof3_ss1_b_pins[] = {
3012         /* SS1 */
3013         RCAR_GP_PIN(1, 4),
3014 };
3015 static const unsigned int msiof3_ss1_b_mux[] = {
3016         MSIOF3_SS1_B_MARK,
3017 };
3018 static const unsigned int msiof3_ss2_b_pins[] = {
3019         /* SS2 */
3020         RCAR_GP_PIN(1, 5),
3021 };
3022 static const unsigned int msiof3_ss2_b_mux[] = {
3023         MSIOF3_SS2_B_MARK,
3024 };
3025 static const unsigned int msiof3_txd_b_pins[] = {
3026         /* TXD */
3027         RCAR_GP_PIN(1, 1),
3028 };
3029 static const unsigned int msiof3_txd_b_mux[] = {
3030         MSIOF3_TXD_B_MARK,
3031 };
3032 static const unsigned int msiof3_rxd_b_pins[] = {
3033         /* RXD */
3034         RCAR_GP_PIN(1, 3),
3035 };
3036 static const unsigned int msiof3_rxd_b_mux[] = {
3037         MSIOF3_RXD_B_MARK,
3038 };
3039 static const unsigned int msiof3_clk_c_pins[] = {
3040         /* SCK */
3041         RCAR_GP_PIN(1, 12),
3042 };
3043 static const unsigned int msiof3_clk_c_mux[] = {
3044         MSIOF3_SCK_C_MARK,
3045 };
3046 static const unsigned int msiof3_sync_c_pins[] = {
3047         /* SYNC */
3048         RCAR_GP_PIN(1, 13),
3049 };
3050 static const unsigned int msiof3_sync_c_mux[] = {
3051         MSIOF3_SYNC_C_MARK,
3052 };
3053 static const unsigned int msiof3_txd_c_pins[] = {
3054         /* TXD */
3055         RCAR_GP_PIN(1, 15),
3056 };
3057 static const unsigned int msiof3_txd_c_mux[] = {
3058         MSIOF3_TXD_C_MARK,
3059 };
3060 static const unsigned int msiof3_rxd_c_pins[] = {
3061         /* RXD */
3062         RCAR_GP_PIN(1, 14),
3063 };
3064 static const unsigned int msiof3_rxd_c_mux[] = {
3065         MSIOF3_RXD_C_MARK,
3066 };
3067 static const unsigned int msiof3_clk_d_pins[] = {
3068         /* SCK */
3069         RCAR_GP_PIN(1, 22),
3070 };
3071 static const unsigned int msiof3_clk_d_mux[] = {
3072         MSIOF3_SCK_D_MARK,
3073 };
3074 static const unsigned int msiof3_sync_d_pins[] = {
3075         /* SYNC */
3076         RCAR_GP_PIN(1, 23),
3077 };
3078 static const unsigned int msiof3_sync_d_mux[] = {
3079         MSIOF3_SYNC_D_MARK,
3080 };
3081 static const unsigned int msiof3_ss1_d_pins[] = {
3082         /* SS1 */
3083         RCAR_GP_PIN(1, 26),
3084 };
3085 static const unsigned int msiof3_ss1_d_mux[] = {
3086         MSIOF3_SS1_D_MARK,
3087 };
3088 static const unsigned int msiof3_txd_d_pins[] = {
3089         /* TXD */
3090         RCAR_GP_PIN(1, 25),
3091 };
3092 static const unsigned int msiof3_txd_d_mux[] = {
3093         MSIOF3_TXD_D_MARK,
3094 };
3095 static const unsigned int msiof3_rxd_d_pins[] = {
3096         /* RXD */
3097         RCAR_GP_PIN(1, 24),
3098 };
3099 static const unsigned int msiof3_rxd_d_mux[] = {
3100         MSIOF3_RXD_D_MARK,
3101 };
3102
3103 static const unsigned int msiof3_clk_e_pins[] = {
3104         /* SCK */
3105         RCAR_GP_PIN(2, 3),
3106 };
3107 static const unsigned int msiof3_clk_e_mux[] = {
3108         MSIOF3_SCK_E_MARK,
3109 };
3110 static const unsigned int msiof3_sync_e_pins[] = {
3111         /* SYNC */
3112         RCAR_GP_PIN(2, 2),
3113 };
3114 static const unsigned int msiof3_sync_e_mux[] = {
3115         MSIOF3_SYNC_E_MARK,
3116 };
3117 static const unsigned int msiof3_ss1_e_pins[] = {
3118         /* SS1 */
3119         RCAR_GP_PIN(2, 1),
3120 };
3121 static const unsigned int msiof3_ss1_e_mux[] = {
3122         MSIOF3_SS1_E_MARK,
3123 };
3124 static const unsigned int msiof3_ss2_e_pins[] = {
3125         /* SS1 */
3126         RCAR_GP_PIN(2, 0),
3127 };
3128 static const unsigned int msiof3_ss2_e_mux[] = {
3129         MSIOF3_SS2_E_MARK,
3130 };
3131 static const unsigned int msiof3_txd_e_pins[] = {
3132         /* TXD */
3133         RCAR_GP_PIN(2, 5),
3134 };
3135 static const unsigned int msiof3_txd_e_mux[] = {
3136         MSIOF3_TXD_E_MARK,
3137 };
3138 static const unsigned int msiof3_rxd_e_pins[] = {
3139         /* RXD */
3140         RCAR_GP_PIN(2, 4),
3141 };
3142 static const unsigned int msiof3_rxd_e_mux[] = {
3143         MSIOF3_RXD_E_MARK,
3144 };
3145
3146 /* - PWM0 --------------------------------------------------------------------*/
3147 static const unsigned int pwm0_pins[] = {
3148         /* PWM */
3149         RCAR_GP_PIN(2, 6),
3150 };
3151 static const unsigned int pwm0_mux[] = {
3152         PWM0_MARK,
3153 };
3154 /* - PWM1 --------------------------------------------------------------------*/
3155 static const unsigned int pwm1_a_pins[] = {
3156         /* PWM */
3157         RCAR_GP_PIN(2, 7),
3158 };
3159 static const unsigned int pwm1_a_mux[] = {
3160         PWM1_A_MARK,
3161 };
3162 static const unsigned int pwm1_b_pins[] = {
3163         /* PWM */
3164         RCAR_GP_PIN(1, 8),
3165 };
3166 static const unsigned int pwm1_b_mux[] = {
3167         PWM1_B_MARK,
3168 };
3169 /* - PWM2 --------------------------------------------------------------------*/
3170 static const unsigned int pwm2_a_pins[] = {
3171         /* PWM */
3172         RCAR_GP_PIN(2, 8),
3173 };
3174 static const unsigned int pwm2_a_mux[] = {
3175         PWM2_A_MARK,
3176 };
3177 static const unsigned int pwm2_b_pins[] = {
3178         /* PWM */
3179         RCAR_GP_PIN(1, 11),
3180 };
3181 static const unsigned int pwm2_b_mux[] = {
3182         PWM2_B_MARK,
3183 };
3184 /* - PWM3 --------------------------------------------------------------------*/
3185 static const unsigned int pwm3_a_pins[] = {
3186         /* PWM */
3187         RCAR_GP_PIN(1, 0),
3188 };
3189 static const unsigned int pwm3_a_mux[] = {
3190         PWM3_A_MARK,
3191 };
3192 static const unsigned int pwm3_b_pins[] = {
3193         /* PWM */
3194         RCAR_GP_PIN(2, 2),
3195 };
3196 static const unsigned int pwm3_b_mux[] = {
3197         PWM3_B_MARK,
3198 };
3199 /* - PWM4 --------------------------------------------------------------------*/
3200 static const unsigned int pwm4_a_pins[] = {
3201         /* PWM */
3202         RCAR_GP_PIN(1, 1),
3203 };
3204 static const unsigned int pwm4_a_mux[] = {
3205         PWM4_A_MARK,
3206 };
3207 static const unsigned int pwm4_b_pins[] = {
3208         /* PWM */
3209         RCAR_GP_PIN(2, 3),
3210 };
3211 static const unsigned int pwm4_b_mux[] = {
3212         PWM4_B_MARK,
3213 };
3214 /* - PWM5 --------------------------------------------------------------------*/
3215 static const unsigned int pwm5_a_pins[] = {
3216         /* PWM */
3217         RCAR_GP_PIN(1, 2),
3218 };
3219 static const unsigned int pwm5_a_mux[] = {
3220         PWM5_A_MARK,
3221 };
3222 static const unsigned int pwm5_b_pins[] = {
3223         /* PWM */
3224         RCAR_GP_PIN(2, 4),
3225 };
3226 static const unsigned int pwm5_b_mux[] = {
3227         PWM5_B_MARK,
3228 };
3229 /* - PWM6 --------------------------------------------------------------------*/
3230 static const unsigned int pwm6_a_pins[] = {
3231         /* PWM */
3232         RCAR_GP_PIN(1, 3),
3233 };
3234 static const unsigned int pwm6_a_mux[] = {
3235         PWM6_A_MARK,
3236 };
3237 static const unsigned int pwm6_b_pins[] = {
3238         /* PWM */
3239         RCAR_GP_PIN(2, 5),
3240 };
3241 static const unsigned int pwm6_b_mux[] = {
3242         PWM6_B_MARK,
3243 };
3244
3245 /* - SCIF0 ------------------------------------------------------------------ */
3246 static const unsigned int scif0_data_pins[] = {
3247         /* RX, TX */
3248         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3249 };
3250 static const unsigned int scif0_data_mux[] = {
3251         RX0_MARK, TX0_MARK,
3252 };
3253 static const unsigned int scif0_clk_pins[] = {
3254         /* SCK */
3255         RCAR_GP_PIN(5, 0),
3256 };
3257 static const unsigned int scif0_clk_mux[] = {
3258         SCK0_MARK,
3259 };
3260 static const unsigned int scif0_ctrl_pins[] = {
3261         /* RTS, CTS */
3262         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3263 };
3264 static const unsigned int scif0_ctrl_mux[] = {
3265         RTS0_N_MARK, CTS0_N_MARK,
3266 };
3267 /* - SCIF1 ------------------------------------------------------------------ */
3268 static const unsigned int scif1_data_a_pins[] = {
3269         /* RX, TX */
3270         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3271 };
3272 static const unsigned int scif1_data_a_mux[] = {
3273         RX1_A_MARK, TX1_A_MARK,
3274 };
3275 static const unsigned int scif1_clk_pins[] = {
3276         /* SCK */
3277         RCAR_GP_PIN(6, 21),
3278 };
3279 static const unsigned int scif1_clk_mux[] = {
3280         SCK1_MARK,
3281 };
3282 static const unsigned int scif1_ctrl_pins[] = {
3283         /* RTS, CTS */
3284         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3285 };
3286 static const unsigned int scif1_ctrl_mux[] = {
3287         RTS1_N_MARK, CTS1_N_MARK,
3288 };
3289
3290 static const unsigned int scif1_data_b_pins[] = {
3291         /* RX, TX */
3292         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3293 };
3294 static const unsigned int scif1_data_b_mux[] = {
3295         RX1_B_MARK, TX1_B_MARK,
3296 };
3297 /* - SCIF2 ------------------------------------------------------------------ */
3298 static const unsigned int scif2_data_a_pins[] = {
3299         /* RX, TX */
3300         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3301 };
3302 static const unsigned int scif2_data_a_mux[] = {
3303         RX2_A_MARK, TX2_A_MARK,
3304 };
3305 static const unsigned int scif2_clk_pins[] = {
3306         /* SCK */
3307         RCAR_GP_PIN(5, 9),
3308 };
3309 static const unsigned int scif2_clk_mux[] = {
3310         SCK2_MARK,
3311 };
3312 static const unsigned int scif2_data_b_pins[] = {
3313         /* RX, TX */
3314         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3315 };
3316 static const unsigned int scif2_data_b_mux[] = {
3317         RX2_B_MARK, TX2_B_MARK,
3318 };
3319 /* - SCIF3 ------------------------------------------------------------------ */
3320 static const unsigned int scif3_data_a_pins[] = {
3321         /* RX, TX */
3322         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3323 };
3324 static const unsigned int scif3_data_a_mux[] = {
3325         RX3_A_MARK, TX3_A_MARK,
3326 };
3327 static const unsigned int scif3_clk_pins[] = {
3328         /* SCK */
3329         RCAR_GP_PIN(1, 22),
3330 };
3331 static const unsigned int scif3_clk_mux[] = {
3332         SCK3_MARK,
3333 };
3334 static const unsigned int scif3_ctrl_pins[] = {
3335         /* RTS, CTS */
3336         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3337 };
3338 static const unsigned int scif3_ctrl_mux[] = {
3339         RTS3_N_MARK, CTS3_N_MARK,
3340 };
3341 static const unsigned int scif3_data_b_pins[] = {
3342         /* RX, TX */
3343         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3344 };
3345 static const unsigned int scif3_data_b_mux[] = {
3346         RX3_B_MARK, TX3_B_MARK,
3347 };
3348 /* - SCIF4 ------------------------------------------------------------------ */
3349 static const unsigned int scif4_data_a_pins[] = {
3350         /* RX, TX */
3351         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3352 };
3353 static const unsigned int scif4_data_a_mux[] = {
3354         RX4_A_MARK, TX4_A_MARK,
3355 };
3356 static const unsigned int scif4_clk_a_pins[] = {
3357         /* SCK */
3358         RCAR_GP_PIN(2, 10),
3359 };
3360 static const unsigned int scif4_clk_a_mux[] = {
3361         SCK4_A_MARK,
3362 };
3363 static const unsigned int scif4_ctrl_a_pins[] = {
3364         /* RTS, CTS */
3365         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3366 };
3367 static const unsigned int scif4_ctrl_a_mux[] = {
3368         RTS4_N_A_MARK, CTS4_N_A_MARK,
3369 };
3370 static const unsigned int scif4_data_b_pins[] = {
3371         /* RX, TX */
3372         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3373 };
3374 static const unsigned int scif4_data_b_mux[] = {
3375         RX4_B_MARK, TX4_B_MARK,
3376 };
3377 static const unsigned int scif4_clk_b_pins[] = {
3378         /* SCK */
3379         RCAR_GP_PIN(1, 5),
3380 };
3381 static const unsigned int scif4_clk_b_mux[] = {
3382         SCK4_B_MARK,
3383 };
3384 static const unsigned int scif4_ctrl_b_pins[] = {
3385         /* RTS, CTS */
3386         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3387 };
3388 static const unsigned int scif4_ctrl_b_mux[] = {
3389         RTS4_N_B_MARK, CTS4_N_B_MARK,
3390 };
3391 static const unsigned int scif4_data_c_pins[] = {
3392         /* RX, TX */
3393         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3394 };
3395 static const unsigned int scif4_data_c_mux[] = {
3396         RX4_C_MARK, TX4_C_MARK,
3397 };
3398 static const unsigned int scif4_clk_c_pins[] = {
3399         /* SCK */
3400         RCAR_GP_PIN(0, 8),
3401 };
3402 static const unsigned int scif4_clk_c_mux[] = {
3403         SCK4_C_MARK,
3404 };
3405 static const unsigned int scif4_ctrl_c_pins[] = {
3406         /* RTS, CTS */
3407         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3408 };
3409 static const unsigned int scif4_ctrl_c_mux[] = {
3410         RTS4_N_C_MARK, CTS4_N_C_MARK,
3411 };
3412 /* - SCIF5 ------------------------------------------------------------------ */
3413 static const unsigned int scif5_data_a_pins[] = {
3414         /* RX, TX */
3415         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3416 };
3417 static const unsigned int scif5_data_a_mux[] = {
3418         RX5_A_MARK, TX5_A_MARK,
3419 };
3420 static const unsigned int scif5_clk_a_pins[] = {
3421         /* SCK */
3422         RCAR_GP_PIN(6, 21),
3423 };
3424 static const unsigned int scif5_clk_a_mux[] = {
3425         SCK5_A_MARK,
3426 };
3427
3428 static const unsigned int scif5_data_b_pins[] = {
3429         /* RX, TX */
3430         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3431 };
3432 static const unsigned int scif5_data_b_mux[] = {
3433         RX5_B_MARK, TX5_B_MARK,
3434 };
3435 static const unsigned int scif5_clk_b_pins[] = {
3436         /* SCK */
3437         RCAR_GP_PIN(5, 0),
3438 };
3439 static const unsigned int scif5_clk_b_mux[] = {
3440         SCK5_B_MARK,
3441 };
3442
3443 /* - SCIF Clock ------------------------------------------------------------- */
3444 static const unsigned int scif_clk_a_pins[] = {
3445         /* SCIF_CLK */
3446         RCAR_GP_PIN(6, 23),
3447 };
3448 static const unsigned int scif_clk_a_mux[] = {
3449         SCIF_CLK_A_MARK,
3450 };
3451 static const unsigned int scif_clk_b_pins[] = {
3452         /* SCIF_CLK */
3453         RCAR_GP_PIN(5, 9),
3454 };
3455 static const unsigned int scif_clk_b_mux[] = {
3456         SCIF_CLK_B_MARK,
3457 };
3458
3459 /* - SDHI0 ------------------------------------------------------------------ */
3460 static const unsigned int sdhi0_data1_pins[] = {
3461         /* D0 */
3462         RCAR_GP_PIN(3, 2),
3463 };
3464 static const unsigned int sdhi0_data1_mux[] = {
3465         SD0_DAT0_MARK,
3466 };
3467 static const unsigned int sdhi0_data4_pins[] = {
3468         /* D[0:3] */
3469         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3470         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3471 };
3472 static const unsigned int sdhi0_data4_mux[] = {
3473         SD0_DAT0_MARK, SD0_DAT1_MARK,
3474         SD0_DAT2_MARK, SD0_DAT3_MARK,
3475 };
3476 static const unsigned int sdhi0_ctrl_pins[] = {
3477         /* CLK, CMD */
3478         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3479 };
3480 static const unsigned int sdhi0_ctrl_mux[] = {
3481         SD0_CLK_MARK, SD0_CMD_MARK,
3482 };
3483 static const unsigned int sdhi0_cd_pins[] = {
3484         /* CD */
3485         RCAR_GP_PIN(3, 12),
3486 };
3487 static const unsigned int sdhi0_cd_mux[] = {
3488         SD0_CD_MARK,
3489 };
3490 static const unsigned int sdhi0_wp_pins[] = {
3491         /* WP */
3492         RCAR_GP_PIN(3, 13),
3493 };
3494 static const unsigned int sdhi0_wp_mux[] = {
3495         SD0_WP_MARK,
3496 };
3497 /* - SDHI1 ------------------------------------------------------------------ */
3498 static const unsigned int sdhi1_data1_pins[] = {
3499         /* D0 */
3500         RCAR_GP_PIN(3, 8),
3501 };
3502 static const unsigned int sdhi1_data1_mux[] = {
3503         SD1_DAT0_MARK,
3504 };
3505 static const unsigned int sdhi1_data4_pins[] = {
3506         /* D[0:3] */
3507         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3508         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3509 };
3510 static const unsigned int sdhi1_data4_mux[] = {
3511         SD1_DAT0_MARK, SD1_DAT1_MARK,
3512         SD1_DAT2_MARK, SD1_DAT3_MARK,
3513 };
3514 static const unsigned int sdhi1_ctrl_pins[] = {
3515         /* CLK, CMD */
3516         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3517 };
3518 static const unsigned int sdhi1_ctrl_mux[] = {
3519         SD1_CLK_MARK, SD1_CMD_MARK,
3520 };
3521 static const unsigned int sdhi1_cd_pins[] = {
3522         /* CD */
3523         RCAR_GP_PIN(3, 14),
3524 };
3525 static const unsigned int sdhi1_cd_mux[] = {
3526         SD1_CD_MARK,
3527 };
3528 static const unsigned int sdhi1_wp_pins[] = {
3529         /* WP */
3530         RCAR_GP_PIN(3, 15),
3531 };
3532 static const unsigned int sdhi1_wp_mux[] = {
3533         SD1_WP_MARK,
3534 };
3535 /* - SDHI2 ------------------------------------------------------------------ */
3536 static const unsigned int sdhi2_data1_pins[] = {
3537         /* D0 */
3538         RCAR_GP_PIN(4, 2),
3539 };
3540 static const unsigned int sdhi2_data1_mux[] = {
3541         SD2_DAT0_MARK,
3542 };
3543 static const unsigned int sdhi2_data4_pins[] = {
3544         /* D[0:3] */
3545         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3546         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3547 };
3548 static const unsigned int sdhi2_data4_mux[] = {
3549         SD2_DAT0_MARK, SD2_DAT1_MARK,
3550         SD2_DAT2_MARK, SD2_DAT3_MARK,
3551 };
3552 static const unsigned int sdhi2_data8_pins[] = {
3553         /* D[0:7] */
3554         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3555         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3556         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3557         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3558 };
3559 static const unsigned int sdhi2_data8_mux[] = {
3560         SD2_DAT0_MARK, SD2_DAT1_MARK,
3561         SD2_DAT2_MARK, SD2_DAT3_MARK,
3562         SD2_DAT4_MARK, SD2_DAT5_MARK,
3563         SD2_DAT6_MARK, SD2_DAT7_MARK,
3564 };
3565 static const unsigned int sdhi2_ctrl_pins[] = {
3566         /* CLK, CMD */
3567         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3568 };
3569 static const unsigned int sdhi2_ctrl_mux[] = {
3570         SD2_CLK_MARK, SD2_CMD_MARK,
3571 };
3572 static const unsigned int sdhi2_cd_a_pins[] = {
3573         /* CD */
3574         RCAR_GP_PIN(4, 13),
3575 };
3576 static const unsigned int sdhi2_cd_a_mux[] = {
3577         SD2_CD_A_MARK,
3578 };
3579 static const unsigned int sdhi2_cd_b_pins[] = {
3580         /* CD */
3581         RCAR_GP_PIN(5, 10),
3582 };
3583 static const unsigned int sdhi2_cd_b_mux[] = {
3584         SD2_CD_B_MARK,
3585 };
3586 static const unsigned int sdhi2_wp_a_pins[] = {
3587         /* WP */
3588         RCAR_GP_PIN(4, 14),
3589 };
3590 static const unsigned int sdhi2_wp_a_mux[] = {
3591         SD2_WP_A_MARK,
3592 };
3593 static const unsigned int sdhi2_wp_b_pins[] = {
3594         /* WP */
3595         RCAR_GP_PIN(5, 11),
3596 };
3597 static const unsigned int sdhi2_wp_b_mux[] = {
3598         SD2_WP_B_MARK,
3599 };
3600 static const unsigned int sdhi2_ds_pins[] = {
3601         /* DS */
3602         RCAR_GP_PIN(4, 6),
3603 };
3604 static const unsigned int sdhi2_ds_mux[] = {
3605         SD2_DS_MARK,
3606 };
3607 /* - SDHI3 ------------------------------------------------------------------ */
3608 static const unsigned int sdhi3_data1_pins[] = {
3609         /* D0 */
3610         RCAR_GP_PIN(4, 9),
3611 };
3612 static const unsigned int sdhi3_data1_mux[] = {
3613         SD3_DAT0_MARK,
3614 };
3615 static const unsigned int sdhi3_data4_pins[] = {
3616         /* D[0:3] */
3617         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3618         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3619 };
3620 static const unsigned int sdhi3_data4_mux[] = {
3621         SD3_DAT0_MARK, SD3_DAT1_MARK,
3622         SD3_DAT2_MARK, SD3_DAT3_MARK,
3623 };
3624 static const unsigned int sdhi3_data8_pins[] = {
3625         /* D[0:7] */
3626         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3627         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3628         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3629         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3630 };
3631 static const unsigned int sdhi3_data8_mux[] = {
3632         SD3_DAT0_MARK, SD3_DAT1_MARK,
3633         SD3_DAT2_MARK, SD3_DAT3_MARK,
3634         SD3_DAT4_MARK, SD3_DAT5_MARK,
3635         SD3_DAT6_MARK, SD3_DAT7_MARK,
3636 };
3637 static const unsigned int sdhi3_ctrl_pins[] = {
3638         /* CLK, CMD */
3639         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3640 };
3641 static const unsigned int sdhi3_ctrl_mux[] = {
3642         SD3_CLK_MARK, SD3_CMD_MARK,
3643 };
3644 static const unsigned int sdhi3_cd_pins[] = {
3645         /* CD */
3646         RCAR_GP_PIN(4, 15),
3647 };
3648 static const unsigned int sdhi3_cd_mux[] = {
3649         SD3_CD_MARK,
3650 };
3651 static const unsigned int sdhi3_wp_pins[] = {
3652         /* WP */
3653         RCAR_GP_PIN(4, 16),
3654 };
3655 static const unsigned int sdhi3_wp_mux[] = {
3656         SD3_WP_MARK,
3657 };
3658 static const unsigned int sdhi3_ds_pins[] = {
3659         /* DS */
3660         RCAR_GP_PIN(4, 17),
3661 };
3662 static const unsigned int sdhi3_ds_mux[] = {
3663         SD3_DS_MARK,
3664 };
3665
3666 /* - SSI -------------------------------------------------------------------- */
3667 static const unsigned int ssi0_data_pins[] = {
3668         /* SDATA */
3669         RCAR_GP_PIN(6, 2),
3670 };
3671 static const unsigned int ssi0_data_mux[] = {
3672         SSI_SDATA0_MARK,
3673 };
3674 static const unsigned int ssi01239_ctrl_pins[] = {
3675         /* SCK, WS */
3676         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3677 };
3678 static const unsigned int ssi01239_ctrl_mux[] = {
3679         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3680 };
3681 static const unsigned int ssi1_data_a_pins[] = {
3682         /* SDATA */
3683         RCAR_GP_PIN(6, 3),
3684 };
3685 static const unsigned int ssi1_data_a_mux[] = {
3686         SSI_SDATA1_A_MARK,
3687 };
3688 static const unsigned int ssi1_data_b_pins[] = {
3689         /* SDATA */
3690         RCAR_GP_PIN(5, 12),
3691 };
3692 static const unsigned int ssi1_data_b_mux[] = {
3693         SSI_SDATA1_B_MARK,
3694 };
3695 static const unsigned int ssi1_ctrl_a_pins[] = {
3696         /* SCK, WS */
3697         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3698 };
3699 static const unsigned int ssi1_ctrl_a_mux[] = {
3700         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3701 };
3702 static const unsigned int ssi1_ctrl_b_pins[] = {
3703         /* SCK, WS */
3704         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3705 };
3706 static const unsigned int ssi1_ctrl_b_mux[] = {
3707         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3708 };
3709 static const unsigned int ssi2_data_a_pins[] = {
3710         /* SDATA */
3711         RCAR_GP_PIN(6, 4),
3712 };
3713 static const unsigned int ssi2_data_a_mux[] = {
3714         SSI_SDATA2_A_MARK,
3715 };
3716 static const unsigned int ssi2_data_b_pins[] = {
3717         /* SDATA */
3718         RCAR_GP_PIN(5, 13),
3719 };
3720 static const unsigned int ssi2_data_b_mux[] = {
3721         SSI_SDATA2_B_MARK,
3722 };
3723 static const unsigned int ssi2_ctrl_a_pins[] = {
3724         /* SCK, WS */
3725         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3726 };
3727 static const unsigned int ssi2_ctrl_a_mux[] = {
3728         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3729 };
3730 static const unsigned int ssi2_ctrl_b_pins[] = {
3731         /* SCK, WS */
3732         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3733 };
3734 static const unsigned int ssi2_ctrl_b_mux[] = {
3735         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3736 };
3737 static const unsigned int ssi3_data_pins[] = {
3738         /* SDATA */
3739         RCAR_GP_PIN(6, 7),
3740 };
3741 static const unsigned int ssi3_data_mux[] = {
3742         SSI_SDATA3_MARK,
3743 };
3744 static const unsigned int ssi349_ctrl_pins[] = {
3745         /* SCK, WS */
3746         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3747 };
3748 static const unsigned int ssi349_ctrl_mux[] = {
3749         SSI_SCK349_MARK, SSI_WS349_MARK,
3750 };
3751 static const unsigned int ssi4_data_pins[] = {
3752         /* SDATA */
3753         RCAR_GP_PIN(6, 10),
3754 };
3755 static const unsigned int ssi4_data_mux[] = {
3756         SSI_SDATA4_MARK,
3757 };
3758 static const unsigned int ssi4_ctrl_pins[] = {
3759         /* SCK, WS */
3760         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3761 };
3762 static const unsigned int ssi4_ctrl_mux[] = {
3763         SSI_SCK4_MARK, SSI_WS4_MARK,
3764 };
3765 static const unsigned int ssi5_data_pins[] = {
3766         /* SDATA */
3767         RCAR_GP_PIN(6, 13),
3768 };
3769 static const unsigned int ssi5_data_mux[] = {
3770         SSI_SDATA5_MARK,
3771 };
3772 static const unsigned int ssi5_ctrl_pins[] = {
3773         /* SCK, WS */
3774         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3775 };
3776 static const unsigned int ssi5_ctrl_mux[] = {
3777         SSI_SCK5_MARK, SSI_WS5_MARK,
3778 };
3779 static const unsigned int ssi6_data_pins[] = {
3780         /* SDATA */
3781         RCAR_GP_PIN(6, 16),
3782 };
3783 static const unsigned int ssi6_data_mux[] = {
3784         SSI_SDATA6_MARK,
3785 };
3786 static const unsigned int ssi6_ctrl_pins[] = {
3787         /* SCK, WS */
3788         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3789 };
3790 static const unsigned int ssi6_ctrl_mux[] = {
3791         SSI_SCK6_MARK, SSI_WS6_MARK,
3792 };
3793 static const unsigned int ssi7_data_pins[] = {
3794         /* SDATA */
3795         RCAR_GP_PIN(6, 19),
3796 };
3797 static const unsigned int ssi7_data_mux[] = {
3798         SSI_SDATA7_MARK,
3799 };
3800 static const unsigned int ssi78_ctrl_pins[] = {
3801         /* SCK, WS */
3802         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3803 };
3804 static const unsigned int ssi78_ctrl_mux[] = {
3805         SSI_SCK78_MARK, SSI_WS78_MARK,
3806 };
3807 static const unsigned int ssi8_data_pins[] = {
3808         /* SDATA */
3809         RCAR_GP_PIN(6, 20),
3810 };
3811 static const unsigned int ssi8_data_mux[] = {
3812         SSI_SDATA8_MARK,
3813 };
3814 static const unsigned int ssi9_data_a_pins[] = {
3815         /* SDATA */
3816         RCAR_GP_PIN(6, 21),
3817 };
3818 static const unsigned int ssi9_data_a_mux[] = {
3819         SSI_SDATA9_A_MARK,
3820 };
3821 static const unsigned int ssi9_data_b_pins[] = {
3822         /* SDATA */
3823         RCAR_GP_PIN(5, 14),
3824 };
3825 static const unsigned int ssi9_data_b_mux[] = {
3826         SSI_SDATA9_B_MARK,
3827 };
3828 static const unsigned int ssi9_ctrl_a_pins[] = {
3829         /* SCK, WS */
3830         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3831 };
3832 static const unsigned int ssi9_ctrl_a_mux[] = {
3833         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3834 };
3835 static const unsigned int ssi9_ctrl_b_pins[] = {
3836         /* SCK, WS */
3837         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3838 };
3839 static const unsigned int ssi9_ctrl_b_mux[] = {
3840         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3841 };
3842
3843 /* - TMU -------------------------------------------------------------------- */
3844 static const unsigned int tmu_tclk1_a_pins[] = {
3845         /* TCLK */
3846         RCAR_GP_PIN(6, 23),
3847 };
3848 static const unsigned int tmu_tclk1_a_mux[] = {
3849         TCLK1_A_MARK,
3850 };
3851 static const unsigned int tmu_tclk1_b_pins[] = {
3852         /* TCLK */
3853         RCAR_GP_PIN(5, 19),
3854 };
3855 static const unsigned int tmu_tclk1_b_mux[] = {
3856         TCLK1_B_MARK,
3857 };
3858 static const unsigned int tmu_tclk2_a_pins[] = {
3859         /* TCLK */
3860         RCAR_GP_PIN(6, 19),
3861 };
3862 static const unsigned int tmu_tclk2_a_mux[] = {
3863         TCLK2_A_MARK,
3864 };
3865 static const unsigned int tmu_tclk2_b_pins[] = {
3866         /* TCLK */
3867         RCAR_GP_PIN(6, 28),
3868 };
3869 static const unsigned int tmu_tclk2_b_mux[] = {
3870         TCLK2_B_MARK,
3871 };
3872
3873 /* - USB0 ------------------------------------------------------------------- */
3874 static const unsigned int usb0_pins[] = {
3875         /* PWEN, OVC */
3876         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3877 };
3878 static const unsigned int usb0_mux[] = {
3879         USB0_PWEN_MARK, USB0_OVC_MARK,
3880 };
3881 /* - USB1 ------------------------------------------------------------------- */
3882 static const unsigned int usb1_pins[] = {
3883         /* PWEN, OVC */
3884         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3885 };
3886 static const unsigned int usb1_mux[] = {
3887         USB1_PWEN_MARK, USB1_OVC_MARK,
3888 };
3889
3890 /* - USB30 ------------------------------------------------------------------ */
3891 static const unsigned int usb30_pins[] = {
3892         /* PWEN, OVC */
3893         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3894 };
3895 static const unsigned int usb30_mux[] = {
3896         USB30_PWEN_MARK, USB30_OVC_MARK,
3897 };
3898
3899 /* - VIN4 ------------------------------------------------------------------- */
3900 static const unsigned int vin4_data18_a_pins[] = {
3901         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3902         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3903         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3904         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3905         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3906         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3907         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3908         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3909         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3910 };
3911 static const unsigned int vin4_data18_a_mux[] = {
3912         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3913         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3914         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3915         VI4_DATA10_MARK, VI4_DATA11_MARK,
3916         VI4_DATA12_MARK, VI4_DATA13_MARK,
3917         VI4_DATA14_MARK, VI4_DATA15_MARK,
3918         VI4_DATA18_MARK, VI4_DATA19_MARK,
3919         VI4_DATA20_MARK, VI4_DATA21_MARK,
3920         VI4_DATA22_MARK, VI4_DATA23_MARK,
3921 };
3922 static const unsigned int vin4_data18_b_pins[] = {
3923         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3924         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3925         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3926         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3927         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3928         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3929         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3930         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3931         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3932 };
3933 static const unsigned int vin4_data18_b_mux[] = {
3934         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3935         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3936         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3937         VI4_DATA10_MARK, VI4_DATA11_MARK,
3938         VI4_DATA12_MARK, VI4_DATA13_MARK,
3939         VI4_DATA14_MARK, VI4_DATA15_MARK,
3940         VI4_DATA18_MARK, VI4_DATA19_MARK,
3941         VI4_DATA20_MARK, VI4_DATA21_MARK,
3942         VI4_DATA22_MARK, VI4_DATA23_MARK,
3943 };
3944 static const union vin_data vin4_data_a_pins = {
3945         .data24 = {
3946                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3947                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3948                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3949                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3950                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3951                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3952                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3953                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3954                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3955                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3956                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3957                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3958         },
3959 };
3960 static const union vin_data vin4_data_a_mux = {
3961         .data24 = {
3962                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3963                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3964                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3965                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3966                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
3967                 VI4_DATA10_MARK, VI4_DATA11_MARK,
3968                 VI4_DATA12_MARK, VI4_DATA13_MARK,
3969                 VI4_DATA14_MARK, VI4_DATA15_MARK,
3970                 VI4_DATA16_MARK, VI4_DATA17_MARK,
3971                 VI4_DATA18_MARK, VI4_DATA19_MARK,
3972                 VI4_DATA20_MARK, VI4_DATA21_MARK,
3973                 VI4_DATA22_MARK, VI4_DATA23_MARK,
3974         },
3975 };
3976 static const union vin_data vin4_data_b_pins = {
3977         .data24 = {
3978                 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3979                 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3980                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3981                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3982                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3983                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3984                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3985                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3986                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3987                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3988                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3989                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3990         },
3991 };
3992 static const union vin_data vin4_data_b_mux = {
3993         .data24 = {
3994                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3995                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3996                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3997                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3998                 VI4_DATA8_MARK,  VI4_DATA9_MARK,
3999                 VI4_DATA10_MARK, VI4_DATA11_MARK,
4000                 VI4_DATA12_MARK, VI4_DATA13_MARK,
4001                 VI4_DATA14_MARK, VI4_DATA15_MARK,
4002                 VI4_DATA16_MARK, VI4_DATA17_MARK,
4003                 VI4_DATA18_MARK, VI4_DATA19_MARK,
4004                 VI4_DATA20_MARK, VI4_DATA21_MARK,
4005                 VI4_DATA22_MARK, VI4_DATA23_MARK,
4006         },
4007 };
4008 static const unsigned int vin4_sync_pins[] = {
4009         /* HSYNC#, VSYNC# */
4010         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4011 };
4012 static const unsigned int vin4_sync_mux[] = {
4013         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4014 };
4015 static const unsigned int vin4_field_pins[] = {
4016         /* FIELD */
4017         RCAR_GP_PIN(1, 16),
4018 };
4019 static const unsigned int vin4_field_mux[] = {
4020         VI4_FIELD_MARK,
4021 };
4022 static const unsigned int vin4_clkenb_pins[] = {
4023         /* CLKENB */
4024         RCAR_GP_PIN(1, 19),
4025 };
4026 static const unsigned int vin4_clkenb_mux[] = {
4027         VI4_CLKENB_MARK,
4028 };
4029 static const unsigned int vin4_clk_pins[] = {
4030         /* CLK */
4031         RCAR_GP_PIN(1, 27),
4032 };
4033 static const unsigned int vin4_clk_mux[] = {
4034         VI4_CLK_MARK,
4035 };
4036
4037 /* - VIN5 ------------------------------------------------------------------- */
4038 static const unsigned int vin5_data8_pins[] = {
4039         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4040         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4041         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4042         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4043 };
4044 static const unsigned int vin5_data8_mux[] = {
4045         VI5_DATA0_MARK, VI5_DATA1_MARK,
4046         VI5_DATA2_MARK, VI5_DATA3_MARK,
4047         VI5_DATA4_MARK, VI5_DATA5_MARK,
4048         VI5_DATA6_MARK, VI5_DATA7_MARK,
4049 };
4050 static const unsigned int vin5_data10_pins[] = {
4051         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4052         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4053         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4054         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4055         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4056 };
4057 static const unsigned int vin5_data10_mux[] = {
4058         VI5_DATA0_MARK, VI5_DATA1_MARK,
4059         VI5_DATA2_MARK, VI5_DATA3_MARK,
4060         VI5_DATA4_MARK, VI5_DATA5_MARK,
4061         VI5_DATA6_MARK, VI5_DATA7_MARK,
4062         VI5_DATA8_MARK,  VI5_DATA9_MARK,
4063 };
4064 static const unsigned int vin5_data12_pins[] = {
4065         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4066         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4067         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4068         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4069         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4070         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4071 };
4072 static const unsigned int vin5_data12_mux[] = {
4073         VI5_DATA0_MARK, VI5_DATA1_MARK,
4074         VI5_DATA2_MARK, VI5_DATA3_MARK,
4075         VI5_DATA4_MARK, VI5_DATA5_MARK,
4076         VI5_DATA6_MARK, VI5_DATA7_MARK,
4077         VI5_DATA8_MARK,  VI5_DATA9_MARK,
4078         VI5_DATA10_MARK, VI5_DATA11_MARK,
4079 };
4080 static const unsigned int vin5_data16_pins[] = {
4081         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4082         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4083         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4084         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4085         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4086         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4087         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4088         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4089 };
4090 static const unsigned int vin5_data16_mux[] = {
4091         VI5_DATA0_MARK, VI5_DATA1_MARK,
4092         VI5_DATA2_MARK, VI5_DATA3_MARK,
4093         VI5_DATA4_MARK, VI5_DATA5_MARK,
4094         VI5_DATA6_MARK, VI5_DATA7_MARK,
4095         VI5_DATA8_MARK,  VI5_DATA9_MARK,
4096         VI5_DATA10_MARK, VI5_DATA11_MARK,
4097         VI5_DATA12_MARK, VI5_DATA13_MARK,
4098         VI5_DATA14_MARK, VI5_DATA15_MARK,
4099 };
4100 static const unsigned int vin5_sync_pins[] = {
4101         /* HSYNC#, VSYNC# */
4102         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4103 };
4104 static const unsigned int vin5_sync_mux[] = {
4105         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4106 };
4107 static const unsigned int vin5_field_pins[] = {
4108         RCAR_GP_PIN(1, 11),
4109 };
4110 static const unsigned int vin5_field_mux[] = {
4111         /* FIELD */
4112         VI5_FIELD_MARK,
4113 };
4114 static const unsigned int vin5_clkenb_pins[] = {
4115         RCAR_GP_PIN(1, 20),
4116 };
4117 static const unsigned int vin5_clkenb_mux[] = {
4118         /* CLKENB */
4119         VI5_CLKENB_MARK,
4120 };
4121 static const unsigned int vin5_clk_pins[] = {
4122         RCAR_GP_PIN(1, 21),
4123 };
4124 static const unsigned int vin5_clk_mux[] = {
4125         /* CLK */
4126         VI5_CLK_MARK,
4127 };
4128
4129 static const struct sh_pfc_pin_group pinmux_groups[] = {
4130         SH_PFC_PIN_GROUP(audio_clk_a_a),
4131         SH_PFC_PIN_GROUP(audio_clk_a_b),
4132         SH_PFC_PIN_GROUP(audio_clk_a_c),
4133         SH_PFC_PIN_GROUP(audio_clk_b_a),
4134         SH_PFC_PIN_GROUP(audio_clk_b_b),
4135         SH_PFC_PIN_GROUP(audio_clk_c_a),
4136         SH_PFC_PIN_GROUP(audio_clk_c_b),
4137         SH_PFC_PIN_GROUP(audio_clkout_a),
4138         SH_PFC_PIN_GROUP(audio_clkout_b),
4139         SH_PFC_PIN_GROUP(audio_clkout_c),
4140         SH_PFC_PIN_GROUP(audio_clkout_d),
4141         SH_PFC_PIN_GROUP(audio_clkout1_a),
4142         SH_PFC_PIN_GROUP(audio_clkout1_b),
4143         SH_PFC_PIN_GROUP(audio_clkout2_a),
4144         SH_PFC_PIN_GROUP(audio_clkout2_b),
4145         SH_PFC_PIN_GROUP(audio_clkout3_a),
4146         SH_PFC_PIN_GROUP(audio_clkout3_b),
4147         SH_PFC_PIN_GROUP(avb_link),
4148         SH_PFC_PIN_GROUP(avb_magic),
4149         SH_PFC_PIN_GROUP(avb_phy_int),
4150         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
4151         SH_PFC_PIN_GROUP(avb_mdio),
4152         SH_PFC_PIN_GROUP(avb_mii),
4153         SH_PFC_PIN_GROUP(avb_avtp_pps),
4154         SH_PFC_PIN_GROUP(avb_avtp_match_a),
4155         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4156         SH_PFC_PIN_GROUP(avb_avtp_match_b),
4157         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4158         SH_PFC_PIN_GROUP(can0_data_a),
4159         SH_PFC_PIN_GROUP(can0_data_b),
4160         SH_PFC_PIN_GROUP(can1_data),
4161         SH_PFC_PIN_GROUP(can_clk),
4162         SH_PFC_PIN_GROUP(canfd0_data_a),
4163         SH_PFC_PIN_GROUP(canfd0_data_b),
4164         SH_PFC_PIN_GROUP(canfd1_data),
4165         SH_PFC_PIN_GROUP(drif0_ctrl_a),
4166         SH_PFC_PIN_GROUP(drif0_data0_a),
4167         SH_PFC_PIN_GROUP(drif0_data1_a),
4168         SH_PFC_PIN_GROUP(drif0_ctrl_b),
4169         SH_PFC_PIN_GROUP(drif0_data0_b),
4170         SH_PFC_PIN_GROUP(drif0_data1_b),
4171         SH_PFC_PIN_GROUP(drif0_ctrl_c),
4172         SH_PFC_PIN_GROUP(drif0_data0_c),
4173         SH_PFC_PIN_GROUP(drif0_data1_c),
4174         SH_PFC_PIN_GROUP(drif1_ctrl_a),
4175         SH_PFC_PIN_GROUP(drif1_data0_a),
4176         SH_PFC_PIN_GROUP(drif1_data1_a),
4177         SH_PFC_PIN_GROUP(drif1_ctrl_b),
4178         SH_PFC_PIN_GROUP(drif1_data0_b),
4179         SH_PFC_PIN_GROUP(drif1_data1_b),
4180         SH_PFC_PIN_GROUP(drif1_ctrl_c),
4181         SH_PFC_PIN_GROUP(drif1_data0_c),
4182         SH_PFC_PIN_GROUP(drif1_data1_c),
4183         SH_PFC_PIN_GROUP(drif2_ctrl_a),
4184         SH_PFC_PIN_GROUP(drif2_data0_a),
4185         SH_PFC_PIN_GROUP(drif2_data1_a),
4186         SH_PFC_PIN_GROUP(drif2_ctrl_b),
4187         SH_PFC_PIN_GROUP(drif2_data0_b),
4188         SH_PFC_PIN_GROUP(drif2_data1_b),
4189         SH_PFC_PIN_GROUP(drif3_ctrl_a),
4190         SH_PFC_PIN_GROUP(drif3_data0_a),
4191         SH_PFC_PIN_GROUP(drif3_data1_a),
4192         SH_PFC_PIN_GROUP(drif3_ctrl_b),
4193         SH_PFC_PIN_GROUP(drif3_data0_b),
4194         SH_PFC_PIN_GROUP(drif3_data1_b),
4195         SH_PFC_PIN_GROUP(du_rgb666),
4196         SH_PFC_PIN_GROUP(du_rgb888),
4197         SH_PFC_PIN_GROUP(du_clk_out_0),
4198         SH_PFC_PIN_GROUP(du_clk_out_1),
4199         SH_PFC_PIN_GROUP(du_sync),
4200         SH_PFC_PIN_GROUP(du_oddf),
4201         SH_PFC_PIN_GROUP(du_cde),
4202         SH_PFC_PIN_GROUP(du_disp),
4203         SH_PFC_PIN_GROUP(hdmi0_cec),
4204         SH_PFC_PIN_GROUP(hscif0_data),
4205         SH_PFC_PIN_GROUP(hscif0_clk),
4206         SH_PFC_PIN_GROUP(hscif0_ctrl),
4207         SH_PFC_PIN_GROUP(hscif1_data_a),
4208         SH_PFC_PIN_GROUP(hscif1_clk_a),
4209         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4210         SH_PFC_PIN_GROUP(hscif1_data_b),
4211         SH_PFC_PIN_GROUP(hscif1_clk_b),
4212         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4213         SH_PFC_PIN_GROUP(hscif2_data_a),
4214         SH_PFC_PIN_GROUP(hscif2_clk_a),
4215         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4216         SH_PFC_PIN_GROUP(hscif2_data_b),
4217         SH_PFC_PIN_GROUP(hscif2_clk_b),
4218         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4219         SH_PFC_PIN_GROUP(hscif2_data_c),
4220         SH_PFC_PIN_GROUP(hscif2_clk_c),
4221         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4222         SH_PFC_PIN_GROUP(hscif3_data_a),
4223         SH_PFC_PIN_GROUP(hscif3_clk),
4224         SH_PFC_PIN_GROUP(hscif3_ctrl),
4225         SH_PFC_PIN_GROUP(hscif3_data_b),
4226         SH_PFC_PIN_GROUP(hscif3_data_c),
4227         SH_PFC_PIN_GROUP(hscif3_data_d),
4228         SH_PFC_PIN_GROUP(hscif4_data_a),
4229         SH_PFC_PIN_GROUP(hscif4_clk),
4230         SH_PFC_PIN_GROUP(hscif4_ctrl),
4231         SH_PFC_PIN_GROUP(hscif4_data_b),
4232         SH_PFC_PIN_GROUP(i2c1_a),
4233         SH_PFC_PIN_GROUP(i2c1_b),
4234         SH_PFC_PIN_GROUP(i2c2_a),
4235         SH_PFC_PIN_GROUP(i2c2_b),
4236         SH_PFC_PIN_GROUP(i2c6_a),
4237         SH_PFC_PIN_GROUP(i2c6_b),
4238         SH_PFC_PIN_GROUP(i2c6_c),
4239         SH_PFC_PIN_GROUP(intc_ex_irq0),
4240         SH_PFC_PIN_GROUP(intc_ex_irq1),
4241         SH_PFC_PIN_GROUP(intc_ex_irq2),
4242         SH_PFC_PIN_GROUP(intc_ex_irq3),
4243         SH_PFC_PIN_GROUP(intc_ex_irq4),
4244         SH_PFC_PIN_GROUP(intc_ex_irq5),
4245         SH_PFC_PIN_GROUP(msiof0_clk),
4246         SH_PFC_PIN_GROUP(msiof0_sync),
4247         SH_PFC_PIN_GROUP(msiof0_ss1),
4248         SH_PFC_PIN_GROUP(msiof0_ss2),
4249         SH_PFC_PIN_GROUP(msiof0_txd),
4250         SH_PFC_PIN_GROUP(msiof0_rxd),
4251         SH_PFC_PIN_GROUP(msiof1_clk_a),
4252         SH_PFC_PIN_GROUP(msiof1_sync_a),
4253         SH_PFC_PIN_GROUP(msiof1_ss1_a),
4254         SH_PFC_PIN_GROUP(msiof1_ss2_a),
4255         SH_PFC_PIN_GROUP(msiof1_txd_a),
4256         SH_PFC_PIN_GROUP(msiof1_rxd_a),
4257         SH_PFC_PIN_GROUP(msiof1_clk_b),
4258         SH_PFC_PIN_GROUP(msiof1_sync_b),
4259         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4260         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4261         SH_PFC_PIN_GROUP(msiof1_txd_b),
4262         SH_PFC_PIN_GROUP(msiof1_rxd_b),
4263         SH_PFC_PIN_GROUP(msiof1_clk_c),
4264         SH_PFC_PIN_GROUP(msiof1_sync_c),
4265         SH_PFC_PIN_GROUP(msiof1_ss1_c),
4266         SH_PFC_PIN_GROUP(msiof1_ss2_c),
4267         SH_PFC_PIN_GROUP(msiof1_txd_c),
4268         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4269         SH_PFC_PIN_GROUP(msiof1_clk_d),
4270         SH_PFC_PIN_GROUP(msiof1_sync_d),
4271         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4272         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4273         SH_PFC_PIN_GROUP(msiof1_txd_d),
4274         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4275         SH_PFC_PIN_GROUP(msiof1_clk_e),
4276         SH_PFC_PIN_GROUP(msiof1_sync_e),
4277         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4278         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4279         SH_PFC_PIN_GROUP(msiof1_txd_e),
4280         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4281         SH_PFC_PIN_GROUP(msiof1_clk_f),
4282         SH_PFC_PIN_GROUP(msiof1_sync_f),
4283         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4284         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4285         SH_PFC_PIN_GROUP(msiof1_txd_f),
4286         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4287         SH_PFC_PIN_GROUP(msiof1_clk_g),
4288         SH_PFC_PIN_GROUP(msiof1_sync_g),
4289         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4290         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4291         SH_PFC_PIN_GROUP(msiof1_txd_g),
4292         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4293         SH_PFC_PIN_GROUP(msiof2_clk_a),
4294         SH_PFC_PIN_GROUP(msiof2_sync_a),
4295         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4296         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4297         SH_PFC_PIN_GROUP(msiof2_txd_a),
4298         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4299         SH_PFC_PIN_GROUP(msiof2_clk_b),
4300         SH_PFC_PIN_GROUP(msiof2_sync_b),
4301         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4302         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4303         SH_PFC_PIN_GROUP(msiof2_txd_b),
4304         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4305         SH_PFC_PIN_GROUP(msiof2_clk_c),
4306         SH_PFC_PIN_GROUP(msiof2_sync_c),
4307         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4308         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4309         SH_PFC_PIN_GROUP(msiof2_txd_c),
4310         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4311         SH_PFC_PIN_GROUP(msiof2_clk_d),
4312         SH_PFC_PIN_GROUP(msiof2_sync_d),
4313         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4314         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4315         SH_PFC_PIN_GROUP(msiof2_txd_d),
4316         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4317         SH_PFC_PIN_GROUP(msiof3_clk_a),
4318         SH_PFC_PIN_GROUP(msiof3_sync_a),
4319         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4320         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4321         SH_PFC_PIN_GROUP(msiof3_txd_a),
4322         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4323         SH_PFC_PIN_GROUP(msiof3_clk_b),
4324         SH_PFC_PIN_GROUP(msiof3_sync_b),
4325         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4326         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4327         SH_PFC_PIN_GROUP(msiof3_txd_b),
4328         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4329         SH_PFC_PIN_GROUP(msiof3_clk_c),
4330         SH_PFC_PIN_GROUP(msiof3_sync_c),
4331         SH_PFC_PIN_GROUP(msiof3_txd_c),
4332         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4333         SH_PFC_PIN_GROUP(msiof3_clk_d),
4334         SH_PFC_PIN_GROUP(msiof3_sync_d),
4335         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4336         SH_PFC_PIN_GROUP(msiof3_txd_d),
4337         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4338         SH_PFC_PIN_GROUP(msiof3_clk_e),
4339         SH_PFC_PIN_GROUP(msiof3_sync_e),
4340         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4341         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4342         SH_PFC_PIN_GROUP(msiof3_txd_e),
4343         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4344         SH_PFC_PIN_GROUP(pwm0),
4345         SH_PFC_PIN_GROUP(pwm1_a),
4346         SH_PFC_PIN_GROUP(pwm1_b),
4347         SH_PFC_PIN_GROUP(pwm2_a),
4348         SH_PFC_PIN_GROUP(pwm2_b),
4349         SH_PFC_PIN_GROUP(pwm3_a),
4350         SH_PFC_PIN_GROUP(pwm3_b),
4351         SH_PFC_PIN_GROUP(pwm4_a),
4352         SH_PFC_PIN_GROUP(pwm4_b),
4353         SH_PFC_PIN_GROUP(pwm5_a),
4354         SH_PFC_PIN_GROUP(pwm5_b),
4355         SH_PFC_PIN_GROUP(pwm6_a),
4356         SH_PFC_PIN_GROUP(pwm6_b),
4357         SH_PFC_PIN_GROUP(scif0_data),
4358         SH_PFC_PIN_GROUP(scif0_clk),
4359         SH_PFC_PIN_GROUP(scif0_ctrl),
4360         SH_PFC_PIN_GROUP(scif1_data_a),
4361         SH_PFC_PIN_GROUP(scif1_clk),
4362         SH_PFC_PIN_GROUP(scif1_ctrl),
4363         SH_PFC_PIN_GROUP(scif1_data_b),
4364         SH_PFC_PIN_GROUP(scif2_data_a),
4365         SH_PFC_PIN_GROUP(scif2_clk),
4366         SH_PFC_PIN_GROUP(scif2_data_b),
4367         SH_PFC_PIN_GROUP(scif3_data_a),
4368         SH_PFC_PIN_GROUP(scif3_clk),
4369         SH_PFC_PIN_GROUP(scif3_ctrl),
4370         SH_PFC_PIN_GROUP(scif3_data_b),
4371         SH_PFC_PIN_GROUP(scif4_data_a),
4372         SH_PFC_PIN_GROUP(scif4_clk_a),
4373         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4374         SH_PFC_PIN_GROUP(scif4_data_b),
4375         SH_PFC_PIN_GROUP(scif4_clk_b),
4376         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4377         SH_PFC_PIN_GROUP(scif4_data_c),
4378         SH_PFC_PIN_GROUP(scif4_clk_c),
4379         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4380         SH_PFC_PIN_GROUP(scif5_data_a),
4381         SH_PFC_PIN_GROUP(scif5_clk_a),
4382         SH_PFC_PIN_GROUP(scif5_data_b),
4383         SH_PFC_PIN_GROUP(scif5_clk_b),
4384         SH_PFC_PIN_GROUP(scif_clk_a),
4385         SH_PFC_PIN_GROUP(scif_clk_b),
4386         SH_PFC_PIN_GROUP(sdhi0_data1),
4387         SH_PFC_PIN_GROUP(sdhi0_data4),
4388         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4389         SH_PFC_PIN_GROUP(sdhi0_cd),
4390         SH_PFC_PIN_GROUP(sdhi0_wp),
4391         SH_PFC_PIN_GROUP(sdhi1_data1),
4392         SH_PFC_PIN_GROUP(sdhi1_data4),
4393         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4394         SH_PFC_PIN_GROUP(sdhi1_cd),
4395         SH_PFC_PIN_GROUP(sdhi1_wp),
4396         SH_PFC_PIN_GROUP(sdhi2_data1),
4397         SH_PFC_PIN_GROUP(sdhi2_data4),
4398         SH_PFC_PIN_GROUP(sdhi2_data8),
4399         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4400         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4401         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4402         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4403         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4404         SH_PFC_PIN_GROUP(sdhi2_ds),
4405         SH_PFC_PIN_GROUP(sdhi3_data1),
4406         SH_PFC_PIN_GROUP(sdhi3_data4),
4407         SH_PFC_PIN_GROUP(sdhi3_data8),
4408         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4409         SH_PFC_PIN_GROUP(sdhi3_cd),
4410         SH_PFC_PIN_GROUP(sdhi3_wp),
4411         SH_PFC_PIN_GROUP(sdhi3_ds),
4412         SH_PFC_PIN_GROUP(ssi0_data),
4413         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4414         SH_PFC_PIN_GROUP(ssi1_data_a),
4415         SH_PFC_PIN_GROUP(ssi1_data_b),
4416         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4417         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4418         SH_PFC_PIN_GROUP(ssi2_data_a),
4419         SH_PFC_PIN_GROUP(ssi2_data_b),
4420         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4421         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4422         SH_PFC_PIN_GROUP(ssi3_data),
4423         SH_PFC_PIN_GROUP(ssi349_ctrl),
4424         SH_PFC_PIN_GROUP(ssi4_data),
4425         SH_PFC_PIN_GROUP(ssi4_ctrl),
4426         SH_PFC_PIN_GROUP(ssi5_data),
4427         SH_PFC_PIN_GROUP(ssi5_ctrl),
4428         SH_PFC_PIN_GROUP(ssi6_data),
4429         SH_PFC_PIN_GROUP(ssi6_ctrl),
4430         SH_PFC_PIN_GROUP(ssi7_data),
4431         SH_PFC_PIN_GROUP(ssi78_ctrl),
4432         SH_PFC_PIN_GROUP(ssi8_data),
4433         SH_PFC_PIN_GROUP(ssi9_data_a),
4434         SH_PFC_PIN_GROUP(ssi9_data_b),
4435         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4436         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4437         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4438         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4439         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4440         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4441         SH_PFC_PIN_GROUP(usb0),
4442         SH_PFC_PIN_GROUP(usb1),
4443         SH_PFC_PIN_GROUP(usb30),
4444         VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4445         VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4446         VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4447         VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4448         SH_PFC_PIN_GROUP(vin4_data18_a),
4449         VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4450         VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4451         VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4452         VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4453         VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4454         VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4455         SH_PFC_PIN_GROUP(vin4_data18_b),
4456         VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4457         VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4458         SH_PFC_PIN_GROUP(vin4_sync),
4459         SH_PFC_PIN_GROUP(vin4_field),
4460         SH_PFC_PIN_GROUP(vin4_clkenb),
4461         SH_PFC_PIN_GROUP(vin4_clk),
4462         SH_PFC_PIN_GROUP(vin5_data8),
4463         SH_PFC_PIN_GROUP(vin5_data10),
4464         SH_PFC_PIN_GROUP(vin5_data12),
4465         SH_PFC_PIN_GROUP(vin5_data16),
4466         SH_PFC_PIN_GROUP(vin5_sync),
4467         SH_PFC_PIN_GROUP(vin5_field),
4468         SH_PFC_PIN_GROUP(vin5_clkenb),
4469         SH_PFC_PIN_GROUP(vin5_clk),
4470 };
4471
4472 static const char * const audio_clk_groups[] = {
4473         "audio_clk_a_a",
4474         "audio_clk_a_b",
4475         "audio_clk_a_c",
4476         "audio_clk_b_a",
4477         "audio_clk_b_b",
4478         "audio_clk_c_a",
4479         "audio_clk_c_b",
4480         "audio_clkout_a",
4481         "audio_clkout_b",
4482         "audio_clkout_c",
4483         "audio_clkout_d",
4484         "audio_clkout1_a",
4485         "audio_clkout1_b",
4486         "audio_clkout2_a",
4487         "audio_clkout2_b",
4488         "audio_clkout3_a",
4489         "audio_clkout3_b",
4490 };
4491
4492 static const char * const avb_groups[] = {
4493         "avb_link",
4494         "avb_magic",
4495         "avb_phy_int",
4496         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4497         "avb_mdio",
4498         "avb_mii",
4499         "avb_avtp_pps",
4500         "avb_avtp_match_a",
4501         "avb_avtp_capture_a",
4502         "avb_avtp_match_b",
4503         "avb_avtp_capture_b",
4504 };
4505
4506 static const char * const can0_groups[] = {
4507         "can0_data_a",
4508         "can0_data_b",
4509 };
4510
4511 static const char * const can1_groups[] = {
4512         "can1_data",
4513 };
4514
4515 static const char * const can_clk_groups[] = {
4516         "can_clk",
4517 };
4518
4519 static const char * const canfd0_groups[] = {
4520         "canfd0_data_a",
4521         "canfd0_data_b",
4522 };
4523
4524 static const char * const canfd1_groups[] = {
4525         "canfd1_data",
4526 };
4527
4528 static const char * const drif0_groups[] = {
4529         "drif0_ctrl_a",
4530         "drif0_data0_a",
4531         "drif0_data1_a",
4532         "drif0_ctrl_b",
4533         "drif0_data0_b",
4534         "drif0_data1_b",
4535         "drif0_ctrl_c",
4536         "drif0_data0_c",
4537         "drif0_data1_c",
4538 };
4539
4540 static const char * const drif1_groups[] = {
4541         "drif1_ctrl_a",
4542         "drif1_data0_a",
4543         "drif1_data1_a",
4544         "drif1_ctrl_b",
4545         "drif1_data0_b",
4546         "drif1_data1_b",
4547         "drif1_ctrl_c",
4548         "drif1_data0_c",
4549         "drif1_data1_c",
4550 };
4551
4552 static const char * const drif2_groups[] = {
4553         "drif2_ctrl_a",
4554         "drif2_data0_a",
4555         "drif2_data1_a",
4556         "drif2_ctrl_b",
4557         "drif2_data0_b",
4558         "drif2_data1_b",
4559 };
4560
4561 static const char * const drif3_groups[] = {
4562         "drif3_ctrl_a",
4563         "drif3_data0_a",
4564         "drif3_data1_a",
4565         "drif3_ctrl_b",
4566         "drif3_data0_b",
4567         "drif3_data1_b",
4568 };
4569
4570 static const char * const du_groups[] = {
4571         "du_rgb666",
4572         "du_rgb888",
4573         "du_clk_out_0",
4574         "du_clk_out_1",
4575         "du_sync",
4576         "du_oddf",
4577         "du_cde",
4578         "du_disp",
4579 };
4580
4581 static const char * const hdmi0_groups[] = {
4582         "hdmi0_cec",
4583 };
4584
4585 static const char * const hscif0_groups[] = {
4586         "hscif0_data",
4587         "hscif0_clk",
4588         "hscif0_ctrl",
4589 };
4590
4591 static const char * const hscif1_groups[] = {
4592         "hscif1_data_a",
4593         "hscif1_clk_a",
4594         "hscif1_ctrl_a",
4595         "hscif1_data_b",
4596         "hscif1_clk_b",
4597         "hscif1_ctrl_b",
4598 };
4599
4600 static const char * const hscif2_groups[] = {
4601         "hscif2_data_a",
4602         "hscif2_clk_a",
4603         "hscif2_ctrl_a",
4604         "hscif2_data_b",
4605         "hscif2_clk_b",
4606         "hscif2_ctrl_b",
4607         "hscif2_data_c",
4608         "hscif2_clk_c",
4609         "hscif2_ctrl_c",
4610 };
4611
4612 static const char * const hscif3_groups[] = {
4613         "hscif3_data_a",
4614         "hscif3_clk",
4615         "hscif3_ctrl",
4616         "hscif3_data_b",
4617         "hscif3_data_c",
4618         "hscif3_data_d",
4619 };
4620
4621 static const char * const hscif4_groups[] = {
4622         "hscif4_data_a",
4623         "hscif4_clk",
4624         "hscif4_ctrl",
4625         "hscif4_data_b",
4626 };
4627
4628 static const char * const i2c1_groups[] = {
4629         "i2c1_a",
4630         "i2c1_b",
4631 };
4632
4633 static const char * const i2c2_groups[] = {
4634         "i2c2_a",
4635         "i2c2_b",
4636 };
4637
4638 static const char * const i2c6_groups[] = {
4639         "i2c6_a",
4640         "i2c6_b",
4641         "i2c6_c",
4642 };
4643
4644 static const char * const intc_ex_groups[] = {
4645         "intc_ex_irq0",
4646         "intc_ex_irq1",
4647         "intc_ex_irq2",
4648         "intc_ex_irq3",
4649         "intc_ex_irq4",
4650         "intc_ex_irq5",
4651 };
4652
4653 static const char * const msiof0_groups[] = {
4654         "msiof0_clk",
4655         "msiof0_sync",
4656         "msiof0_ss1",
4657         "msiof0_ss2",
4658         "msiof0_txd",
4659         "msiof0_rxd",
4660 };
4661
4662 static const char * const msiof1_groups[] = {
4663         "msiof1_clk_a",
4664         "msiof1_sync_a",
4665         "msiof1_ss1_a",
4666         "msiof1_ss2_a",
4667         "msiof1_txd_a",
4668         "msiof1_rxd_a",
4669         "msiof1_clk_b",
4670         "msiof1_sync_b",
4671         "msiof1_ss1_b",
4672         "msiof1_ss2_b",
4673         "msiof1_txd_b",
4674         "msiof1_rxd_b",
4675         "msiof1_clk_c",
4676         "msiof1_sync_c",
4677         "msiof1_ss1_c",
4678         "msiof1_ss2_c",
4679         "msiof1_txd_c",
4680         "msiof1_rxd_c",
4681         "msiof1_clk_d",
4682         "msiof1_sync_d",
4683         "msiof1_ss1_d",
4684         "msiof1_ss2_d",
4685         "msiof1_txd_d",
4686         "msiof1_rxd_d",
4687         "msiof1_clk_e",
4688         "msiof1_sync_e",
4689         "msiof1_ss1_e",
4690         "msiof1_ss2_e",
4691         "msiof1_txd_e",
4692         "msiof1_rxd_e",
4693         "msiof1_clk_f",
4694         "msiof1_sync_f",
4695         "msiof1_ss1_f",
4696         "msiof1_ss2_f",
4697         "msiof1_txd_f",
4698         "msiof1_rxd_f",
4699         "msiof1_clk_g",
4700         "msiof1_sync_g",
4701         "msiof1_ss1_g",
4702         "msiof1_ss2_g",
4703         "msiof1_txd_g",
4704         "msiof1_rxd_g",
4705 };
4706
4707 static const char * const msiof2_groups[] = {
4708         "msiof2_clk_a",
4709         "msiof2_sync_a",
4710         "msiof2_ss1_a",
4711         "msiof2_ss2_a",
4712         "msiof2_txd_a",
4713         "msiof2_rxd_a",
4714         "msiof2_clk_b",
4715         "msiof2_sync_b",
4716         "msiof2_ss1_b",
4717         "msiof2_ss2_b",
4718         "msiof2_txd_b",
4719         "msiof2_rxd_b",
4720         "msiof2_clk_c",
4721         "msiof2_sync_c",
4722         "msiof2_ss1_c",
4723         "msiof2_ss2_c",
4724         "msiof2_txd_c",
4725         "msiof2_rxd_c",
4726         "msiof2_clk_d",
4727         "msiof2_sync_d",
4728         "msiof2_ss1_d",
4729         "msiof2_ss2_d",
4730         "msiof2_txd_d",
4731         "msiof2_rxd_d",
4732 };
4733
4734 static const char * const msiof3_groups[] = {
4735         "msiof3_clk_a",
4736         "msiof3_sync_a",
4737         "msiof3_ss1_a",
4738         "msiof3_ss2_a",
4739         "msiof3_txd_a",
4740         "msiof3_rxd_a",
4741         "msiof3_clk_b",
4742         "msiof3_sync_b",
4743         "msiof3_ss1_b",
4744         "msiof3_ss2_b",
4745         "msiof3_txd_b",
4746         "msiof3_rxd_b",
4747         "msiof3_clk_c",
4748         "msiof3_sync_c",
4749         "msiof3_txd_c",
4750         "msiof3_rxd_c",
4751         "msiof3_clk_d",
4752         "msiof3_sync_d",
4753         "msiof3_ss1_d",
4754         "msiof3_txd_d",
4755         "msiof3_rxd_d",
4756         "msiof3_clk_e",
4757         "msiof3_sync_e",
4758         "msiof3_ss1_e",
4759         "msiof3_ss2_e",
4760         "msiof3_txd_e",
4761         "msiof3_rxd_e",
4762 };
4763
4764 static const char * const pwm0_groups[] = {
4765         "pwm0",
4766 };
4767
4768 static const char * const pwm1_groups[] = {
4769         "pwm1_a",
4770         "pwm1_b",
4771 };
4772
4773 static const char * const pwm2_groups[] = {
4774         "pwm2_a",
4775         "pwm2_b",
4776 };
4777
4778 static const char * const pwm3_groups[] = {
4779         "pwm3_a",
4780         "pwm3_b",
4781 };
4782
4783 static const char * const pwm4_groups[] = {
4784         "pwm4_a",
4785         "pwm4_b",
4786 };
4787
4788 static const char * const pwm5_groups[] = {
4789         "pwm5_a",
4790         "pwm5_b",
4791 };
4792
4793 static const char * const pwm6_groups[] = {
4794         "pwm6_a",
4795         "pwm6_b",
4796 };
4797
4798 static const char * const scif0_groups[] = {
4799         "scif0_data",
4800         "scif0_clk",
4801         "scif0_ctrl",
4802 };
4803
4804 static const char * const scif1_groups[] = {
4805         "scif1_data_a",
4806         "scif1_clk",
4807         "scif1_ctrl",
4808         "scif1_data_b",
4809 };
4810
4811 static const char * const scif2_groups[] = {
4812         "scif2_data_a",
4813         "scif2_clk",
4814         "scif2_data_b",
4815 };
4816
4817 static const char * const scif3_groups[] = {
4818         "scif3_data_a",
4819         "scif3_clk",
4820         "scif3_ctrl",
4821         "scif3_data_b",
4822 };
4823
4824 static const char * const scif4_groups[] = {
4825         "scif4_data_a",
4826         "scif4_clk_a",
4827         "scif4_ctrl_a",
4828         "scif4_data_b",
4829         "scif4_clk_b",
4830         "scif4_ctrl_b",
4831         "scif4_data_c",
4832         "scif4_clk_c",
4833         "scif4_ctrl_c",
4834 };
4835
4836 static const char * const scif5_groups[] = {
4837         "scif5_data_a",
4838         "scif5_clk_a",
4839         "scif5_data_b",
4840         "scif5_clk_b",
4841 };
4842
4843 static const char * const scif_clk_groups[] = {
4844         "scif_clk_a",
4845         "scif_clk_b",
4846 };
4847
4848 static const char * const sdhi0_groups[] = {
4849         "sdhi0_data1",
4850         "sdhi0_data4",
4851         "sdhi0_ctrl",
4852         "sdhi0_cd",
4853         "sdhi0_wp",
4854 };
4855
4856 static const char * const sdhi1_groups[] = {
4857         "sdhi1_data1",
4858         "sdhi1_data4",
4859         "sdhi1_ctrl",
4860         "sdhi1_cd",
4861         "sdhi1_wp",
4862 };
4863
4864 static const char * const sdhi2_groups[] = {
4865         "sdhi2_data1",
4866         "sdhi2_data4",
4867         "sdhi2_data8",
4868         "sdhi2_ctrl",
4869         "sdhi2_cd_a",
4870         "sdhi2_wp_a",
4871         "sdhi2_cd_b",
4872         "sdhi2_wp_b",
4873         "sdhi2_ds",
4874 };
4875
4876 static const char * const sdhi3_groups[] = {
4877         "sdhi3_data1",
4878         "sdhi3_data4",
4879         "sdhi3_data8",
4880         "sdhi3_ctrl",
4881         "sdhi3_cd",
4882         "sdhi3_wp",
4883         "sdhi3_ds",
4884 };
4885
4886 static const char * const ssi_groups[] = {
4887         "ssi0_data",
4888         "ssi01239_ctrl",
4889         "ssi1_data_a",
4890         "ssi1_data_b",
4891         "ssi1_ctrl_a",
4892         "ssi1_ctrl_b",
4893         "ssi2_data_a",
4894         "ssi2_data_b",
4895         "ssi2_ctrl_a",
4896         "ssi2_ctrl_b",
4897         "ssi3_data",
4898         "ssi349_ctrl",
4899         "ssi4_data",
4900         "ssi4_ctrl",
4901         "ssi5_data",
4902         "ssi5_ctrl",
4903         "ssi6_data",
4904         "ssi6_ctrl",
4905         "ssi7_data",
4906         "ssi78_ctrl",
4907         "ssi8_data",
4908         "ssi9_data_a",
4909         "ssi9_data_b",
4910         "ssi9_ctrl_a",
4911         "ssi9_ctrl_b",
4912 };
4913
4914 static const char * const tmu_groups[] = {
4915         "tmu_tclk1_a",
4916         "tmu_tclk1_b",
4917         "tmu_tclk2_a",
4918         "tmu_tclk2_b",
4919 };
4920
4921 static const char * const usb0_groups[] = {
4922         "usb0",
4923 };
4924
4925 static const char * const usb1_groups[] = {
4926         "usb1",
4927 };
4928
4929 static const char * const usb30_groups[] = {
4930         "usb30",
4931 };
4932
4933 static const char * const vin4_groups[] = {
4934         "vin4_data8_a",
4935         "vin4_data10_a",
4936         "vin4_data12_a",
4937         "vin4_data16_a",
4938         "vin4_data18_a",
4939         "vin4_data20_a",
4940         "vin4_data24_a",
4941         "vin4_data8_b",
4942         "vin4_data10_b",
4943         "vin4_data12_b",
4944         "vin4_data16_b",
4945         "vin4_data18_b",
4946         "vin4_data20_b",
4947         "vin4_data24_b",
4948         "vin4_sync",
4949         "vin4_field",
4950         "vin4_clkenb",
4951         "vin4_clk",
4952 };
4953
4954 static const char * const vin5_groups[] = {
4955         "vin5_data8",
4956         "vin5_data10",
4957         "vin5_data12",
4958         "vin5_data16",
4959         "vin5_sync",
4960         "vin5_field",
4961         "vin5_clkenb",
4962         "vin5_clk",
4963 };
4964
4965 static const struct sh_pfc_function pinmux_functions[] = {
4966         SH_PFC_FUNCTION(audio_clk),
4967         SH_PFC_FUNCTION(avb),
4968         SH_PFC_FUNCTION(can0),
4969         SH_PFC_FUNCTION(can1),
4970         SH_PFC_FUNCTION(can_clk),
4971         SH_PFC_FUNCTION(canfd0),
4972         SH_PFC_FUNCTION(canfd1),
4973         SH_PFC_FUNCTION(drif0),
4974         SH_PFC_FUNCTION(drif1),
4975         SH_PFC_FUNCTION(drif2),
4976         SH_PFC_FUNCTION(drif3),
4977         SH_PFC_FUNCTION(du),
4978         SH_PFC_FUNCTION(hdmi0),
4979         SH_PFC_FUNCTION(hscif0),
4980         SH_PFC_FUNCTION(hscif1),
4981         SH_PFC_FUNCTION(hscif2),
4982         SH_PFC_FUNCTION(hscif3),
4983         SH_PFC_FUNCTION(hscif4),
4984         SH_PFC_FUNCTION(i2c1),
4985         SH_PFC_FUNCTION(i2c2),
4986         SH_PFC_FUNCTION(i2c6),
4987         SH_PFC_FUNCTION(intc_ex),
4988         SH_PFC_FUNCTION(msiof0),
4989         SH_PFC_FUNCTION(msiof1),
4990         SH_PFC_FUNCTION(msiof2),
4991         SH_PFC_FUNCTION(msiof3),
4992         SH_PFC_FUNCTION(pwm0),
4993         SH_PFC_FUNCTION(pwm1),
4994         SH_PFC_FUNCTION(pwm2),
4995         SH_PFC_FUNCTION(pwm3),
4996         SH_PFC_FUNCTION(pwm4),
4997         SH_PFC_FUNCTION(pwm5),
4998         SH_PFC_FUNCTION(pwm6),
4999         SH_PFC_FUNCTION(scif0),
5000         SH_PFC_FUNCTION(scif1),
5001         SH_PFC_FUNCTION(scif2),
5002         SH_PFC_FUNCTION(scif3),
5003         SH_PFC_FUNCTION(scif4),
5004         SH_PFC_FUNCTION(scif5),
5005         SH_PFC_FUNCTION(scif_clk),
5006         SH_PFC_FUNCTION(sdhi0),
5007         SH_PFC_FUNCTION(sdhi1),
5008         SH_PFC_FUNCTION(sdhi2),
5009         SH_PFC_FUNCTION(sdhi3),
5010         SH_PFC_FUNCTION(ssi),
5011         SH_PFC_FUNCTION(tmu),
5012         SH_PFC_FUNCTION(usb0),
5013         SH_PFC_FUNCTION(usb1),
5014         SH_PFC_FUNCTION(usb30),
5015         SH_PFC_FUNCTION(vin4),
5016         SH_PFC_FUNCTION(vin5),
5017 };
5018
5019 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5020 #define F_(x, y)        FN_##y
5021 #define FM(x)           FN_##x
5022         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5023                 0, 0,
5024                 0, 0,
5025                 0, 0,
5026                 0, 0,
5027                 0, 0,
5028                 0, 0,
5029                 0, 0,
5030                 0, 0,
5031                 0, 0,
5032                 0, 0,
5033                 0, 0,
5034                 0, 0,
5035                 0, 0,
5036                 0, 0,
5037                 0, 0,
5038                 0, 0,
5039                 GP_0_15_FN,     GPSR0_15,
5040                 GP_0_14_FN,     GPSR0_14,
5041                 GP_0_13_FN,     GPSR0_13,
5042                 GP_0_12_FN,     GPSR0_12,
5043                 GP_0_11_FN,     GPSR0_11,
5044                 GP_0_10_FN,     GPSR0_10,
5045                 GP_0_9_FN,      GPSR0_9,
5046                 GP_0_8_FN,      GPSR0_8,
5047                 GP_0_7_FN,      GPSR0_7,
5048                 GP_0_6_FN,      GPSR0_6,
5049                 GP_0_5_FN,      GPSR0_5,
5050                 GP_0_4_FN,      GPSR0_4,
5051                 GP_0_3_FN,      GPSR0_3,
5052                 GP_0_2_FN,      GPSR0_2,
5053                 GP_0_1_FN,      GPSR0_1,
5054                 GP_0_0_FN,      GPSR0_0, }
5055         },
5056         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5057                 0, 0,
5058                 0, 0,
5059                 0, 0,
5060                 GP_1_28_FN,     GPSR1_28,
5061                 GP_1_27_FN,     GPSR1_27,
5062                 GP_1_26_FN,     GPSR1_26,
5063                 GP_1_25_FN,     GPSR1_25,
5064                 GP_1_24_FN,     GPSR1_24,
5065                 GP_1_23_FN,     GPSR1_23,
5066                 GP_1_22_FN,     GPSR1_22,
5067                 GP_1_21_FN,     GPSR1_21,
5068                 GP_1_20_FN,     GPSR1_20,
5069                 GP_1_19_FN,     GPSR1_19,
5070                 GP_1_18_FN,     GPSR1_18,
5071                 GP_1_17_FN,     GPSR1_17,
5072                 GP_1_16_FN,     GPSR1_16,
5073                 GP_1_15_FN,     GPSR1_15,
5074                 GP_1_14_FN,     GPSR1_14,
5075                 GP_1_13_FN,     GPSR1_13,
5076                 GP_1_12_FN,     GPSR1_12,
5077                 GP_1_11_FN,     GPSR1_11,
5078                 GP_1_10_FN,     GPSR1_10,
5079                 GP_1_9_FN,      GPSR1_9,
5080                 GP_1_8_FN,      GPSR1_8,
5081                 GP_1_7_FN,      GPSR1_7,
5082                 GP_1_6_FN,      GPSR1_6,
5083                 GP_1_5_FN,      GPSR1_5,
5084                 GP_1_4_FN,      GPSR1_4,
5085                 GP_1_3_FN,      GPSR1_3,
5086                 GP_1_2_FN,      GPSR1_2,
5087                 GP_1_1_FN,      GPSR1_1,
5088                 GP_1_0_FN,      GPSR1_0, }
5089         },
5090         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5091                 0, 0,
5092                 0, 0,
5093                 0, 0,
5094                 0, 0,
5095                 0, 0,
5096                 0, 0,
5097                 0, 0,
5098                 0, 0,
5099                 0, 0,
5100                 0, 0,
5101                 0, 0,
5102                 0, 0,
5103                 0, 0,
5104                 0, 0,
5105                 0, 0,
5106                 0, 0,
5107                 0, 0,
5108                 GP_2_14_FN,     GPSR2_14,
5109                 GP_2_13_FN,     GPSR2_13,
5110                 GP_2_12_FN,     GPSR2_12,
5111                 GP_2_11_FN,     GPSR2_11,
5112                 GP_2_10_FN,     GPSR2_10,
5113                 GP_2_9_FN,      GPSR2_9,
5114                 GP_2_8_FN,      GPSR2_8,
5115                 GP_2_7_FN,      GPSR2_7,
5116                 GP_2_6_FN,      GPSR2_6,
5117                 GP_2_5_FN,      GPSR2_5,
5118                 GP_2_4_FN,      GPSR2_4,
5119                 GP_2_3_FN,      GPSR2_3,
5120                 GP_2_2_FN,      GPSR2_2,
5121                 GP_2_1_FN,      GPSR2_1,
5122                 GP_2_0_FN,      GPSR2_0, }
5123         },
5124         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5125                 0, 0,
5126                 0, 0,
5127                 0, 0,
5128                 0, 0,
5129                 0, 0,
5130                 0, 0,
5131                 0, 0,
5132                 0, 0,
5133                 0, 0,
5134                 0, 0,
5135                 0, 0,
5136                 0, 0,
5137                 0, 0,
5138                 0, 0,
5139                 0, 0,
5140                 0, 0,
5141                 GP_3_15_FN,     GPSR3_15,
5142                 GP_3_14_FN,     GPSR3_14,
5143                 GP_3_13_FN,     GPSR3_13,
5144                 GP_3_12_FN,     GPSR3_12,
5145                 GP_3_11_FN,     GPSR3_11,
5146                 GP_3_10_FN,     GPSR3_10,
5147                 GP_3_9_FN,      GPSR3_9,
5148                 GP_3_8_FN,      GPSR3_8,
5149                 GP_3_7_FN,      GPSR3_7,
5150                 GP_3_6_FN,      GPSR3_6,
5151                 GP_3_5_FN,      GPSR3_5,
5152                 GP_3_4_FN,      GPSR3_4,
5153                 GP_3_3_FN,      GPSR3_3,
5154                 GP_3_2_FN,      GPSR3_2,
5155                 GP_3_1_FN,      GPSR3_1,
5156                 GP_3_0_FN,      GPSR3_0, }
5157         },
5158         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5159                 0, 0,
5160                 0, 0,
5161                 0, 0,
5162                 0, 0,
5163                 0, 0,
5164                 0, 0,
5165                 0, 0,
5166                 0, 0,
5167                 0, 0,
5168                 0, 0,
5169                 0, 0,
5170                 0, 0,
5171                 0, 0,
5172                 0, 0,
5173                 GP_4_17_FN,     GPSR4_17,
5174                 GP_4_16_FN,     GPSR4_16,
5175                 GP_4_15_FN,     GPSR4_15,
5176                 GP_4_14_FN,     GPSR4_14,
5177                 GP_4_13_FN,     GPSR4_13,
5178                 GP_4_12_FN,     GPSR4_12,
5179                 GP_4_11_FN,     GPSR4_11,
5180                 GP_4_10_FN,     GPSR4_10,
5181                 GP_4_9_FN,      GPSR4_9,
5182                 GP_4_8_FN,      GPSR4_8,
5183                 GP_4_7_FN,      GPSR4_7,
5184                 GP_4_6_FN,      GPSR4_6,
5185                 GP_4_5_FN,      GPSR4_5,
5186                 GP_4_4_FN,      GPSR4_4,
5187                 GP_4_3_FN,      GPSR4_3,
5188                 GP_4_2_FN,      GPSR4_2,
5189                 GP_4_1_FN,      GPSR4_1,
5190                 GP_4_0_FN,      GPSR4_0, }
5191         },
5192         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5193                 0, 0,
5194                 0, 0,
5195                 0, 0,
5196                 0, 0,
5197                 0, 0,
5198                 0, 0,
5199                 GP_5_25_FN,     GPSR5_25,
5200                 GP_5_24_FN,     GPSR5_24,
5201                 GP_5_23_FN,     GPSR5_23,
5202                 GP_5_22_FN,     GPSR5_22,
5203                 GP_5_21_FN,     GPSR5_21,
5204                 GP_5_20_FN,     GPSR5_20,
5205                 GP_5_19_FN,     GPSR5_19,
5206                 GP_5_18_FN,     GPSR5_18,
5207                 GP_5_17_FN,     GPSR5_17,
5208                 GP_5_16_FN,     GPSR5_16,
5209                 GP_5_15_FN,     GPSR5_15,
5210                 GP_5_14_FN,     GPSR5_14,
5211                 GP_5_13_FN,     GPSR5_13,
5212                 GP_5_12_FN,     GPSR5_12,
5213                 GP_5_11_FN,     GPSR5_11,
5214                 GP_5_10_FN,     GPSR5_10,
5215                 GP_5_9_FN,      GPSR5_9,
5216                 GP_5_8_FN,      GPSR5_8,
5217                 GP_5_7_FN,      GPSR5_7,
5218                 GP_5_6_FN,      GPSR5_6,
5219                 GP_5_5_FN,      GPSR5_5,
5220                 GP_5_4_FN,      GPSR5_4,
5221                 GP_5_3_FN,      GPSR5_3,
5222                 GP_5_2_FN,      GPSR5_2,
5223                 GP_5_1_FN,      GPSR5_1,
5224                 GP_5_0_FN,      GPSR5_0, }
5225         },
5226         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5227                 GP_6_31_FN,     GPSR6_31,
5228                 GP_6_30_FN,     GPSR6_30,
5229                 GP_6_29_FN,     GPSR6_29,
5230                 GP_6_28_FN,     GPSR6_28,
5231                 GP_6_27_FN,     GPSR6_27,
5232                 GP_6_26_FN,     GPSR6_26,
5233                 GP_6_25_FN,     GPSR6_25,
5234                 GP_6_24_FN,     GPSR6_24,
5235                 GP_6_23_FN,     GPSR6_23,
5236                 GP_6_22_FN,     GPSR6_22,
5237                 GP_6_21_FN,     GPSR6_21,
5238                 GP_6_20_FN,     GPSR6_20,
5239                 GP_6_19_FN,     GPSR6_19,
5240                 GP_6_18_FN,     GPSR6_18,
5241                 GP_6_17_FN,     GPSR6_17,
5242                 GP_6_16_FN,     GPSR6_16,
5243                 GP_6_15_FN,     GPSR6_15,
5244                 GP_6_14_FN,     GPSR6_14,
5245                 GP_6_13_FN,     GPSR6_13,
5246                 GP_6_12_FN,     GPSR6_12,
5247                 GP_6_11_FN,     GPSR6_11,
5248                 GP_6_10_FN,     GPSR6_10,
5249                 GP_6_9_FN,      GPSR6_9,
5250                 GP_6_8_FN,      GPSR6_8,
5251                 GP_6_7_FN,      GPSR6_7,
5252                 GP_6_6_FN,      GPSR6_6,
5253                 GP_6_5_FN,      GPSR6_5,
5254                 GP_6_4_FN,      GPSR6_4,
5255                 GP_6_3_FN,      GPSR6_3,
5256                 GP_6_2_FN,      GPSR6_2,
5257                 GP_6_1_FN,      GPSR6_1,
5258                 GP_6_0_FN,      GPSR6_0, }
5259         },
5260         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5261                 0, 0,
5262                 0, 0,
5263                 0, 0,
5264                 0, 0,
5265                 0, 0,
5266                 0, 0,
5267                 0, 0,
5268                 0, 0,
5269                 0, 0,
5270                 0, 0,
5271                 0, 0,
5272                 0, 0,
5273                 0, 0,
5274                 0, 0,
5275                 0, 0,
5276                 0, 0,
5277                 0, 0,
5278                 0, 0,
5279                 0, 0,
5280                 0, 0,
5281                 0, 0,
5282                 0, 0,
5283                 0, 0,
5284                 0, 0,
5285                 0, 0,
5286                 0, 0,
5287                 0, 0,
5288                 0, 0,
5289                 GP_7_3_FN, GPSR7_3,
5290                 GP_7_2_FN, GPSR7_2,
5291                 GP_7_1_FN, GPSR7_1,
5292                 GP_7_0_FN, GPSR7_0, }
5293         },
5294 #undef F_
5295 #undef FM
5296
5297 #define F_(x, y)        x,
5298 #define FM(x)           FN_##x,
5299         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5300                 IP0_31_28
5301                 IP0_27_24
5302                 IP0_23_20
5303                 IP0_19_16
5304                 IP0_15_12
5305                 IP0_11_8
5306                 IP0_7_4
5307                 IP0_3_0 }
5308         },
5309         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5310                 IP1_31_28
5311                 IP1_27_24
5312                 IP1_23_20
5313                 IP1_19_16
5314                 IP1_15_12
5315                 IP1_11_8
5316                 IP1_7_4
5317                 IP1_3_0 }
5318         },
5319         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5320                 IP2_31_28
5321                 IP2_27_24
5322                 IP2_23_20
5323                 IP2_19_16
5324                 IP2_15_12
5325                 IP2_11_8
5326                 IP2_7_4
5327                 IP2_3_0 }
5328         },
5329         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5330                 IP3_31_28
5331                 IP3_27_24
5332                 IP3_23_20
5333                 IP3_19_16
5334                 IP3_15_12
5335                 IP3_11_8
5336                 IP3_7_4
5337                 IP3_3_0 }
5338         },
5339         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5340                 IP4_31_28
5341                 IP4_27_24
5342                 IP4_23_20
5343                 IP4_19_16
5344                 IP4_15_12
5345                 IP4_11_8
5346                 IP4_7_4
5347                 IP4_3_0 }
5348         },
5349         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5350                 IP5_31_28
5351                 IP5_27_24
5352                 IP5_23_20
5353                 IP5_19_16
5354                 IP5_15_12
5355                 IP5_11_8
5356                 IP5_7_4
5357                 IP5_3_0 }
5358         },
5359         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5360                 IP6_31_28
5361                 IP6_27_24
5362                 IP6_23_20
5363                 IP6_19_16
5364                 IP6_15_12
5365                 IP6_11_8
5366                 IP6_7_4
5367                 IP6_3_0 }
5368         },
5369         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5370                 IP7_31_28
5371                 IP7_27_24
5372                 IP7_23_20
5373                 IP7_19_16
5374                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5375                 IP7_11_8
5376                 IP7_7_4
5377                 IP7_3_0 }
5378         },
5379         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5380                 IP8_31_28
5381                 IP8_27_24
5382                 IP8_23_20
5383                 IP8_19_16
5384                 IP8_15_12
5385                 IP8_11_8
5386                 IP8_7_4
5387                 IP8_3_0 }
5388         },
5389         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5390                 IP9_31_28
5391                 IP9_27_24
5392                 IP9_23_20
5393                 IP9_19_16
5394                 IP9_15_12
5395                 IP9_11_8
5396                 IP9_7_4
5397                 IP9_3_0 }
5398         },
5399         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5400                 IP10_31_28
5401                 IP10_27_24
5402                 IP10_23_20
5403                 IP10_19_16
5404                 IP10_15_12
5405                 IP10_11_8
5406                 IP10_7_4
5407                 IP10_3_0 }
5408         },
5409         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5410                 IP11_31_28
5411                 IP11_27_24
5412                 IP11_23_20
5413                 IP11_19_16
5414                 IP11_15_12
5415                 IP11_11_8
5416                 IP11_7_4
5417                 IP11_3_0 }
5418         },
5419         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5420                 IP12_31_28
5421                 IP12_27_24
5422                 IP12_23_20
5423                 IP12_19_16
5424                 IP12_15_12
5425                 IP12_11_8
5426                 IP12_7_4
5427                 IP12_3_0 }
5428         },
5429         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5430                 IP13_31_28
5431                 IP13_27_24
5432                 IP13_23_20
5433                 IP13_19_16
5434                 IP13_15_12
5435                 IP13_11_8
5436                 IP13_7_4
5437                 IP13_3_0 }
5438         },
5439         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5440                 IP14_31_28
5441                 IP14_27_24
5442                 IP14_23_20
5443                 IP14_19_16
5444                 IP14_15_12
5445                 IP14_11_8
5446                 IP14_7_4
5447                 IP14_3_0 }
5448         },
5449         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5450                 IP15_31_28
5451                 IP15_27_24
5452                 IP15_23_20
5453                 IP15_19_16
5454                 IP15_15_12
5455                 IP15_11_8
5456                 IP15_7_4
5457                 IP15_3_0 }
5458         },
5459         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5460                 IP16_31_28
5461                 IP16_27_24
5462                 IP16_23_20
5463                 IP16_19_16
5464                 IP16_15_12
5465                 IP16_11_8
5466                 IP16_7_4
5467                 IP16_3_0 }
5468         },
5469         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5470                 IP17_31_28
5471                 IP17_27_24
5472                 IP17_23_20
5473                 IP17_19_16
5474                 IP17_15_12
5475                 IP17_11_8
5476                 IP17_7_4
5477                 IP17_3_0 }
5478         },
5479         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5480                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5481                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5482                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5483                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5484                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5485                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5486                 IP18_7_4
5487                 IP18_3_0 }
5488         },
5489 #undef F_
5490 #undef FM
5491
5492 #define F_(x, y)        x,
5493 #define FM(x)           FN_##x,
5494         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5495                              3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5496                              1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5497                 MOD_SEL0_31_30_29
5498                 MOD_SEL0_28_27
5499                 MOD_SEL0_26_25_24
5500                 MOD_SEL0_23
5501                 MOD_SEL0_22
5502                 MOD_SEL0_21
5503                 MOD_SEL0_20
5504                 MOD_SEL0_19
5505                 MOD_SEL0_18_17
5506                 MOD_SEL0_16
5507                 0, 0, /* RESERVED 15 */
5508                 MOD_SEL0_14_13
5509                 MOD_SEL0_12
5510                 MOD_SEL0_11
5511                 MOD_SEL0_10
5512                 MOD_SEL0_9_8
5513                 MOD_SEL0_7_6
5514                 MOD_SEL0_5
5515                 MOD_SEL0_4_3
5516                 /* RESERVED 2, 1, 0 */
5517                 0, 0, 0, 0, 0, 0, 0, 0 }
5518         },
5519         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5520                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5521                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5522                 MOD_SEL1_31_30
5523                 MOD_SEL1_29_28_27
5524                 MOD_SEL1_26
5525                 MOD_SEL1_25_24
5526                 MOD_SEL1_23_22_21
5527                 MOD_SEL1_20
5528                 MOD_SEL1_19
5529                 MOD_SEL1_18_17
5530                 MOD_SEL1_16
5531                 MOD_SEL1_15_14
5532                 MOD_SEL1_13
5533                 MOD_SEL1_12
5534                 MOD_SEL1_11
5535                 MOD_SEL1_10
5536                 MOD_SEL1_9
5537                 0, 0, 0, 0, /* RESERVED 8, 7 */
5538                 MOD_SEL1_6
5539                 MOD_SEL1_5
5540                 MOD_SEL1_4
5541                 MOD_SEL1_3
5542                 MOD_SEL1_2
5543                 MOD_SEL1_1
5544                 MOD_SEL1_0 }
5545         },
5546         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5547                              1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5548                              4, 4, 4, 3, 1) {
5549                 MOD_SEL2_31
5550                 MOD_SEL2_30
5551                 MOD_SEL2_29
5552                 MOD_SEL2_28_27
5553                 MOD_SEL2_26
5554                 MOD_SEL2_25_24_23
5555                 MOD_SEL2_22
5556                 MOD_SEL2_21
5557                 MOD_SEL2_20
5558                 MOD_SEL2_19
5559                 MOD_SEL2_18
5560                 MOD_SEL2_17
5561                 /* RESERVED 16 */
5562                 0, 0,
5563                 /* RESERVED 15, 14, 13, 12 */
5564                 0, 0, 0, 0, 0, 0, 0, 0,
5565                 0, 0, 0, 0, 0, 0, 0, 0,
5566                 /* RESERVED 11, 10, 9, 8 */
5567                 0, 0, 0, 0, 0, 0, 0, 0,
5568                 0, 0, 0, 0, 0, 0, 0, 0,
5569                 /* RESERVED 7, 6, 5, 4 */
5570                 0, 0, 0, 0, 0, 0, 0, 0,
5571                 0, 0, 0, 0, 0, 0, 0, 0,
5572                 /* RESERVED 3, 2, 1 */
5573                 0, 0, 0, 0, 0, 0, 0, 0,
5574                 MOD_SEL2_0 }
5575         },
5576         { },
5577 };
5578
5579 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5580         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5581                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5582                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5583                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5584                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5585                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5586                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5587                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5588                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5589         } },
5590         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5591                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5592                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5593                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5594                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5595                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5596                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5597                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5598                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5599         } },
5600         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5601                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5602                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5603                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5604                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5605                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5606                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5607                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5608                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5609         } },
5610         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5611                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5612                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5613                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5614                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5615                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5616                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5617                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5618                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5619         } },
5620         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5621                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5622                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5623                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5624                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5625                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5626                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5627                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5628                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5629         } },
5630         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5631                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5632                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5633                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5634                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5635                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5636                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5637                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5638                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5639         } },
5640         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5641                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5642                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5643                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5644                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5645                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5646                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5647                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5648                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5649         } },
5650         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5651                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5652                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5653                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5654                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5655                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5656                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5657                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5658                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5659         } },
5660         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5661                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5662                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5663                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5664                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5665                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5666                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5667                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5668                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5669         } },
5670         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5671                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5672                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5673                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5674                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5675                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5676                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5677                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5678                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5679         } },
5680         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5681                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5682                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5683                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5684                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5685                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5686                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5687                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5688                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5689         } },
5690         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5691                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5692                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5693                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5694                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5695                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5696                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5697                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5698                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5699         } },
5700         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5701                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN2 */
5702                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5703                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5704         } },
5705         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5706                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5707                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5708                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5709                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5710                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5711                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5712                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5713                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5714         } },
5715         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5716                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5717                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5718                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5719                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5720                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5721                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5722                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5723                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5724         } },
5725         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5726                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5727                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5728                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5729                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5730                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5731                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5732                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5733                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5734         } },
5735         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5736                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5737                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5738                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5739                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5740                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5741                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5742                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5743                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5744         } },
5745         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5746                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5747                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5748                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5749                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5750                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5751                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5752                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5753                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5754         } },
5755         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5756                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5757                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5758                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5759                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5760                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5761                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5762                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5763                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5764         } },
5765         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5766                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5767                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5768                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5769                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5770                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5771                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5772                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5773                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5774         } },
5775         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5776                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5777                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5778                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5779                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5780                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5781                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5782                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5783                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5784         } },
5785         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5786                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5787                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5788                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5789                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5790                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5791                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5792                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5793                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5794         } },
5795         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5796                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5797                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5798                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5799                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5800                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5801                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5802                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5803                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5804         } },
5805         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5806                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5807                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5808                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5809                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5810                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5811                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5812                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5813                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5814         } },
5815         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5816                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5817                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5818                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5819                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5820                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5821                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5822                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5823         } },
5824         { },
5825 };
5826
5827 enum ioctrl_regs {
5828         POCCTRL,
5829 };
5830
5831 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5832         [POCCTRL] = { 0xe6060380, },
5833         { /* sentinel */ },
5834 };
5835
5836 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5837 {
5838         int bit = -EINVAL;
5839
5840         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5841
5842         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5843                 bit = pin & 0x1f;
5844
5845         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5846                 bit = (pin & 0x1f) + 12;
5847
5848         return bit;
5849 }
5850
5851 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5852         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5853                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5854                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5855                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5856                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5857                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5858                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5859                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5860                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5861                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5862                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5863                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5864                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5865                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5866                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5867                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5868                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5869                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5870                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5871                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5872                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5873                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5874                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5875                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5876                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5877                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5878                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5879                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5880                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5881                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5882                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5883                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5884                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5885         } },
5886         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5887                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5888                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5889                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5890                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5891                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5892                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5893                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5894                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5895                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5896                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5897                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5898                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5899                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5900                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5901                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5902                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5903                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5904                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5905                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5906                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5907                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5908                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5909                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5910                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5911                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5912                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5913                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5914                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5915                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5916                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5917                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5918                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5919         } },
5920         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5921                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5922                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5923                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5924                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5925                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5926                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5927                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5928                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5929                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5930                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5931                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5932                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5933                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5934                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5935                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5936                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5937                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5938                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5939                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5940                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5941                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5942                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5943                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5944                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5945                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5946                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5947                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5948                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5949                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
5950                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
5951                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5952                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5953         } },
5954         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5955                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN2 */
5956                 [ 1] = PIN_NONE,
5957                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
5958                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5959                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5960                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5961                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5962                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5963                 [ 8] = PIN_NONE,
5964                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5965                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5966                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5967                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5968                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5969                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5970                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5971                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5972                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5973                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5974                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5975                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5976                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5977                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5978                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5979                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5980                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5981                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5982                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5983                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5984                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5985                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5986                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5987         } },
5988         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5989                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5990                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5991                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5992                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5993                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5994                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5995                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5996                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5997                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5998                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5999                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
6000                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
6001                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
6002                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
6003                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
6004                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
6005                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
6006                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
6007                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
6008                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
6009                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
6010                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
6011                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
6012                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
6013                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
6014                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
6015                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
6016                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
6017                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
6018                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
6019                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
6020                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
6021         } },
6022         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6023                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
6024                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
6025                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
6026                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
6027                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
6028                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
6029                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
6030                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
6031                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
6032                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
6033                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
6034                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
6035                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
6036                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
6037                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
6038                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
6039                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
6040                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
6041                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
6042                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
6043                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
6044                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
6045                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
6046                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
6047                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
6048                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
6049                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
6050                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
6051                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
6052                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
6053                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
6054                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
6055         } },
6056         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6057                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
6058                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
6059                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
6060                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
6061                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
6062                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
6063                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
6064                 [ 7] = PIN_NONE,
6065                 [ 8] = PIN_NONE,
6066                 [ 9] = PIN_NONE,
6067                 [10] = PIN_NONE,
6068                 [11] = PIN_NONE,
6069                 [12] = PIN_NONE,
6070                 [13] = PIN_NONE,
6071                 [14] = PIN_NONE,
6072                 [15] = PIN_NONE,
6073                 [16] = PIN_NONE,
6074                 [17] = PIN_NONE,
6075                 [18] = PIN_NONE,
6076                 [19] = PIN_NONE,
6077                 [20] = PIN_NONE,
6078                 [21] = PIN_NONE,
6079                 [22] = PIN_NONE,
6080                 [23] = PIN_NONE,
6081                 [24] = PIN_NONE,
6082                 [25] = PIN_NONE,
6083                 [26] = PIN_NONE,
6084                 [27] = PIN_NONE,
6085                 [28] = PIN_NONE,
6086                 [29] = PIN_NONE,
6087                 [30] = PIN_NONE,
6088                 [31] = PIN_NONE,
6089         } },
6090         { /* sentinel */ },
6091 };
6092
6093 static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
6094                                             unsigned int pin)
6095 {
6096         const struct pinmux_bias_reg *reg;
6097         unsigned int bit;
6098
6099         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6100         if (!reg)
6101                 return PIN_CONFIG_BIAS_DISABLE;
6102
6103         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6104                 return PIN_CONFIG_BIAS_DISABLE;
6105         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6106                 return PIN_CONFIG_BIAS_PULL_UP;
6107         else
6108                 return PIN_CONFIG_BIAS_PULL_DOWN;
6109 }
6110
6111 static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6112                                    unsigned int bias)
6113 {
6114         const struct pinmux_bias_reg *reg;
6115         u32 enable, updown;
6116         unsigned int bit;
6117
6118         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6119         if (!reg)
6120                 return;
6121
6122         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6123         if (bias != PIN_CONFIG_BIAS_DISABLE)
6124                 enable |= BIT(bit);
6125
6126         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6127         if (bias == PIN_CONFIG_BIAS_PULL_UP)
6128                 updown |= BIT(bit);
6129
6130         sh_pfc_write(pfc, reg->pud, updown);
6131         sh_pfc_write(pfc, reg->puen, enable);
6132 }
6133
6134 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6135         .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6136         .get_bias = r8a7796_pinmux_get_bias,
6137         .set_bias = r8a7796_pinmux_set_bias,
6138 };
6139
6140 const struct sh_pfc_soc_info r8a7796_pinmux_info = {
6141         .name = "r8a77960_pfc",
6142         .ops = &r8a7796_pinmux_ops,
6143         .unlock_reg = 0xe6060000, /* PMMR */
6144
6145         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6146
6147         .pins = pinmux_pins,
6148         .nr_pins = ARRAY_SIZE(pinmux_pins),
6149         .groups = pinmux_groups,
6150         .nr_groups = ARRAY_SIZE(pinmux_groups),
6151         .functions = pinmux_functions,
6152         .nr_functions = ARRAY_SIZE(pinmux_functions),
6153
6154         .cfg_regs = pinmux_config_regs,
6155         .drive_regs = pinmux_drive_regs,
6156         .bias_regs = pinmux_bias_regs,
6157         .ioctrl_regs = pinmux_ioctrl_regs,
6158
6159         .pinmux_data = pinmux_data,
6160         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6161 };