git.sur5r.net Git - u-boot/blob - drivers/pinctrl/renesas/pfc-r8a77970.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A77970 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  *
   7  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   8  *
   9  * R-Car Gen3 processor support - PFC hardware block.
  10  *
  11  * Copyright (C) 2015  Renesas Electronics Corporation
  12  */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/kernel.h>
  19
  20 #include "sh_pfc.h"
  21
  22 #define CPU_ALL_PORT(fn, sfx)                                           \
  23         PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  24         PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  25         PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  26         PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  27         PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),       \
  28         PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
  29 /*
  30  * F_() : just information
  31  * FM() : macro for FN_xxx / xxx_MARK
  32  */
  33
  34 /* GPSR0 */
  35 #define GPSR0_21        F_(DU_EXODDF_DU_ODDF_DISP_CDE,  IP2_23_20)
  36 #define GPSR0_20        F_(DU_EXVSYNC_DU_VSYNC,         IP2_19_16)
  37 #define GPSR0_19        F_(DU_EXHSYNC_DU_HSYNC,         IP2_15_12)
  38 #define GPSR0_18        F_(DU_DOTCLKOUT,                IP2_11_8)
  39 #define GPSR0_17        F_(DU_DB7,                      IP2_7_4)
  40 #define GPSR0_16        F_(DU_DB6,                      IP2_3_0)
  41 #define GPSR0_15        F_(DU_DB5,                      IP1_31_28)
  42 #define GPSR0_14        F_(DU_DB4,                      IP1_27_24)
  43 #define GPSR0_13        F_(DU_DB3,                      IP1_23_20)
  44 #define GPSR0_12        F_(DU_DB2,                      IP1_19_16)
  45 #define GPSR0_11        F_(DU_DG7,                      IP1_15_12)
  46 #define GPSR0_10        F_(DU_DG6,                      IP1_11_8)
  47 #define GPSR0_9         F_(DU_DG5,                      IP1_7_4)
  48 #define GPSR0_8         F_(DU_DG4,                      IP1_3_0)
  49 #define GPSR0_7         F_(DU_DG3,                      IP0_31_28)
  50 #define GPSR0_6         F_(DU_DG2,                      IP0_27_24)
  51 #define GPSR0_5         F_(DU_DR7,                      IP0_23_20)
  52 #define GPSR0_4         F_(DU_DR6,                      IP0_19_16)
  53 #define GPSR0_3         F_(DU_DR5,                      IP0_15_12)
  54 #define GPSR0_2         F_(DU_DR4,                      IP0_11_8)
  55 #define GPSR0_1         F_(DU_DR3,                      IP0_7_4)
  56 #define GPSR0_0         F_(DU_DR2,                      IP0_3_0)
  57
  58 /* GPSR1 */
  59 #define GPSR1_27        F_(DIGRF_CLKOUT,        IP8_27_24)
  60 #define GPSR1_26        F_(DIGRF_CLKIN,         IP8_23_20)
  61 #define GPSR1_25        F_(CANFD_CLK_A,         IP8_19_16)
  62 #define GPSR1_24        F_(CANFD1_RX,           IP8_15_12)
  63 #define GPSR1_23        F_(CANFD1_TX,           IP8_11_8)
  64 #define GPSR1_22        F_(CANFD0_RX_A,         IP8_7_4)
  65 #define GPSR1_21        F_(CANFD0_TX_A,         IP8_3_0)
  66 #define GPSR1_20        F_(AVB0_AVTP_CAPTURE,   IP7_31_28)
  67 #define GPSR1_19        FM(AVB0_AVTP_MATCH)
  68 #define GPSR1_18        FM(AVB0_LINK)
  69 #define GPSR1_17        FM(AVB0_PHY_INT)
  70 #define GPSR1_16        FM(AVB0_MAGIC)
  71 #define GPSR1_15        FM(AVB0_MDC)
  72 #define GPSR1_14        FM(AVB0_MDIO)
  73 #define GPSR1_13        FM(AVB0_TXCREFCLK)
  74 #define GPSR1_12        FM(AVB0_TD3)
  75 #define GPSR1_11        FM(AVB0_TD2)
  76 #define GPSR1_10        FM(AVB0_TD1)
  77 #define GPSR1_9         FM(AVB0_TD0)
  78 #define GPSR1_8         FM(AVB0_TXC)
  79 #define GPSR1_7         FM(AVB0_TX_CTL)
  80 #define GPSR1_6         FM(AVB0_RD3)
  81 #define GPSR1_5         FM(AVB0_RD2)
  82 #define GPSR1_4         FM(AVB0_RD1)
  83 #define GPSR1_3         FM(AVB0_RD0)
  84 #define GPSR1_2         FM(AVB0_RXC)
  85 #define GPSR1_1         FM(AVB0_RX_CTL)
  86 #define GPSR1_0         F_(IRQ0,                IP2_27_24)
  87
  88 /* GPSR2 */
  89 #define GPSR2_16        F_(VI0_FIELD,           IP4_31_28)
  90 #define GPSR2_15        F_(VI0_DATA11,          IP4_27_24)
  91 #define GPSR2_14        F_(VI0_DATA10,          IP4_23_20)
  92 #define GPSR2_13        F_(VI0_DATA9,           IP4_19_16)
  93 #define GPSR2_12        F_(VI0_DATA8,           IP4_15_12)
  94 #define GPSR2_11        F_(VI0_DATA7,           IP4_11_8)
  95 #define GPSR2_10        F_(VI0_DATA6,           IP4_7_4)
  96 #define GPSR2_9         F_(VI0_DATA5,           IP4_3_0)
  97 #define GPSR2_8         F_(VI0_DATA4,           IP3_31_28)
  98 #define GPSR2_7         F_(VI0_DATA3,           IP3_27_24)
  99 #define GPSR2_6         F_(VI0_DATA2,           IP3_23_20)
 100 #define GPSR2_5         F_(VI0_DATA1,           IP3_19_16)
 101 #define GPSR2_4         F_(VI0_DATA0,           IP3_15_12)
 102 #define GPSR2_3         F_(VI0_VSYNC_N,         IP3_11_8)
 103 #define GPSR2_2         F_(VI0_HSYNC_N,         IP3_7_4)
 104 #define GPSR2_1         F_(VI0_CLKENB,          IP3_3_0)
 105 #define GPSR2_0         F_(VI0_CLK,             IP2_31_28)
 106
 107 /* GPSR3 */
 108 #define GPSR3_16        F_(VI1_FIELD,           IP7_3_0)
 109 #define GPSR3_15        F_(VI1_DATA11,          IP6_31_28)
 110 #define GPSR3_14        F_(VI1_DATA10,          IP6_27_24)
 111 #define GPSR3_13        F_(VI1_DATA9,           IP6_23_20)
 112 #define GPSR3_12        F_(VI1_DATA8,           IP6_19_16)
 113 #define GPSR3_11        F_(VI1_DATA7,           IP6_15_12)
 114 #define GPSR3_10        F_(VI1_DATA6,           IP6_11_8)
 115 #define GPSR3_9         F_(VI1_DATA5,           IP6_7_4)
 116 #define GPSR3_8         F_(VI1_DATA4,           IP6_3_0)
 117 #define GPSR3_7         F_(VI1_DATA3,           IP5_31_28)
 118 #define GPSR3_6         F_(VI1_DATA2,           IP5_27_24)
 119 #define GPSR3_5         F_(VI1_DATA1,           IP5_23_20)
 120 #define GPSR3_4         F_(VI1_DATA0,           IP5_19_16)
 121 #define GPSR3_3         F_(VI1_VSYNC_N,         IP5_15_12)
 122 #define GPSR3_2         F_(VI1_HSYNC_N,         IP5_11_8)
 123 #define GPSR3_1         F_(VI1_CLKENB,          IP5_7_4)
 124 #define GPSR3_0         F_(VI1_CLK,             IP5_3_0)
 125
 126 /* GPSR4 */
 127 #define GPSR4_5         F_(SDA2,                IP7_27_24)
 128 #define GPSR4_4         F_(SCL2,                IP7_23_20)
 129 #define GPSR4_3         F_(SDA1,                IP7_19_16)
 130 #define GPSR4_2         F_(SCL1,                IP7_15_12)
 131 #define GPSR4_1         F_(SDA0,                IP7_11_8)
 132 #define GPSR4_0         F_(SCL0,                IP7_7_4)
 133
 134 /* GPSR5 */
 135 #define GPSR5_14        FM(RPC_INT_N)
 136 #define GPSR5_13        FM(RPC_WP_N)
 137 #define GPSR5_12        FM(RPC_RESET_N)
 138 #define GPSR5_11        FM(QSPI1_SSL)
 139 #define GPSR5_10        FM(QSPI1_IO3)
 140 #define GPSR5_9         FM(QSPI1_IO2)
 141 #define GPSR5_8         FM(QSPI1_MISO_IO1)
 142 #define GPSR5_7         FM(QSPI1_MOSI_IO0)
 143 #define GPSR5_6         FM(QSPI1_SPCLK)
 144 #define GPSR5_5         FM(QSPI0_SSL)
 145 #define GPSR5_4         FM(QSPI0_IO3)
 146 #define GPSR5_3         FM(QSPI0_IO2)
 147 #define GPSR5_2         FM(QSPI0_MISO_IO1)
 148 #define GPSR5_1         FM(QSPI0_MOSI_IO0)
 149 #define GPSR5_0         FM(QSPI0_SPCLK)
 150
 151
 152 /* IPSRx */             /* 0 */                         /* 1 */                 /* 2 */         /* 3 */         /* 4 */                 /* 5 */         /* 6 - F */
 153 #define IP0_3_0         FM(DU_DR2)                      FM(HSCK0)               F_(0, 0)        FM(A0)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 154 #define IP0_7_4         FM(DU_DR3)                      FM(HRTS0_N)             F_(0, 0)        FM(A1)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 155 #define IP0_11_8        FM(DU_DR4)                      FM(HCTS0_N)             F_(0, 0)        FM(A2)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 156 #define IP0_15_12       FM(DU_DR5)                      FM(HTX0)                F_(0, 0)        FM(A3)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 157 #define IP0_19_16       FM(DU_DR6)                      FM(MSIOF3_RXD)          F_(0, 0)        FM(A4)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 158 #define IP0_23_20       FM(DU_DR7)                      FM(MSIOF3_TXD)          F_(0, 0)        FM(A5)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 159 #define IP0_27_24       FM(DU_DG2)                      FM(MSIOF3_SS1)          F_(0, 0)        FM(A6)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 160 #define IP0_31_28       FM(DU_DG3)                      FM(MSIOF3_SS2)          F_(0, 0)        FM(A7)          FM(PWMFSW0)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 161 #define IP1_3_0         FM(DU_DG4)                      F_(0, 0)                F_(0, 0)        FM(A8)          FM(FSO_CFE_0_N_A)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 162 #define IP1_7_4         FM(DU_DG5)                      F_(0, 0)                F_(0, 0)        FM(A9)          FM(FSO_CFE_1_N_A)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 163 #define IP1_11_8        FM(DU_DG6)                      F_(0, 0)                F_(0, 0)        FM(A10)         FM(FSO_TOE_N_A)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 164 #define IP1_15_12       FM(DU_DG7)                      F_(0, 0)                F_(0, 0)        FM(A11)         FM(IRQ1)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 165 #define IP1_19_16       FM(DU_DB2)                      F_(0, 0)                F_(0, 0)        FM(A12)         FM(IRQ2)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 166 #define IP1_23_20       FM(DU_DB3)                      F_(0, 0)                F_(0, 0)        FM(A13)         FM(FXR_CLKOUT1)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 167 #define IP1_27_24       FM(DU_DB4)                      F_(0, 0)                F_(0, 0)        FM(A14)         FM(FXR_CLKOUT2)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 168 #define IP1_31_28       FM(DU_DB5)                      F_(0, 0)                F_(0, 0)        FM(A15)         FM(FXR_TXENA_N)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 169 #define IP2_3_0         FM(DU_DB6)                      F_(0, 0)                F_(0, 0)        FM(A16)         FM(FXR_TXENB_N)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 170 #define IP2_7_4         FM(DU_DB7)                      F_(0, 0)                F_(0, 0)        FM(A17)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 171 #define IP2_11_8        FM(DU_DOTCLKOUT)                FM(SCIF_CLK_A)          F_(0, 0)        FM(A18)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 172 #define IP2_15_12       FM(DU_EXHSYNC_DU_HSYNC)         FM(HRX0)                F_(0, 0)        FM(A19)         FM(IRQ3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 173 #define IP2_19_16       FM(DU_EXVSYNC_DU_VSYNC)         FM(MSIOF3_SCK)          F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 174 #define IP2_23_20       FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(MSIOF3_SYNC)         F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 175 #define IP2_27_24       FM(IRQ0)                        FM(CC5_OSCOUT)          F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 176 #define IP2_31_28       FM(VI0_CLK)                     FM(MSIOF2_SCK)          FM(SCK3)        F_(0, 0)        FM(HSCK3)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 177 #define IP3_3_0         FM(VI0_CLKENB)                  FM(MSIOF2_RXD)          FM(RX3)         FM(RD_WR_N)     FM(HCTS3_N)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 178 #define IP3_7_4         FM(VI0_HSYNC_N)                 FM(MSIOF2_TXD)          FM(TX3)         F_(0, 0)        FM(HRTS3_N)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 179 #define IP3_11_8        FM(VI0_VSYNC_N)                 FM(MSIOF2_SYNC)         FM(CTS3_N)      F_(0, 0)        FM(HTX3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 180 #define IP3_15_12       FM(VI0_DATA0)                   FM(MSIOF2_SS1)          FM(RTS3_N_TANS) F_(0, 0)        FM(HRX3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 181 #define IP3_19_16       FM(VI0_DATA1)                   FM(MSIOF2_SS2)          FM(SCK1)        F_(0, 0)        FM(SPEEDIN_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 182 #define IP3_23_20       FM(VI0_DATA2)                   FM(AVB0_AVTP_PPS)       FM(SDA3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 183 #define IP3_27_24       FM(VI0_DATA3)                   FM(HSCK1)               FM(SCL3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 184 #define IP3_31_28       FM(VI0_DATA4)                   FM(HRTS1_N)             FM(RX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 185 #define IP4_3_0         FM(VI0_DATA5)                   FM(HCTS1_N)             FM(TX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 186 #define IP4_7_4         FM(VI0_DATA6)                   FM(HTX1)                FM(CTS1_N)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 187 #define IP4_11_8        FM(VI0_DATA7)                   FM(HRX1)                FM(RTS1_N_TANS) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 188 #define IP4_15_12       FM(VI0_DATA8)                   FM(HSCK2)               FM(PWM0_A)      FM(A22)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 189 #define IP4_19_16       FM(VI0_DATA9)                   FM(HCTS2_N)             FM(PWM1_A)      FM(A23)         FM(FSO_CFE_0_N_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 190 #define IP4_23_20       FM(VI0_DATA10)                  FM(HRTS2_N)             FM(PWM2_A)      FM(A24)         FM(FSO_CFE_1_N_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 191 #define IP4_27_24       FM(VI0_DATA11)                  FM(HTX2)                FM(PWM3_A)      FM(A25)         FM(FSO_TOE_N_B)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 192 #define IP4_31_28       FM(VI0_FIELD)                   FM(HRX2)                FM(PWM4_A)      FM(CS1_N)       FM(FSCLKST2_N_A)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 193 #define IP5_3_0         FM(VI1_CLK)                     FM(MSIOF1_RXD)          F_(0, 0)        FM(CS0_N)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 194 #define IP5_7_4         FM(VI1_CLKENB)                  FM(MSIOF1_TXD)          F_(0, 0)        FM(D0)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 195 #define IP5_11_8        FM(VI1_HSYNC_N)                 FM(MSIOF1_SCK)          F_(0, 0)        FM(D1)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 196 #define IP5_15_12       FM(VI1_VSYNC_N)                 FM(MSIOF1_SYNC)         F_(0, 0)        FM(D2)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 197 #define IP5_19_16       FM(VI1_DATA0)                   FM(MSIOF1_SS1)          F_(0, 0)        FM(D3)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 198 #define IP5_23_20       FM(VI1_DATA1)                   FM(MSIOF1_SS2)          F_(0, 0)        FM(D4)          FM(MMC_CMD)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 199 #define IP5_27_24       FM(VI1_DATA2)                   FM(CANFD0_TX_B)         F_(0, 0)        FM(D5)          FM(MMC_D0)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 200 #define IP5_31_28       FM(VI1_DATA3)                   FM(CANFD0_RX_B)         F_(0, 0)        FM(D6)          FM(MMC_D1)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 201 #define IP6_3_0         FM(VI1_DATA4)                   FM(CANFD_CLK_B)         F_(0, 0)        FM(D7)          FM(MMC_D2)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 202 #define IP6_7_4         FM(VI1_DATA5)                   F_(0,0)                 FM(SCK4)        FM(D8)          FM(MMC_D3)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 203 #define IP6_11_8        FM(VI1_DATA6)                   F_(0,0)                 FM(RX4)         FM(D9)          FM(MMC_CLK)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 204 #define IP6_15_12       FM(VI1_DATA7)                   F_(0,0)                 FM(TX4)         FM(D10)         FM(MMC_D4)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 205 #define IP6_19_16       FM(VI1_DATA8)                   F_(0,0)                 FM(CTS4_N)      FM(D11)         FM(MMC_D5)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 206 #define IP6_23_20       FM(VI1_DATA9)                   F_(0,0)                 FM(RTS4_N_TANS) FM(D12)         FM(MMC_D6)              FM(SCL3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 207 #define IP6_27_24       FM(VI1_DATA10)                  F_(0,0)                 F_(0, 0)        FM(D13)         FM(MMC_D7)              FM(SDA3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 208 #define IP6_31_28       FM(VI1_DATA11)                  FM(SCL4)                FM(IRQ4)        FM(D14)         FM(MMC_WP)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 209 #define IP7_3_0         FM(VI1_FIELD)                   FM(SDA4)                FM(IRQ5)        FM(D15)         FM(MMC_CD)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 210 #define IP7_7_4         FM(SCL0)                        FM(DU_DR0)              FM(TPU0TO0)     FM(CLKOUT)      F_(0, 0)                FM(MSIOF0_RXD)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 211 #define IP7_11_8        FM(SDA0)                        FM(DU_DR1)              FM(TPU0TO1)     FM(BS_N)        FM(SCK0)                FM(MSIOF0_TXD)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212 #define IP7_15_12       FM(SCL1)                        FM(DU_DG0)              FM(TPU0TO2)     FM(RD_N)        FM(CTS0_N)              FM(MSIOF0_SCK)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP7_19_16       FM(SDA1)                        FM(DU_DG1)              FM(TPU0TO3)     FM(WE0_N)       FM(RTS0_N_TANS)         FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP7_23_20       FM(SCL2)                        FM(DU_DB0)              FM(TCLK1_A)     FM(WE1_N)       FM(RX0)                 FM(MSIOF0_SS1)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP7_27_24       FM(SDA2)                        FM(DU_DB1)              FM(TCLK2_A)     FM(EX_WAIT0)    FM(TX0)                 FM(MSIOF0_SS2)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP7_31_28       FM(AVB0_AVTP_CAPTURE)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(FSCLKST2_N_B)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP8_3_0         FM(CANFD0_TX_A)                 FM(FXR_TXDA)            FM(PWM0_B)      FM(DU_DISP)     FM(FSCLKST2_N_C)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP8_7_4         FM(CANFD0_RX_A)                 FM(RXDA_EXTFXR)         FM(PWM1_B)      FM(DU_CDE)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP8_11_8        FM(CANFD1_TX)                   FM(FXR_TXDB)            FM(PWM2_B)      FM(TCLK1_B)     FM(TX1_B)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP8_15_12       FM(CANFD1_RX)                   FM(RXDB_EXTFXR)         FM(PWM3_B)      FM(TCLK2_B)     FM(RX1_B)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP8_19_16       FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)      FM(SPEEDIN_B)   FM(SCIF_CLK_B)          F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP8_23_20       FM(DIGRF_CLKIN)                 FM(DIGRF_CLKEN_IN)      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP8_27_24       FM(DIGRF_CLKOUT)                FM(DIGRF_CLKEN_OUT)     F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP8_31_28       F_(0, 0)                        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)  F_(0, 0) F_(0, 0) F_(0, 0)
 225
 226 #define PINMUX_GPSR     \
 227 \
 228                 GPSR1_27 \
 229                 GPSR1_26 \
 230                 GPSR1_25 \
 231                 GPSR1_24 \
 232                 GPSR1_23 \
 233                 GPSR1_22 \
 234 GPSR0_21        GPSR1_21 \
 235 GPSR0_20        GPSR1_20 \
 236 GPSR0_19        GPSR1_19 \
 237 GPSR0_18        GPSR1_18 \
 238 GPSR0_17        GPSR1_17 \
 239 GPSR0_16        GPSR1_16        GPSR2_16        GPSR3_16 \
 240 GPSR0_15        GPSR1_15        GPSR2_15        GPSR3_15 \
 241 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14                        GPSR5_14 \
 242 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13                        GPSR5_13 \
 243 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12                        GPSR5_12 \
 244 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11                        GPSR5_11 \
 245 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10                        GPSR5_10 \
 246 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9                         GPSR5_9 \
 247 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8                         GPSR5_8 \
 248 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7                         GPSR5_7 \
 249 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6                         GPSR5_6 \
 250 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5 \
 251 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4 \
 252 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3 \
 253 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2 \
 254 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1 \
 255 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0
 256
 257 #define PINMUX_IPSR     \
 258 \
 259 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 260 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 261 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 262 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 263 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 264 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 265 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 266 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 267 \
 268 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 269 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 270 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 271 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 272 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 273 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 274 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 275 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 276 \
 277 FM(IP8_3_0)     IP8_3_0 \
 278 FM(IP8_7_4)     IP8_7_4 \
 279 FM(IP8_11_8)    IP8_11_8 \
 280 FM(IP8_15_12)   IP8_15_12 \
 281 FM(IP8_19_16)   IP8_19_16 \
 282 FM(IP8_23_20)   IP8_23_20 \
 283 FM(IP8_27_24)   IP8_27_24 \
 284 FM(IP8_31_28)   IP8_31_28
 285
 286 /* MOD_SEL0 */          /* 0 */                 /* 1 */
 287 #define MOD_SEL0_11     FM(SEL_I2C3_0)          FM(SEL_I2C3_1)
 288 #define MOD_SEL0_10     FM(SEL_HSCIF0_0)        FM(SEL_HSCIF0_1)
 289 #define MOD_SEL0_9      FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 290 #define MOD_SEL0_8      FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 291 #define MOD_SEL0_7      FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 292 #define MOD_SEL0_6      FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 293 #define MOD_SEL0_5      FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 294 #define MOD_SEL0_4      FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 295 #define MOD_SEL0_3      FM(SEL_PWM0_0)          FM(SEL_PWM0_1)
 296 #define MOD_SEL0_2      FM(SEL_RFSO_0)          FM(SEL_RFSO_1)
 297 #define MOD_SEL0_1      FM(SEL_RSP_0)           FM(SEL_RSP_1)
 298 #define MOD_SEL0_0      FM(SEL_TMU_0)           FM(SEL_TMU_1)
 299
 300 #define PINMUX_MOD_SELS \
 301 \
 302 MOD_SEL0_11 \
 303 MOD_SEL0_10 \
 304 MOD_SEL0_9 \
 305 MOD_SEL0_8 \
 306 MOD_SEL0_7 \
 307 MOD_SEL0_6 \
 308 MOD_SEL0_5 \
 309 MOD_SEL0_4 \
 310 MOD_SEL0_3 \
 311 MOD_SEL0_2 \
 312 MOD_SEL0_1 \
 313 MOD_SEL0_0
 314
 315 enum {
 316         PINMUX_RESERVED = 0,
 317
 318         PINMUX_DATA_BEGIN,
 319         GP_ALL(DATA),
 320         PINMUX_DATA_END,
 321
 322 #define F_(x, y)
 323 #define FM(x)   FN_##x,
 324         PINMUX_FUNCTION_BEGIN,
 325         GP_ALL(FN),
 326         PINMUX_GPSR
 327         PINMUX_IPSR
 328         PINMUX_MOD_SELS
 329         PINMUX_FUNCTION_END,
 330 #undef F_
 331 #undef FM
 332
 333 #define F_(x, y)
 334 #define FM(x)   x##_MARK,
 335         PINMUX_MARK_BEGIN,
 336         PINMUX_GPSR
 337         PINMUX_IPSR
 338         PINMUX_MOD_SELS
 339         PINMUX_MARK_END,
 340 #undef F_
 341 #undef FM
 342 };
 343
 344 static const u16 pinmux_data[] = {
 345         PINMUX_DATA_GP_ALL(),
 346
 347         PINMUX_SINGLE(AVB0_RX_CTL),
 348         PINMUX_SINGLE(AVB0_RXC),
 349         PINMUX_SINGLE(AVB0_RD0),
 350         PINMUX_SINGLE(AVB0_RD1),
 351         PINMUX_SINGLE(AVB0_RD2),
 352         PINMUX_SINGLE(AVB0_RD3),
 353         PINMUX_SINGLE(AVB0_TX_CTL),
 354         PINMUX_SINGLE(AVB0_TXC),
 355         PINMUX_SINGLE(AVB0_TD0),
 356         PINMUX_SINGLE(AVB0_TD1),
 357         PINMUX_SINGLE(AVB0_TD2),
 358         PINMUX_SINGLE(AVB0_TD3),
 359         PINMUX_SINGLE(AVB0_TXCREFCLK),
 360         PINMUX_SINGLE(AVB0_MDIO),
 361         PINMUX_SINGLE(AVB0_MDC),
 362         PINMUX_SINGLE(AVB0_MAGIC),
 363         PINMUX_SINGLE(AVB0_PHY_INT),
 364         PINMUX_SINGLE(AVB0_LINK),
 365         PINMUX_SINGLE(AVB0_AVTP_MATCH),
 366
 367         PINMUX_SINGLE(QSPI0_SPCLK),
 368         PINMUX_SINGLE(QSPI0_MOSI_IO0),
 369         PINMUX_SINGLE(QSPI0_MISO_IO1),
 370         PINMUX_SINGLE(QSPI0_IO2),
 371         PINMUX_SINGLE(QSPI0_IO3),
 372         PINMUX_SINGLE(QSPI0_SSL),
 373         PINMUX_SINGLE(QSPI1_SPCLK),
 374         PINMUX_SINGLE(QSPI1_MOSI_IO0),
 375         PINMUX_SINGLE(QSPI1_MISO_IO1),
 376         PINMUX_SINGLE(QSPI1_IO2),
 377         PINMUX_SINGLE(QSPI1_IO3),
 378         PINMUX_SINGLE(QSPI1_SSL),
 379         PINMUX_SINGLE(RPC_RESET_N),
 380         PINMUX_SINGLE(RPC_WP_N),
 381         PINMUX_SINGLE(RPC_INT_N),
 382
 383         /* IPSR0 */
 384         PINMUX_IPSR_GPSR(IP0_3_0,       DU_DR2),
 385         PINMUX_IPSR_GPSR(IP0_3_0,       HSCK0),
 386         PINMUX_IPSR_GPSR(IP0_3_0,       A0),
 387
 388         PINMUX_IPSR_GPSR(IP0_7_4,       DU_DR3),
 389         PINMUX_IPSR_GPSR(IP0_7_4,       HRTS0_N),
 390         PINMUX_IPSR_GPSR(IP0_7_4,       A1),
 391
 392         PINMUX_IPSR_GPSR(IP0_11_8,      DU_DR4),
 393         PINMUX_IPSR_GPSR(IP0_11_8,      HCTS0_N),
 394         PINMUX_IPSR_GPSR(IP0_11_8,      A2),
 395
 396         PINMUX_IPSR_GPSR(IP0_15_12,     DU_DR5),
 397         PINMUX_IPSR_GPSR(IP0_15_12,     HTX0),
 398         PINMUX_IPSR_GPSR(IP0_15_12,     A3),
 399
 400         PINMUX_IPSR_GPSR(IP0_19_16,     DU_DR6),
 401         PINMUX_IPSR_GPSR(IP0_19_16,     MSIOF3_RXD),
 402         PINMUX_IPSR_GPSR(IP0_19_16,     A4),
 403
 404         PINMUX_IPSR_GPSR(IP0_23_20,     DU_DR7),
 405         PINMUX_IPSR_GPSR(IP0_23_20,     MSIOF3_TXD),
 406         PINMUX_IPSR_GPSR(IP0_23_20,     A5),
 407
 408         PINMUX_IPSR_GPSR(IP0_27_24,     DU_DG2),
 409         PINMUX_IPSR_GPSR(IP0_27_24,     MSIOF3_SS1),
 410         PINMUX_IPSR_GPSR(IP0_27_24,     A6),
 411
 412         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DG3),
 413         PINMUX_IPSR_GPSR(IP0_31_28,     MSIOF3_SS2),
 414         PINMUX_IPSR_GPSR(IP0_31_28,     A7),
 415         PINMUX_IPSR_GPSR(IP0_31_28,     PWMFSW0),
 416
 417         /* IPSR1 */
 418         PINMUX_IPSR_GPSR(IP1_3_0,       DU_DG4),
 419         PINMUX_IPSR_GPSR(IP1_3_0,       A8),
 420         PINMUX_IPSR_MSEL(IP1_3_0,       FSO_CFE_0_N_A,  SEL_RFSO_0),
 421
 422         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DG5),
 423         PINMUX_IPSR_GPSR(IP1_7_4,       A9),
 424         PINMUX_IPSR_MSEL(IP1_7_4,       FSO_CFE_1_N_A,  SEL_RFSO_0),
 425
 426         PINMUX_IPSR_GPSR(IP1_11_8,      DU_DG6),
 427         PINMUX_IPSR_GPSR(IP1_11_8,      A10),
 428         PINMUX_IPSR_MSEL(IP1_11_8,      FSO_TOE_N_A,    SEL_RFSO_0),
 429
 430         PINMUX_IPSR_GPSR(IP1_15_12,     DU_DG7),
 431         PINMUX_IPSR_GPSR(IP1_15_12,     A11),
 432         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ1),
 433
 434         PINMUX_IPSR_GPSR(IP1_19_16,     DU_DB2),
 435         PINMUX_IPSR_GPSR(IP1_19_16,     A12),
 436         PINMUX_IPSR_GPSR(IP1_19_16,     IRQ2),
 437
 438         PINMUX_IPSR_GPSR(IP1_23_20,     DU_DB3),
 439         PINMUX_IPSR_GPSR(IP1_23_20,     A13),
 440         PINMUX_IPSR_GPSR(IP1_23_20,     FXR_CLKOUT1),
 441
 442         PINMUX_IPSR_GPSR(IP1_27_24,     DU_DB4),
 443         PINMUX_IPSR_GPSR(IP1_27_24,     A14),
 444         PINMUX_IPSR_GPSR(IP1_27_24,     FXR_CLKOUT2),
 445
 446         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB5),
 447         PINMUX_IPSR_GPSR(IP1_31_28,     A15),
 448         PINMUX_IPSR_GPSR(IP1_31_28,     FXR_TXENA_N),
 449
 450         /* IPSR2 */
 451         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB6),
 452         PINMUX_IPSR_GPSR(IP2_3_0,       A16),
 453         PINMUX_IPSR_GPSR(IP2_3_0,       FXR_TXENB_N),
 454
 455         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB7),
 456         PINMUX_IPSR_GPSR(IP2_7_4,       A17),
 457
 458         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DOTCLKOUT),
 459         PINMUX_IPSR_MSEL(IP2_11_8,      SCIF_CLK_A,     SEL_HSCIF0_0),
 460         PINMUX_IPSR_GPSR(IP2_11_8,      A18),
 461
 462         PINMUX_IPSR_GPSR(IP2_15_12,     DU_EXHSYNC_DU_HSYNC),
 463         PINMUX_IPSR_GPSR(IP2_15_12,     HRX0),
 464         PINMUX_IPSR_GPSR(IP2_15_12,     A19),
 465         PINMUX_IPSR_GPSR(IP2_15_12,     IRQ3),
 466
 467         PINMUX_IPSR_GPSR(IP2_19_16,     DU_EXVSYNC_DU_VSYNC),
 468         PINMUX_IPSR_GPSR(IP2_19_16,     MSIOF3_SCK),
 469
 470         PINMUX_IPSR_GPSR(IP2_23_20,     DU_EXODDF_DU_ODDF_DISP_CDE),
 471         PINMUX_IPSR_GPSR(IP2_23_20,     MSIOF3_SYNC),
 472
 473         PINMUX_IPSR_GPSR(IP2_27_24,     IRQ0),
 474         PINMUX_IPSR_GPSR(IP2_27_24,     CC5_OSCOUT),
 475
 476         PINMUX_IPSR_GPSR(IP2_31_28,     VI0_CLK),
 477         PINMUX_IPSR_GPSR(IP2_31_28,     MSIOF2_SCK),
 478         PINMUX_IPSR_GPSR(IP2_31_28,     SCK3),
 479         PINMUX_IPSR_GPSR(IP2_31_28,     HSCK3),
 480
 481         /* IPSR3 */
 482         PINMUX_IPSR_GPSR(IP3_3_0,       VI0_CLKENB),
 483         PINMUX_IPSR_GPSR(IP3_3_0,       MSIOF2_RXD),
 484         PINMUX_IPSR_GPSR(IP3_3_0,       RX3),
 485         PINMUX_IPSR_GPSR(IP3_3_0,       RD_WR_N),
 486         PINMUX_IPSR_GPSR(IP3_3_0,       HCTS3_N),
 487
 488         PINMUX_IPSR_GPSR(IP3_7_4,       VI0_HSYNC_N),
 489         PINMUX_IPSR_GPSR(IP3_7_4,       MSIOF2_TXD),
 490         PINMUX_IPSR_GPSR(IP3_7_4,       TX3),
 491         PINMUX_IPSR_GPSR(IP3_7_4,       HRTS3_N),
 492
 493         PINMUX_IPSR_GPSR(IP3_11_8,      VI0_VSYNC_N),
 494         PINMUX_IPSR_GPSR(IP3_11_8,      MSIOF2_SYNC),
 495         PINMUX_IPSR_GPSR(IP3_11_8,      CTS3_N),
 496         PINMUX_IPSR_GPSR(IP3_11_8,      HTX3),
 497
 498         PINMUX_IPSR_GPSR(IP3_15_12,     VI0_DATA0),
 499         PINMUX_IPSR_GPSR(IP3_15_12,     MSIOF2_SS1),
 500         PINMUX_IPSR_GPSR(IP3_15_12,     RTS3_N_TANS),
 501         PINMUX_IPSR_GPSR(IP3_15_12,     HRX3),
 502
 503         PINMUX_IPSR_GPSR(IP3_19_16,     VI0_DATA1),
 504         PINMUX_IPSR_GPSR(IP3_19_16,     MSIOF2_SS2),
 505         PINMUX_IPSR_GPSR(IP3_19_16,     SCK1),
 506         PINMUX_IPSR_MSEL(IP3_19_16,     SPEEDIN_A,      SEL_RSP_0),
 507
 508         PINMUX_IPSR_GPSR(IP3_23_20,     VI0_DATA2),
 509         PINMUX_IPSR_GPSR(IP3_23_20,     AVB0_AVTP_PPS),
 510         PINMUX_IPSR_MSEL(IP3_23_20,     SDA3_A,         SEL_I2C3_0),
 511
 512         PINMUX_IPSR_GPSR(IP3_27_24,     VI0_DATA3),
 513         PINMUX_IPSR_GPSR(IP3_27_24,     HSCK1),
 514         PINMUX_IPSR_MSEL(IP3_27_24,     SCL3_A,         SEL_I2C3_0),
 515
 516         PINMUX_IPSR_GPSR(IP3_31_28,     VI0_DATA4),
 517         PINMUX_IPSR_GPSR(IP3_31_28,     HRTS1_N),
 518         PINMUX_IPSR_MSEL(IP3_31_28,     RX1_A,  SEL_SCIF1_0),
 519
 520         /* IPSR4 */
 521         PINMUX_IPSR_GPSR(IP4_3_0,       VI0_DATA5),
 522         PINMUX_IPSR_GPSR(IP4_3_0,       HCTS1_N),
 523         PINMUX_IPSR_MSEL(IP4_3_0,       TX1_A,  SEL_SCIF1_0),
 524
 525         PINMUX_IPSR_GPSR(IP4_7_4,       VI0_DATA6),
 526         PINMUX_IPSR_GPSR(IP4_7_4,       HTX1),
 527         PINMUX_IPSR_GPSR(IP4_7_4,       CTS1_N),
 528
 529         PINMUX_IPSR_GPSR(IP4_11_8,      VI0_DATA7),
 530         PINMUX_IPSR_GPSR(IP4_11_8,      HRX1),
 531         PINMUX_IPSR_GPSR(IP4_11_8,      RTS1_N_TANS),
 532
 533         PINMUX_IPSR_GPSR(IP4_15_12,     VI0_DATA8),
 534         PINMUX_IPSR_GPSR(IP4_15_12,     HSCK2),
 535         PINMUX_IPSR_MSEL(IP4_15_12,     PWM0_A, SEL_PWM0_0),
 536
 537         PINMUX_IPSR_GPSR(IP4_19_16,     VI0_DATA9),
 538         PINMUX_IPSR_GPSR(IP4_19_16,     HCTS2_N),
 539         PINMUX_IPSR_MSEL(IP4_19_16,     PWM1_A, SEL_PWM1_0),
 540         PINMUX_IPSR_MSEL(IP4_19_16,     FSO_CFE_0_N_B,  SEL_RFSO_1),
 541
 542         PINMUX_IPSR_GPSR(IP4_23_20,     VI0_DATA10),
 543         PINMUX_IPSR_GPSR(IP4_23_20,     HRTS2_N),
 544         PINMUX_IPSR_MSEL(IP4_23_20,     PWM2_A, SEL_PWM2_0),
 545         PINMUX_IPSR_MSEL(IP4_23_20,     FSO_CFE_1_N_B,  SEL_RFSO_1),
 546
 547         PINMUX_IPSR_GPSR(IP4_27_24,     VI0_DATA11),
 548         PINMUX_IPSR_GPSR(IP4_27_24,     HTX2),
 549         PINMUX_IPSR_MSEL(IP4_27_24,     PWM3_A, SEL_PWM3_0),
 550         PINMUX_IPSR_MSEL(IP4_27_24,     FSO_TOE_N_B,    SEL_RFSO_1),
 551
 552         PINMUX_IPSR_GPSR(IP4_31_28,     VI0_FIELD),
 553         PINMUX_IPSR_GPSR(IP4_31_28,     HRX2),
 554         PINMUX_IPSR_MSEL(IP4_31_28,     PWM4_A, SEL_PWM4_0),
 555         PINMUX_IPSR_GPSR(IP4_31_28,     CS1_N),
 556         PINMUX_IPSR_GPSR(IP4_31_28,     FSCLKST2_N_A),
 557
 558         /* IPSR5 */
 559         PINMUX_IPSR_GPSR(IP5_3_0,       VI1_CLK),
 560         PINMUX_IPSR_GPSR(IP5_3_0,       MSIOF1_RXD),
 561         PINMUX_IPSR_GPSR(IP5_3_0,       CS0_N),
 562
 563         PINMUX_IPSR_GPSR(IP5_7_4,       VI1_CLKENB),
 564         PINMUX_IPSR_GPSR(IP5_7_4,       MSIOF1_TXD),
 565         PINMUX_IPSR_GPSR(IP5_7_4,       D0),
 566
 567         PINMUX_IPSR_GPSR(IP5_11_8,      VI1_HSYNC_N),
 568         PINMUX_IPSR_GPSR(IP5_11_8,      MSIOF1_SCK),
 569         PINMUX_IPSR_GPSR(IP5_11_8,      D1),
 570
 571         PINMUX_IPSR_GPSR(IP5_15_12,     VI1_VSYNC_N),
 572         PINMUX_IPSR_GPSR(IP5_15_12,     MSIOF1_SYNC),
 573         PINMUX_IPSR_GPSR(IP5_15_12,     D2),
 574
 575         PINMUX_IPSR_GPSR(IP5_19_16,     VI1_DATA0),
 576         PINMUX_IPSR_GPSR(IP5_19_16,     MSIOF1_SS1),
 577         PINMUX_IPSR_GPSR(IP5_19_16,     D3),
 578
 579         PINMUX_IPSR_GPSR(IP5_23_20,     VI1_DATA1),
 580         PINMUX_IPSR_GPSR(IP5_23_20,     MSIOF1_SS2),
 581         PINMUX_IPSR_GPSR(IP5_23_20,     D4),
 582         PINMUX_IPSR_GPSR(IP5_23_20,     MMC_CMD),
 583
 584         PINMUX_IPSR_GPSR(IP5_27_24,     VI1_DATA2),
 585         PINMUX_IPSR_MSEL(IP5_27_24,     CANFD0_TX_B,    SEL_CANFD0_1),
 586         PINMUX_IPSR_GPSR(IP5_27_24,     D5),
 587         PINMUX_IPSR_GPSR(IP5_27_24,     MMC_D0),
 588
 589         PINMUX_IPSR_GPSR(IP5_31_28,     VI1_DATA3),
 590         PINMUX_IPSR_MSEL(IP5_31_28,     CANFD0_RX_B,    SEL_CANFD0_1),
 591         PINMUX_IPSR_GPSR(IP5_31_28,     D6),
 592         PINMUX_IPSR_GPSR(IP5_31_28,     MMC_D1),
 593
 594         /* IPSR6 */
 595         PINMUX_IPSR_GPSR(IP6_3_0,       VI1_DATA4),
 596         PINMUX_IPSR_MSEL(IP6_3_0,       CANFD_CLK_B,    SEL_CANFD0_1),
 597         PINMUX_IPSR_GPSR(IP6_3_0,       D7),
 598         PINMUX_IPSR_GPSR(IP6_3_0,       MMC_D2),
 599
 600         PINMUX_IPSR_GPSR(IP6_7_4,       VI1_DATA5),
 601         PINMUX_IPSR_GPSR(IP6_7_4,       SCK4),
 602         PINMUX_IPSR_GPSR(IP6_7_4,       D8),
 603         PINMUX_IPSR_GPSR(IP6_7_4,       MMC_D3),
 604
 605         PINMUX_IPSR_GPSR(IP6_11_8,      VI1_DATA6),
 606         PINMUX_IPSR_GPSR(IP6_11_8,      RX4),
 607         PINMUX_IPSR_GPSR(IP6_11_8,      D9),
 608         PINMUX_IPSR_GPSR(IP6_11_8,      MMC_CLK),
 609
 610         PINMUX_IPSR_GPSR(IP6_15_12,     VI1_DATA7),
 611         PINMUX_IPSR_GPSR(IP6_15_12,     TX4),
 612         PINMUX_IPSR_GPSR(IP6_15_12,     D10),
 613         PINMUX_IPSR_GPSR(IP6_15_12,     MMC_D4),
 614
 615         PINMUX_IPSR_GPSR(IP6_19_16,     VI1_DATA8),
 616         PINMUX_IPSR_GPSR(IP6_19_16,     CTS4_N),
 617         PINMUX_IPSR_GPSR(IP6_19_16,     D11),
 618         PINMUX_IPSR_GPSR(IP6_19_16,     MMC_D5),
 619
 620         PINMUX_IPSR_GPSR(IP6_23_20,     VI1_DATA9),
 621         PINMUX_IPSR_GPSR(IP6_23_20,     RTS4_N_TANS),
 622         PINMUX_IPSR_GPSR(IP6_23_20,     D12),
 623         PINMUX_IPSR_GPSR(IP6_23_20,     MMC_D6),
 624         PINMUX_IPSR_MSEL(IP6_23_20,     SCL3_B, SEL_I2C3_1),
 625
 626         PINMUX_IPSR_GPSR(IP6_27_24,     VI1_DATA10),
 627         PINMUX_IPSR_GPSR(IP6_27_24,     D13),
 628         PINMUX_IPSR_GPSR(IP6_27_24,     MMC_D7),
 629         PINMUX_IPSR_MSEL(IP6_27_24,     SDA3_B, SEL_I2C3_1),
 630
 631         PINMUX_IPSR_GPSR(IP6_31_28,     VI1_DATA11),
 632         PINMUX_IPSR_GPSR(IP6_31_28,     SCL4),
 633         PINMUX_IPSR_GPSR(IP6_31_28,     IRQ4),
 634         PINMUX_IPSR_GPSR(IP6_31_28,     D14),
 635         PINMUX_IPSR_GPSR(IP6_31_28,     MMC_WP),
 636
 637         /* IPSR7 */
 638         PINMUX_IPSR_GPSR(IP7_3_0,       VI1_FIELD),
 639         PINMUX_IPSR_GPSR(IP7_3_0,       SDA4),
 640         PINMUX_IPSR_GPSR(IP7_3_0,       IRQ5),
 641         PINMUX_IPSR_GPSR(IP7_3_0,       D15),
 642         PINMUX_IPSR_GPSR(IP7_3_0,       MMC_CD),
 643
 644         PINMUX_IPSR_GPSR(IP7_7_4,       SCL0),
 645         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR0),
 646         PINMUX_IPSR_GPSR(IP7_7_4,       TPU0TO0),
 647         PINMUX_IPSR_GPSR(IP7_7_4,       CLKOUT),
 648         PINMUX_IPSR_GPSR(IP7_7_4,       MSIOF0_RXD),
 649
 650         PINMUX_IPSR_GPSR(IP7_11_8,      SDA0),
 651         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR1),
 652         PINMUX_IPSR_GPSR(IP7_11_8,      TPU0TO1),
 653         PINMUX_IPSR_GPSR(IP7_11_8,      BS_N),
 654         PINMUX_IPSR_GPSR(IP7_11_8,      SCK0),
 655         PINMUX_IPSR_GPSR(IP7_11_8,      MSIOF0_TXD),
 656
 657         PINMUX_IPSR_GPSR(IP7_15_12,     SCL1),
 658         PINMUX_IPSR_GPSR(IP7_15_12,     DU_DG0),
 659         PINMUX_IPSR_GPSR(IP7_15_12,     TPU0TO2),
 660         PINMUX_IPSR_GPSR(IP7_15_12,     RD_N),
 661         PINMUX_IPSR_GPSR(IP7_15_12,     CTS0_N),
 662         PINMUX_IPSR_GPSR(IP7_15_12,     MSIOF0_SCK),
 663
 664         PINMUX_IPSR_GPSR(IP7_19_16,     SDA1),
 665         PINMUX_IPSR_GPSR(IP7_19_16,     DU_DG1),
 666         PINMUX_IPSR_GPSR(IP7_19_16,     TPU0TO3),
 667         PINMUX_IPSR_GPSR(IP7_19_16,     WE0_N),
 668         PINMUX_IPSR_GPSR(IP7_19_16,     RTS0_N_TANS),
 669         PINMUX_IPSR_GPSR(IP7_19_16,     MSIOF0_SYNC),
 670
 671         PINMUX_IPSR_GPSR(IP7_23_20,     SCL2),
 672         PINMUX_IPSR_GPSR(IP7_23_20,     DU_DB0),
 673         PINMUX_IPSR_MSEL(IP7_23_20,     TCLK1_A,        SEL_TMU_0),
 674         PINMUX_IPSR_GPSR(IP7_23_20,     WE1_N),
 675         PINMUX_IPSR_GPSR(IP7_23_20,     RX0),
 676         PINMUX_IPSR_GPSR(IP7_23_20,     MSIOF0_SS1),
 677
 678         PINMUX_IPSR_GPSR(IP7_27_24,     SDA2),
 679         PINMUX_IPSR_GPSR(IP7_27_24,     DU_DB1),
 680         PINMUX_IPSR_MSEL(IP7_27_24,     TCLK2_A,        SEL_TMU_0),
 681         PINMUX_IPSR_GPSR(IP7_27_24,     EX_WAIT0),
 682         PINMUX_IPSR_GPSR(IP7_27_24,     TX0),
 683         PINMUX_IPSR_GPSR(IP7_27_24,     MSIOF0_SS2),
 684
 685         PINMUX_IPSR_GPSR(IP7_31_28,     AVB0_AVTP_CAPTURE),
 686         PINMUX_IPSR_GPSR(IP7_31_28,     FSCLKST2_N_B),
 687
 688         /* IPSR8 */
 689         PINMUX_IPSR_MSEL(IP8_3_0,       CANFD0_TX_A,    SEL_CANFD0_0),
 690         PINMUX_IPSR_GPSR(IP8_3_0,       FXR_TXDA),
 691         PINMUX_IPSR_MSEL(IP8_3_0,       PWM0_B,         SEL_PWM0_1),
 692         PINMUX_IPSR_GPSR(IP8_3_0,       DU_DISP),
 693         PINMUX_IPSR_GPSR(IP8_3_0,       FSCLKST2_N_C),
 694
 695         PINMUX_IPSR_MSEL(IP8_7_4,       CANFD0_RX_A,    SEL_CANFD0_0),
 696         PINMUX_IPSR_GPSR(IP8_7_4,       RXDA_EXTFXR),
 697         PINMUX_IPSR_MSEL(IP8_7_4,       PWM1_B,         SEL_PWM1_1),
 698         PINMUX_IPSR_GPSR(IP8_7_4,       DU_CDE),
 699
 700         PINMUX_IPSR_GPSR(IP8_11_8,      CANFD1_TX),
 701         PINMUX_IPSR_GPSR(IP8_11_8,      FXR_TXDB),
 702         PINMUX_IPSR_MSEL(IP8_11_8,      PWM2_B,         SEL_PWM2_1),
 703         PINMUX_IPSR_MSEL(IP8_11_8,      TCLK1_B,        SEL_TMU_1),
 704         PINMUX_IPSR_MSEL(IP8_11_8,      TX1_B,          SEL_SCIF1_1),
 705
 706         PINMUX_IPSR_GPSR(IP8_15_12,     CANFD1_RX),
 707         PINMUX_IPSR_GPSR(IP8_15_12,     RXDB_EXTFXR),
 708         PINMUX_IPSR_MSEL(IP8_15_12,     PWM3_B,         SEL_PWM3_1),
 709         PINMUX_IPSR_MSEL(IP8_15_12,     TCLK2_B,        SEL_TMU_1),
 710         PINMUX_IPSR_MSEL(IP8_15_12,     RX1_B,          SEL_SCIF1_1),
 711
 712         PINMUX_IPSR_MSEL(IP8_19_16,     CANFD_CLK_A,    SEL_CANFD0_0),
 713         PINMUX_IPSR_GPSR(IP8_19_16,     CLK_EXTFXR),
 714         PINMUX_IPSR_MSEL(IP8_19_16,     PWM4_B,         SEL_PWM4_1),
 715         PINMUX_IPSR_MSEL(IP8_19_16,     SPEEDIN_B,      SEL_RSP_1),
 716         PINMUX_IPSR_MSEL(IP8_19_16,     SCIF_CLK_B,     SEL_HSCIF0_1),
 717
 718         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKIN),
 719         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKEN_IN),
 720
 721         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKOUT),
 722         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKEN_OUT),
 723 };
 724
 725 static const struct sh_pfc_pin pinmux_pins[] = {
 726         PINMUX_GPIO_GP_ALL(),
 727 };
 728
 729 /* - AVB0 ------------------------------------------------------------------- */
 730 static const unsigned int avb0_link_pins[] = {
 731         /* AVB0_LINK */
 732         RCAR_GP_PIN(1, 18),
 733 };
 734 static const unsigned int avb0_link_mux[] = {
 735         AVB0_LINK_MARK,
 736 };
 737 static const unsigned int avb0_magic_pins[] = {
 738         /* AVB0_MAGIC */
 739         RCAR_GP_PIN(1, 16),
 740 };
 741 static const unsigned int avb0_magic_mux[] = {
 742         AVB0_MAGIC_MARK,
 743 };
 744 static const unsigned int avb0_phy_int_pins[] = {
 745         /* AVB0_PHY_INT */
 746         RCAR_GP_PIN(1, 17),
 747 };
 748 static const unsigned int avb0_phy_int_mux[] = {
 749         AVB0_PHY_INT_MARK,
 750 };
 751 static const unsigned int avb0_mdio_pins[] = {
 752         /* AVB0_MDC, AVB0_MDIO */
 753         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
 754 };
 755 static const unsigned int avb0_mdio_mux[] = {
 756         AVB0_MDC_MARK, AVB0_MDIO_MARK,
 757 };
 758 static const unsigned int avb0_rgmii_pins[] = {
 759         /*
 760          * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
 761          * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
 762          */
 763         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
 764         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
 765         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
 766         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
 767         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
 768         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
 769 };
 770 static const unsigned int avb0_rgmii_mux[] = {
 771         AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
 772         AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
 773         AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
 774         AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
 775 };
 776 static const unsigned int avb0_txcrefclk_pins[] = {
 777         /* AVB0_TXCREFCLK */
 778         RCAR_GP_PIN(1, 13),
 779 };
 780 static const unsigned int avb0_txcrefclk_mux[] = {
 781         AVB0_TXCREFCLK_MARK,
 782 };
 783 static const unsigned int avb0_avtp_pps_pins[] = {
 784         /* AVB0_AVTP_PPS */
 785         RCAR_GP_PIN(2, 6),
 786 };
 787 static const unsigned int avb0_avtp_pps_mux[] = {
 788         AVB0_AVTP_PPS_MARK,
 789 };
 790 static const unsigned int avb0_avtp_capture_pins[] = {
 791         /* AVB0_AVTP_CAPTURE */
 792         RCAR_GP_PIN(1, 20),
 793 };
 794 static const unsigned int avb0_avtp_capture_mux[] = {
 795         AVB0_AVTP_CAPTURE_MARK,
 796 };
 797 static const unsigned int avb0_avtp_match_pins[] = {
 798         /* AVB0_AVTP_MATCH */
 799         RCAR_GP_PIN(1, 19),
 800 };
 801 static const unsigned int avb0_avtp_match_mux[] = {
 802         AVB0_AVTP_MATCH_MARK,
 803 };
 804
 805 /* - CANFD Clock ------------------------------------------------------------ */
 806 static const unsigned int canfd_clk_a_pins[] = {
 807         /* CANFD_CLK */
 808         RCAR_GP_PIN(1, 25),
 809 };
 810 static const unsigned int canfd_clk_a_mux[] = {
 811         CANFD_CLK_A_MARK,
 812 };
 813 static const unsigned int canfd_clk_b_pins[] = {
 814         /* CANFD_CLK */
 815         RCAR_GP_PIN(3, 8),
 816 };
 817 static const unsigned int canfd_clk_b_mux[] = {
 818         CANFD_CLK_B_MARK,
 819 };
 820
 821 /* - CANFD0 ----------------------------------------------------------------- */
 822 static const unsigned int canfd0_data_a_pins[] = {
 823         /* TX, RX */
 824         RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
 825 };
 826 static const unsigned int canfd0_data_a_mux[] = {
 827         CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
 828 };
 829 static const unsigned int canfd0_data_b_pins[] = {
 830         /* TX, RX */
 831         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 832 };
 833 static const unsigned int canfd0_data_b_mux[] = {
 834         CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
 835 };
 836
 837 /* - CANFD1 ----------------------------------------------------------------- */
 838 static const unsigned int canfd1_data_pins[] = {
 839         /* TX, RX */
 840         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
 841 };
 842 static const unsigned int canfd1_data_mux[] = {
 843         CANFD1_TX_MARK, CANFD1_RX_MARK,
 844 };
 845
 846 /* - DU --------------------------------------------------------------------- */
 847 static const unsigned int du_rgb666_pins[] = {
 848         /* R[7:2], G[7:2], B[7:2] */
 849         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
 850         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 851         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
 852         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
 853         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
 854         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
 855 };
 856 static const unsigned int du_rgb666_mux[] = {
 857         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
 858         DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
 859         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
 860         DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
 861         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
 862         DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
 863 };
 864 static const unsigned int du_clk_out_pins[] = {
 865         /* DOTCLKOUT */
 866         RCAR_GP_PIN(0, 18),
 867 };
 868 static const unsigned int du_clk_out_mux[] = {
 869         DU_DOTCLKOUT_MARK,
 870 };
 871 static const unsigned int du_sync_pins[] = {
 872         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 873         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 874 };
 875 static const unsigned int du_sync_mux[] = {
 876         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
 877 };
 878 static const unsigned int du_oddf_pins[] = {
 879         /* EXODDF/ODDF/DISP/CDE */
 880         RCAR_GP_PIN(0, 21),
 881 };
 882 static const unsigned int du_oddf_mux[] = {
 883         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
 884 };
 885 static const unsigned int du_cde_pins[] = {
 886         /* CDE */
 887         RCAR_GP_PIN(1, 22),
 888 };
 889 static const unsigned int du_cde_mux[] = {
 890         DU_CDE_MARK,
 891 };
 892 static const unsigned int du_disp_pins[] = {
 893         /* DISP */
 894         RCAR_GP_PIN(1, 21),
 895 };
 896 static const unsigned int du_disp_mux[] = {
 897         DU_DISP_MARK,
 898 };
 899
 900 /* - HSCIF0 ----------------------------------------------------------------- */
 901 static const unsigned int hscif0_data_pins[] = {
 902         /* HRX, HTX */
 903         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
 904 };
 905 static const unsigned int hscif0_data_mux[] = {
 906         HRX0_MARK, HTX0_MARK,
 907 };
 908 static const unsigned int hscif0_clk_pins[] = {
 909         /* HSCK */
 910         RCAR_GP_PIN(0, 0),
 911 };
 912 static const unsigned int hscif0_clk_mux[] = {
 913         HSCK0_MARK,
 914 };
 915 static const unsigned int hscif0_ctrl_pins[] = {
 916         /* HRTS#, HCTS# */
 917         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
 918 };
 919 static const unsigned int hscif0_ctrl_mux[] = {
 920         HRTS0_N_MARK, HCTS0_N_MARK,
 921 };
 922
 923 /* - HSCIF1 ----------------------------------------------------------------- */
 924 static const unsigned int hscif1_data_pins[] = {
 925         /* HRX, HTX */
 926         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
 927 };
 928 static const unsigned int hscif1_data_mux[] = {
 929         HRX1_MARK, HTX1_MARK,
 930 };
 931 static const unsigned int hscif1_clk_pins[] = {
 932         /* HSCK */
 933         RCAR_GP_PIN(2, 7),
 934 };
 935 static const unsigned int hscif1_clk_mux[] = {
 936         HSCK1_MARK,
 937 };
 938 static const unsigned int hscif1_ctrl_pins[] = {
 939         /* HRTS#, HCTS# */
 940         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
 941 };
 942 static const unsigned int hscif1_ctrl_mux[] = {
 943         HRTS1_N_MARK, HCTS1_N_MARK,
 944 };
 945
 946 /* - HSCIF2 ----------------------------------------------------------------- */
 947 static const unsigned int hscif2_data_pins[] = {
 948         /* HRX, HTX */
 949         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
 950 };
 951 static const unsigned int hscif2_data_mux[] = {
 952         HRX2_MARK, HTX2_MARK,
 953 };
 954 static const unsigned int hscif2_clk_pins[] = {
 955         /* HSCK */
 956         RCAR_GP_PIN(2, 12),
 957 };
 958 static const unsigned int hscif2_clk_mux[] = {
 959         HSCK2_MARK,
 960 };
 961 static const unsigned int hscif2_ctrl_pins[] = {
 962         /* HRTS#, HCTS# */
 963         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
 964 };
 965 static const unsigned int hscif2_ctrl_mux[] = {
 966         HRTS2_N_MARK, HCTS2_N_MARK,
 967 };
 968
 969 /* - HSCIF3 ----------------------------------------------------------------- */
 970 static const unsigned int hscif3_data_pins[] = {
 971         /* HRX, HTX */
 972         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
 973 };
 974 static const unsigned int hscif3_data_mux[] = {
 975         HRX3_MARK, HTX3_MARK,
 976 };
 977 static const unsigned int hscif3_clk_pins[] = {
 978         /* HSCK */
 979         RCAR_GP_PIN(2, 0),
 980 };
 981 static const unsigned int hscif3_clk_mux[] = {
 982         HSCK3_MARK,
 983 };
 984 static const unsigned int hscif3_ctrl_pins[] = {
 985         /* HRTS#, HCTS# */
 986         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
 987 };
 988 static const unsigned int hscif3_ctrl_mux[] = {
 989         HRTS3_N_MARK, HCTS3_N_MARK,
 990 };
 991
 992 /* - I2C0 ------------------------------------------------------------------- */
 993 static const unsigned int i2c0_pins[] = {
 994         /* SDA, SCL */
 995         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
 996 };
 997 static const unsigned int i2c0_mux[] = {
 998         SDA0_MARK, SCL0_MARK,
 999 };
1000
1001 /* - I2C1 ------------------------------------------------------------------- */
1002 static const unsigned int i2c1_pins[] = {
1003         /* SDA, SCL */
1004         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1005 };
1006 static const unsigned int i2c1_mux[] = {
1007         SDA1_MARK, SCL1_MARK,
1008 };
1009
1010 /* - I2C2 ------------------------------------------------------------------- */
1011 static const unsigned int i2c2_pins[] = {
1012         /* SDA, SCL */
1013         RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1014 };
1015 static const unsigned int i2c2_mux[] = {
1016         SDA2_MARK, SCL2_MARK,
1017 };
1018
1019 /* - I2C3 ------------------------------------------------------------------- */
1020 static const unsigned int i2c3_a_pins[] = {
1021         /* SDA, SCL */
1022         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1023 };
1024 static const unsigned int i2c3_a_mux[] = {
1025         SDA3_A_MARK, SCL3_A_MARK,
1026 };
1027 static const unsigned int i2c3_b_pins[] = {
1028         /* SDA, SCL */
1029         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1030 };
1031 static const unsigned int i2c3_b_mux[] = {
1032         SDA3_B_MARK, SCL3_B_MARK,
1033 };
1034
1035 /* - I2C4 ------------------------------------------------------------------- */
1036 static const unsigned int i2c4_pins[] = {
1037         /* SDA, SCL */
1038         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1039 };
1040 static const unsigned int i2c4_mux[] = {
1041         SDA4_MARK, SCL4_MARK,
1042 };
1043
1044 /* - INTC-EX ---------------------------------------------------------------- */
1045 static const unsigned int intc_ex_irq0_pins[] = {
1046         /* IRQ0 */
1047         RCAR_GP_PIN(1, 0),
1048 };
1049 static const unsigned int intc_ex_irq0_mux[] = {
1050         IRQ0_MARK,
1051 };
1052 static const unsigned int intc_ex_irq1_pins[] = {
1053         /* IRQ1 */
1054         RCAR_GP_PIN(0, 11),
1055 };
1056 static const unsigned int intc_ex_irq1_mux[] = {
1057         IRQ1_MARK,
1058 };
1059 static const unsigned int intc_ex_irq2_pins[] = {
1060         /* IRQ2 */
1061         RCAR_GP_PIN(0, 12),
1062 };
1063 static const unsigned int intc_ex_irq2_mux[] = {
1064         IRQ2_MARK,
1065 };
1066 static const unsigned int intc_ex_irq3_pins[] = {
1067         /* IRQ3 */
1068         RCAR_GP_PIN(0, 19),
1069 };
1070 static const unsigned int intc_ex_irq3_mux[] = {
1071         IRQ3_MARK,
1072 };
1073 static const unsigned int intc_ex_irq4_pins[] = {
1074         /* IRQ4 */
1075         RCAR_GP_PIN(3, 15),
1076 };
1077 static const unsigned int intc_ex_irq4_mux[] = {
1078         IRQ4_MARK,
1079 };
1080 static const unsigned int intc_ex_irq5_pins[] = {
1081         /* IRQ5 */
1082         RCAR_GP_PIN(3, 16),
1083 };
1084 static const unsigned int intc_ex_irq5_mux[] = {
1085         IRQ5_MARK,
1086 };
1087
1088 /* - MMC -------------------------------------------------------------------- */
1089 static const unsigned int mmc_data1_pins[] = {
1090         /* D0 */
1091         RCAR_GP_PIN(3, 6),
1092 };
1093 static const unsigned int mmc_data1_mux[] = {
1094         MMC_D0_MARK,
1095 };
1096 static const unsigned int mmc_data4_pins[] = {
1097         /* D[0:3] */
1098         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1099         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1100 };
1101 static const unsigned int mmc_data4_mux[] = {
1102         MMC_D0_MARK, MMC_D1_MARK,
1103         MMC_D2_MARK, MMC_D3_MARK,
1104 };
1105 static const unsigned int mmc_data8_pins[] = {
1106         /* D[0:7] */
1107         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1108         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1109         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1110         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1111 };
1112 static const unsigned int mmc_data8_mux[] = {
1113         MMC_D0_MARK, MMC_D1_MARK,
1114         MMC_D2_MARK, MMC_D3_MARK,
1115         MMC_D4_MARK, MMC_D5_MARK,
1116         MMC_D6_MARK, MMC_D7_MARK,
1117 };
1118 static const unsigned int mmc_ctrl_pins[] = {
1119         /* CLK, CMD */
1120         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1121 };
1122 static const unsigned int mmc_ctrl_mux[] = {
1123         MMC_CLK_MARK, MMC_CMD_MARK,
1124 };
1125 static const unsigned int mmc_cd_pins[] = {
1126         /* CD */
1127         RCAR_GP_PIN(3, 16),
1128 };
1129 static const unsigned int mmc_cd_mux[] = {
1130         MMC_CD_MARK,
1131 };
1132 static const unsigned int mmc_wp_pins[] = {
1133         /* WP */
1134         RCAR_GP_PIN(3, 15),
1135 };
1136 static const unsigned int mmc_wp_mux[] = {
1137         MMC_WP_MARK,
1138 };
1139
1140 /* - MSIOF0 ----------------------------------------------------------------- */
1141 static const unsigned int msiof0_clk_pins[] = {
1142         /* SCK */
1143         RCAR_GP_PIN(4, 2),
1144 };
1145 static const unsigned int msiof0_clk_mux[] = {
1146         MSIOF0_SCK_MARK,
1147 };
1148 static const unsigned int msiof0_sync_pins[] = {
1149         /* SYNC */
1150         RCAR_GP_PIN(4, 3),
1151 };
1152 static const unsigned int msiof0_sync_mux[] = {
1153         MSIOF0_SYNC_MARK,
1154 };
1155 static const unsigned int msiof0_ss1_pins[] = {
1156         /* SS1 */
1157         RCAR_GP_PIN(4, 4),
1158 };
1159 static const unsigned int msiof0_ss1_mux[] = {
1160         MSIOF0_SS1_MARK,
1161 };
1162 static const unsigned int msiof0_ss2_pins[] = {
1163         /* SS2 */
1164         RCAR_GP_PIN(4, 5),
1165 };
1166 static const unsigned int msiof0_ss2_mux[] = {
1167         MSIOF0_SS2_MARK,
1168 };
1169 static const unsigned int msiof0_txd_pins[] = {
1170         /* TXD */
1171         RCAR_GP_PIN(4, 1),
1172 };
1173 static const unsigned int msiof0_txd_mux[] = {
1174         MSIOF0_TXD_MARK,
1175 };
1176 static const unsigned int msiof0_rxd_pins[] = {
1177         /* RXD */
1178         RCAR_GP_PIN(4, 0),
1179 };
1180 static const unsigned int msiof0_rxd_mux[] = {
1181         MSIOF0_RXD_MARK,
1182 };
1183
1184 /* - MSIOF1 ----------------------------------------------------------------- */
1185 static const unsigned int msiof1_clk_pins[] = {
1186         /* SCK */
1187         RCAR_GP_PIN(3, 2),
1188 };
1189 static const unsigned int msiof1_clk_mux[] = {
1190         MSIOF1_SCK_MARK,
1191 };
1192 static const unsigned int msiof1_sync_pins[] = {
1193         /* SYNC */
1194         RCAR_GP_PIN(3, 3),
1195 };
1196 static const unsigned int msiof1_sync_mux[] = {
1197         MSIOF1_SYNC_MARK,
1198 };
1199 static const unsigned int msiof1_ss1_pins[] = {
1200         /* SS1 */
1201         RCAR_GP_PIN(3, 4),
1202 };
1203 static const unsigned int msiof1_ss1_mux[] = {
1204         MSIOF1_SS1_MARK,
1205 };
1206 static const unsigned int msiof1_ss2_pins[] = {
1207         /* SS2 */
1208         RCAR_GP_PIN(3, 5),
1209 };
1210 static const unsigned int msiof1_ss2_mux[] = {
1211         MSIOF1_SS2_MARK,
1212 };
1213 static const unsigned int msiof1_txd_pins[] = {
1214         /* TXD */
1215         RCAR_GP_PIN(3, 1),
1216 };
1217 static const unsigned int msiof1_txd_mux[] = {
1218         MSIOF1_TXD_MARK,
1219 };
1220 static const unsigned int msiof1_rxd_pins[] = {
1221         /* RXD */
1222         RCAR_GP_PIN(3, 0),
1223 };
1224 static const unsigned int msiof1_rxd_mux[] = {
1225         MSIOF1_RXD_MARK,
1226 };
1227
1228 /* - MSIOF2 ----------------------------------------------------------------- */
1229 static const unsigned int msiof2_clk_pins[] = {
1230         /* SCK */
1231         RCAR_GP_PIN(2, 0),
1232 };
1233 static const unsigned int msiof2_clk_mux[] = {
1234         MSIOF2_SCK_MARK,
1235 };
1236 static const unsigned int msiof2_sync_pins[] = {
1237         /* SYNC */
1238         RCAR_GP_PIN(2, 3),
1239 };
1240 static const unsigned int msiof2_sync_mux[] = {
1241         MSIOF2_SYNC_MARK,
1242 };
1243 static const unsigned int msiof2_ss1_pins[] = {
1244         /* SS1 */
1245         RCAR_GP_PIN(2, 4),
1246 };
1247 static const unsigned int msiof2_ss1_mux[] = {
1248         MSIOF2_SS1_MARK,
1249 };
1250 static const unsigned int msiof2_ss2_pins[] = {
1251         /* SS2 */
1252         RCAR_GP_PIN(2, 5),
1253 };
1254 static const unsigned int msiof2_ss2_mux[] = {
1255         MSIOF2_SS2_MARK,
1256 };
1257 static const unsigned int msiof2_txd_pins[] = {
1258         /* TXD */
1259         RCAR_GP_PIN(2, 2),
1260 };
1261 static const unsigned int msiof2_txd_mux[] = {
1262         MSIOF2_TXD_MARK,
1263 };
1264 static const unsigned int msiof2_rxd_pins[] = {
1265         /* RXD */
1266         RCAR_GP_PIN(2, 1),
1267 };
1268 static const unsigned int msiof2_rxd_mux[] = {
1269         MSIOF2_RXD_MARK,
1270 };
1271
1272 /* - MSIOF3 ----------------------------------------------------------------- */
1273 static const unsigned int msiof3_clk_pins[] = {
1274         /* SCK */
1275         RCAR_GP_PIN(0, 20),
1276 };
1277 static const unsigned int msiof3_clk_mux[] = {
1278         MSIOF3_SCK_MARK,
1279 };
1280 static const unsigned int msiof3_sync_pins[] = {
1281         /* SYNC */
1282         RCAR_GP_PIN(0, 21),
1283 };
1284 static const unsigned int msiof3_sync_mux[] = {
1285         MSIOF3_SYNC_MARK,
1286 };
1287 static const unsigned int msiof3_ss1_pins[] = {
1288         /* SS1 */
1289         RCAR_GP_PIN(0, 6),
1290 };
1291 static const unsigned int msiof3_ss1_mux[] = {
1292         MSIOF3_SS1_MARK,
1293 };
1294 static const unsigned int msiof3_ss2_pins[] = {
1295         /* SS2 */
1296         RCAR_GP_PIN(0, 7),
1297 };
1298 static const unsigned int msiof3_ss2_mux[] = {
1299         MSIOF3_SS2_MARK,
1300 };
1301 static const unsigned int msiof3_txd_pins[] = {
1302         /* TXD */
1303         RCAR_GP_PIN(0, 5),
1304 };
1305 static const unsigned int msiof3_txd_mux[] = {
1306         MSIOF3_TXD_MARK,
1307 };
1308 static const unsigned int msiof3_rxd_pins[] = {
1309         /* RXD */
1310         RCAR_GP_PIN(0, 4),
1311 };
1312 static const unsigned int msiof3_rxd_mux[] = {
1313         MSIOF3_RXD_MARK,
1314 };
1315
1316 /* - PWM0 ------------------------------------------------------------------- */
1317 static const unsigned int pwm0_a_pins[] = {
1318         RCAR_GP_PIN(2, 12),
1319 };
1320 static const unsigned int pwm0_a_mux[] = {
1321         PWM0_A_MARK,
1322 };
1323 static const unsigned int pwm0_b_pins[] = {
1324         RCAR_GP_PIN(1, 21),
1325 };
1326 static const unsigned int pwm0_b_mux[] = {
1327         PWM0_B_MARK,
1328 };
1329
1330 /* - PWM1 ------------------------------------------------------------------- */
1331 static const unsigned int pwm1_a_pins[] = {
1332         RCAR_GP_PIN(2, 13),
1333 };
1334 static const unsigned int pwm1_a_mux[] = {
1335         PWM1_A_MARK,
1336 };
1337 static const unsigned int pwm1_b_pins[] = {
1338         RCAR_GP_PIN(1, 22),
1339 };
1340 static const unsigned int pwm1_b_mux[] = {
1341         PWM1_B_MARK,
1342 };
1343
1344 /* - PWM2 ------------------------------------------------------------------- */
1345 static const unsigned int pwm2_a_pins[] = {
1346         RCAR_GP_PIN(2, 14),
1347 };
1348 static const unsigned int pwm2_a_mux[] = {
1349         PWM2_A_MARK,
1350 };
1351 static const unsigned int pwm2_b_pins[] = {
1352         RCAR_GP_PIN(1, 23),
1353 };
1354 static const unsigned int pwm2_b_mux[] = {
1355         PWM2_B_MARK,
1356 };
1357
1358 /* - PWM3 ------------------------------------------------------------------- */
1359 static const unsigned int pwm3_a_pins[] = {
1360         RCAR_GP_PIN(2, 15),
1361 };
1362 static const unsigned int pwm3_a_mux[] = {
1363         PWM3_A_MARK,
1364 };
1365 static const unsigned int pwm3_b_pins[] = {
1366         RCAR_GP_PIN(1, 24),
1367 };
1368 static const unsigned int pwm3_b_mux[] = {
1369         PWM3_B_MARK,
1370 };
1371
1372 /* - PWM4 ------------------------------------------------------------------- */
1373 static const unsigned int pwm4_a_pins[] = {
1374         RCAR_GP_PIN(2, 16),
1375 };
1376 static const unsigned int pwm4_a_mux[] = {
1377         PWM4_A_MARK,
1378 };
1379 static const unsigned int pwm4_b_pins[] = {
1380         RCAR_GP_PIN(1, 25),
1381 };
1382 static const unsigned int pwm4_b_mux[] = {
1383         PWM4_B_MARK,
1384 };
1385
1386 /* - SCIF Clock ------------------------------------------------------------- */
1387 static const unsigned int scif_clk_a_pins[] = {
1388         /* SCIF_CLK */
1389         RCAR_GP_PIN(0, 18),
1390 };
1391 static const unsigned int scif_clk_a_mux[] = {
1392         SCIF_CLK_A_MARK,
1393 };
1394 static const unsigned int scif_clk_b_pins[] = {
1395         /* SCIF_CLK */
1396         RCAR_GP_PIN(1, 25),
1397 };
1398 static const unsigned int scif_clk_b_mux[] = {
1399         SCIF_CLK_B_MARK,
1400 };
1401
1402 /* - SCIF0 ------------------------------------------------------------------ */
1403 static const unsigned int scif0_data_pins[] = {
1404         /* RX, TX */
1405         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1406 };
1407 static const unsigned int scif0_data_mux[] = {
1408         RX0_MARK, TX0_MARK,
1409 };
1410 static const unsigned int scif0_clk_pins[] = {
1411         /* SCK */
1412         RCAR_GP_PIN(4, 1),
1413 };
1414 static const unsigned int scif0_clk_mux[] = {
1415         SCK0_MARK,
1416 };
1417 static const unsigned int scif0_ctrl_pins[] = {
1418         /* RTS#, CTS# */
1419         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1420 };
1421 static const unsigned int scif0_ctrl_mux[] = {
1422         RTS0_N_TANS_MARK, CTS0_N_MARK,
1423 };
1424
1425 /* - SCIF1 ------------------------------------------------------------------ */
1426 static const unsigned int scif1_data_a_pins[] = {
1427         /* RX, TX */
1428         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1429 };
1430 static const unsigned int scif1_data_a_mux[] = {
1431         RX1_A_MARK, TX1_A_MARK,
1432 };
1433 static const unsigned int scif1_clk_pins[] = {
1434         /* SCK */
1435         RCAR_GP_PIN(2, 5),
1436 };
1437 static const unsigned int scif1_clk_mux[] = {
1438         SCK1_MARK,
1439 };
1440 static const unsigned int scif1_ctrl_pins[] = {
1441         /* RTS#, CTS# */
1442         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1443 };
1444 static const unsigned int scif1_ctrl_mux[] = {
1445         RTS1_N_TANS_MARK, CTS1_N_MARK,
1446 };
1447 static const unsigned int scif1_data_b_pins[] = {
1448         /* RX, TX */
1449         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1450 };
1451 static const unsigned int scif1_data_b_mux[] = {
1452         RX1_B_MARK, TX1_B_MARK,
1453 };
1454
1455 /* - SCIF3 ------------------------------------------------------------------ */
1456 static const unsigned int scif3_data_pins[] = {
1457         /* RX, TX */
1458         RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1459 };
1460 static const unsigned int scif3_data_mux[] = {
1461         RX3_MARK, TX3_MARK,
1462 };
1463 static const unsigned int scif3_clk_pins[] = {
1464         /* SCK */
1465         RCAR_GP_PIN(2, 0),
1466 };
1467 static const unsigned int scif3_clk_mux[] = {
1468         SCK3_MARK,
1469 };
1470 static const unsigned int scif3_ctrl_pins[] = {
1471         /* RTS#, CTS# */
1472         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1473 };
1474 static const unsigned int scif3_ctrl_mux[] = {
1475         RTS3_N_TANS_MARK, CTS3_N_MARK,
1476 };
1477
1478 /* - SCIF4 ------------------------------------------------------------------ */
1479 static const unsigned int scif4_data_pins[] = {
1480         /* RX, TX */
1481         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1482 };
1483 static const unsigned int scif4_data_mux[] = {
1484         RX4_MARK, TX4_MARK,
1485 };
1486 static const unsigned int scif4_clk_pins[] = {
1487         /* SCK */
1488         RCAR_GP_PIN(3, 9),
1489 };
1490 static const unsigned int scif4_clk_mux[] = {
1491         SCK4_MARK,
1492 };
1493 static const unsigned int scif4_ctrl_pins[] = {
1494         /* RTS#, CTS# */
1495         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1496 };
1497 static const unsigned int scif4_ctrl_mux[] = {
1498         RTS4_N_TANS_MARK, CTS4_N_MARK,
1499 };
1500
1501 /* - TMU -------------------------------------------------------------------- */
1502 static const unsigned int tmu_tclk1_a_pins[] = {
1503         /* TCLK1 */
1504         RCAR_GP_PIN(4, 4),
1505 };
1506 static const unsigned int tmu_tclk1_a_mux[] = {
1507         TCLK1_A_MARK,
1508 };
1509 static const unsigned int tmu_tclk1_b_pins[] = {
1510         /* TCLK1 */
1511         RCAR_GP_PIN(1, 23),
1512 };
1513 static const unsigned int tmu_tclk1_b_mux[] = {
1514         TCLK1_B_MARK,
1515 };
1516 static const unsigned int tmu_tclk2_a_pins[] = {
1517         /* TCLK2 */
1518         RCAR_GP_PIN(4, 5),
1519 };
1520 static const unsigned int tmu_tclk2_a_mux[] = {
1521         TCLK2_A_MARK,
1522 };
1523 static const unsigned int tmu_tclk2_b_pins[] = {
1524         /* TCLK2 */
1525         RCAR_GP_PIN(1, 24),
1526 };
1527 static const unsigned int tmu_tclk2_b_mux[] = {
1528         TCLK2_B_MARK,
1529 };
1530
1531 /* - VIN0 ------------------------------------------------------------------- */
1532 static const unsigned int vin0_data8_pins[] = {
1533         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1534         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1535         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1536         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1537 };
1538 static const unsigned int vin0_data8_mux[] = {
1539         VI0_DATA0_MARK, VI0_DATA1_MARK,
1540         VI0_DATA2_MARK, VI0_DATA3_MARK,
1541         VI0_DATA4_MARK, VI0_DATA5_MARK,
1542         VI0_DATA6_MARK, VI0_DATA7_MARK,
1543 };
1544 static const unsigned int vin0_data10_pins[] = {
1545         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1546         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1547         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1548         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1549         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1550 };
1551 static const unsigned int vin0_data10_mux[] = {
1552         VI0_DATA0_MARK, VI0_DATA1_MARK,
1553         VI0_DATA2_MARK, VI0_DATA3_MARK,
1554         VI0_DATA4_MARK, VI0_DATA5_MARK,
1555         VI0_DATA6_MARK, VI0_DATA7_MARK,
1556         VI0_DATA8_MARK,  VI0_DATA9_MARK,
1557 };
1558 static const unsigned int vin0_data12_pins[] = {
1559         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1560         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1561         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1562         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1563         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1564         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1565 };
1566 static const unsigned int vin0_data12_mux[] = {
1567         VI0_DATA0_MARK, VI0_DATA1_MARK,
1568         VI0_DATA2_MARK, VI0_DATA3_MARK,
1569         VI0_DATA4_MARK, VI0_DATA5_MARK,
1570         VI0_DATA6_MARK, VI0_DATA7_MARK,
1571         VI0_DATA8_MARK,  VI0_DATA9_MARK,
1572         VI0_DATA10_MARK, VI0_DATA11_MARK,
1573 };
1574 static const unsigned int vin0_sync_pins[] = {
1575         /* HSYNC#, VSYNC# */
1576         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1577 };
1578 static const unsigned int vin0_sync_mux[] = {
1579         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1580 };
1581 static const unsigned int vin0_field_pins[] = {
1582         /* FIELD */
1583         RCAR_GP_PIN(2, 16),
1584 };
1585 static const unsigned int vin0_field_mux[] = {
1586         VI0_FIELD_MARK,
1587 };
1588 static const unsigned int vin0_clkenb_pins[] = {
1589         /* CLKENB */
1590         RCAR_GP_PIN(2, 1),
1591 };
1592 static const unsigned int vin0_clkenb_mux[] = {
1593         VI0_CLKENB_MARK,
1594 };
1595 static const unsigned int vin0_clk_pins[] = {
1596         /* CLK */
1597         RCAR_GP_PIN(2, 0),
1598 };
1599 static const unsigned int vin0_clk_mux[] = {
1600         VI0_CLK_MARK,
1601 };
1602
1603 /* - VIN1 ------------------------------------------------------------------- */
1604 static const unsigned int vin1_data8_pins[] = {
1605         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1606         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1607         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1608         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1609 };
1610 static const unsigned int vin1_data8_mux[] = {
1611         VI1_DATA0_MARK, VI1_DATA1_MARK,
1612         VI1_DATA2_MARK, VI1_DATA3_MARK,
1613         VI1_DATA4_MARK, VI1_DATA5_MARK,
1614         VI1_DATA6_MARK, VI1_DATA7_MARK,
1615 };
1616 static const unsigned int vin1_data10_pins[] = {
1617         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1618         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1619         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1620         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1621         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1622 };
1623 static const unsigned int vin1_data10_mux[] = {
1624         VI1_DATA0_MARK, VI1_DATA1_MARK,
1625         VI1_DATA2_MARK, VI1_DATA3_MARK,
1626         VI1_DATA4_MARK, VI1_DATA5_MARK,
1627         VI1_DATA6_MARK, VI1_DATA7_MARK,
1628         VI1_DATA8_MARK,  VI1_DATA9_MARK,
1629 };
1630 static const unsigned int vin1_data12_pins[] = {
1631         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1632         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1633         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1634         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1635         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1636         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1637 };
1638 static const unsigned int vin1_data12_mux[] = {
1639         VI1_DATA0_MARK, VI1_DATA1_MARK,
1640         VI1_DATA2_MARK, VI1_DATA3_MARK,
1641         VI1_DATA4_MARK, VI1_DATA5_MARK,
1642         VI1_DATA6_MARK, VI1_DATA7_MARK,
1643         VI1_DATA8_MARK,  VI1_DATA9_MARK,
1644         VI1_DATA10_MARK, VI1_DATA11_MARK,
1645 };
1646 static const unsigned int vin1_sync_pins[] = {
1647         /* HSYNC#, VSYNC# */
1648         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1649 };
1650 static const unsigned int vin1_sync_mux[] = {
1651         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1652 };
1653 static const unsigned int vin1_field_pins[] = {
1654         RCAR_GP_PIN(3, 16),
1655 };
1656 static const unsigned int vin1_field_mux[] = {
1657         /* FIELD */
1658         VI1_FIELD_MARK,
1659 };
1660 static const unsigned int vin1_clkenb_pins[] = {
1661         RCAR_GP_PIN(3, 1),
1662 };
1663 static const unsigned int vin1_clkenb_mux[] = {
1664         /* CLKENB */
1665         VI1_CLKENB_MARK,
1666 };
1667 static const unsigned int vin1_clk_pins[] = {
1668         RCAR_GP_PIN(3, 0),
1669 };
1670 static const unsigned int vin1_clk_mux[] = {
1671         /* CLK */
1672         VI1_CLK_MARK,
1673 };
1674
1675 static const struct sh_pfc_pin_group pinmux_groups[] = {
1676         SH_PFC_PIN_GROUP(avb0_link),
1677         SH_PFC_PIN_GROUP(avb0_magic),
1678         SH_PFC_PIN_GROUP(avb0_phy_int),
1679         SH_PFC_PIN_GROUP(avb0_mdio),
1680         SH_PFC_PIN_GROUP(avb0_rgmii),
1681         SH_PFC_PIN_GROUP(avb0_txcrefclk),
1682         SH_PFC_PIN_GROUP(avb0_avtp_pps),
1683         SH_PFC_PIN_GROUP(avb0_avtp_capture),
1684         SH_PFC_PIN_GROUP(avb0_avtp_match),
1685         SH_PFC_PIN_GROUP(canfd_clk_a),
1686         SH_PFC_PIN_GROUP(canfd_clk_b),
1687         SH_PFC_PIN_GROUP(canfd0_data_a),
1688         SH_PFC_PIN_GROUP(canfd0_data_b),
1689         SH_PFC_PIN_GROUP(canfd1_data),
1690         SH_PFC_PIN_GROUP(du_rgb666),
1691         SH_PFC_PIN_GROUP(du_clk_out),
1692         SH_PFC_PIN_GROUP(du_sync),
1693         SH_PFC_PIN_GROUP(du_oddf),
1694         SH_PFC_PIN_GROUP(du_cde),
1695         SH_PFC_PIN_GROUP(du_disp),
1696         SH_PFC_PIN_GROUP(hscif0_data),
1697         SH_PFC_PIN_GROUP(hscif0_clk),
1698         SH_PFC_PIN_GROUP(hscif0_ctrl),
1699         SH_PFC_PIN_GROUP(hscif1_data),
1700         SH_PFC_PIN_GROUP(hscif1_clk),
1701         SH_PFC_PIN_GROUP(hscif1_ctrl),
1702         SH_PFC_PIN_GROUP(hscif2_data),
1703         SH_PFC_PIN_GROUP(hscif2_clk),
1704         SH_PFC_PIN_GROUP(hscif2_ctrl),
1705         SH_PFC_PIN_GROUP(hscif3_data),
1706         SH_PFC_PIN_GROUP(hscif3_clk),
1707         SH_PFC_PIN_GROUP(hscif3_ctrl),
1708         SH_PFC_PIN_GROUP(i2c0),
1709         SH_PFC_PIN_GROUP(i2c1),
1710         SH_PFC_PIN_GROUP(i2c2),
1711         SH_PFC_PIN_GROUP(i2c3_a),
1712         SH_PFC_PIN_GROUP(i2c3_b),
1713         SH_PFC_PIN_GROUP(i2c4),
1714         SH_PFC_PIN_GROUP(intc_ex_irq0),
1715         SH_PFC_PIN_GROUP(intc_ex_irq1),
1716         SH_PFC_PIN_GROUP(intc_ex_irq2),
1717         SH_PFC_PIN_GROUP(intc_ex_irq3),
1718         SH_PFC_PIN_GROUP(intc_ex_irq4),
1719         SH_PFC_PIN_GROUP(intc_ex_irq5),
1720         SH_PFC_PIN_GROUP(mmc_data1),
1721         SH_PFC_PIN_GROUP(mmc_data4),
1722         SH_PFC_PIN_GROUP(mmc_data8),
1723         SH_PFC_PIN_GROUP(mmc_ctrl),
1724         SH_PFC_PIN_GROUP(mmc_cd),
1725         SH_PFC_PIN_GROUP(mmc_wp),
1726         SH_PFC_PIN_GROUP(msiof0_clk),
1727         SH_PFC_PIN_GROUP(msiof0_sync),
1728         SH_PFC_PIN_GROUP(msiof0_ss1),
1729         SH_PFC_PIN_GROUP(msiof0_ss2),
1730         SH_PFC_PIN_GROUP(msiof0_txd),
1731         SH_PFC_PIN_GROUP(msiof0_rxd),
1732         SH_PFC_PIN_GROUP(msiof1_clk),
1733         SH_PFC_PIN_GROUP(msiof1_sync),
1734         SH_PFC_PIN_GROUP(msiof1_ss1),
1735         SH_PFC_PIN_GROUP(msiof1_ss2),
1736         SH_PFC_PIN_GROUP(msiof1_txd),
1737         SH_PFC_PIN_GROUP(msiof1_rxd),
1738         SH_PFC_PIN_GROUP(msiof2_clk),
1739         SH_PFC_PIN_GROUP(msiof2_sync),
1740         SH_PFC_PIN_GROUP(msiof2_ss1),
1741         SH_PFC_PIN_GROUP(msiof2_ss2),
1742         SH_PFC_PIN_GROUP(msiof2_txd),
1743         SH_PFC_PIN_GROUP(msiof2_rxd),
1744         SH_PFC_PIN_GROUP(msiof3_clk),
1745         SH_PFC_PIN_GROUP(msiof3_sync),
1746         SH_PFC_PIN_GROUP(msiof3_ss1),
1747         SH_PFC_PIN_GROUP(msiof3_ss2),
1748         SH_PFC_PIN_GROUP(msiof3_txd),
1749         SH_PFC_PIN_GROUP(msiof3_rxd),
1750         SH_PFC_PIN_GROUP(pwm0_a),
1751         SH_PFC_PIN_GROUP(pwm0_b),
1752         SH_PFC_PIN_GROUP(pwm1_a),
1753         SH_PFC_PIN_GROUP(pwm1_b),
1754         SH_PFC_PIN_GROUP(pwm2_a),
1755         SH_PFC_PIN_GROUP(pwm2_b),
1756         SH_PFC_PIN_GROUP(pwm3_a),
1757         SH_PFC_PIN_GROUP(pwm3_b),
1758         SH_PFC_PIN_GROUP(pwm4_a),
1759         SH_PFC_PIN_GROUP(pwm4_b),
1760         SH_PFC_PIN_GROUP(scif_clk_a),
1761         SH_PFC_PIN_GROUP(scif_clk_b),
1762         SH_PFC_PIN_GROUP(scif0_data),
1763         SH_PFC_PIN_GROUP(scif0_clk),
1764         SH_PFC_PIN_GROUP(scif0_ctrl),
1765         SH_PFC_PIN_GROUP(scif1_data_a),
1766         SH_PFC_PIN_GROUP(scif1_clk),
1767         SH_PFC_PIN_GROUP(scif1_ctrl),
1768         SH_PFC_PIN_GROUP(scif1_data_b),
1769         SH_PFC_PIN_GROUP(scif3_data),
1770         SH_PFC_PIN_GROUP(scif3_clk),
1771         SH_PFC_PIN_GROUP(scif3_ctrl),
1772         SH_PFC_PIN_GROUP(scif4_data),
1773         SH_PFC_PIN_GROUP(scif4_clk),
1774         SH_PFC_PIN_GROUP(scif4_ctrl),
1775         SH_PFC_PIN_GROUP(tmu_tclk1_a),
1776         SH_PFC_PIN_GROUP(tmu_tclk1_b),
1777         SH_PFC_PIN_GROUP(tmu_tclk2_a),
1778         SH_PFC_PIN_GROUP(tmu_tclk2_b),
1779         SH_PFC_PIN_GROUP(vin0_data8),
1780         SH_PFC_PIN_GROUP(vin0_data10),
1781         SH_PFC_PIN_GROUP(vin0_data12),
1782         SH_PFC_PIN_GROUP(vin0_sync),
1783         SH_PFC_PIN_GROUP(vin0_field),
1784         SH_PFC_PIN_GROUP(vin0_clkenb),
1785         SH_PFC_PIN_GROUP(vin0_clk),
1786         SH_PFC_PIN_GROUP(vin1_data8),
1787         SH_PFC_PIN_GROUP(vin1_data10),
1788         SH_PFC_PIN_GROUP(vin1_data12),
1789         SH_PFC_PIN_GROUP(vin1_sync),
1790         SH_PFC_PIN_GROUP(vin1_field),
1791         SH_PFC_PIN_GROUP(vin1_clkenb),
1792         SH_PFC_PIN_GROUP(vin1_clk),
1793 };
1794
1795 static const char * const avb0_groups[] = {
1796         "avb0_link",
1797         "avb0_magic",
1798         "avb0_phy_int",
1799         "avb0_mdio",
1800         "avb0_rgmii",
1801         "avb0_txcrefclk",
1802         "avb0_avtp_pps",
1803         "avb0_avtp_capture",
1804         "avb0_avtp_match",
1805 };
1806
1807 static const char * const canfd_clk_groups[] = {
1808         "canfd_clk_a",
1809         "canfd_clk_b",
1810 };
1811
1812 static const char * const canfd0_groups[] = {
1813         "canfd0_data_a",
1814         "canfd0_data_b",
1815 };
1816
1817 static const char * const canfd1_groups[] = {
1818         "canfd1_data",
1819 };
1820
1821 static const char * const du_groups[] = {
1822         "du_rgb666",
1823         "du_clk_out",
1824         "du_sync",
1825         "du_oddf",
1826         "du_cde",
1827         "du_disp",
1828 };
1829
1830 static const char * const hscif0_groups[] = {
1831         "hscif0_data",
1832         "hscif0_clk",
1833         "hscif0_ctrl",
1834 };
1835
1836 static const char * const hscif1_groups[] = {
1837         "hscif1_data",
1838         "hscif1_clk",
1839         "hscif1_ctrl",
1840 };
1841
1842 static const char * const hscif2_groups[] = {
1843         "hscif2_data",
1844         "hscif2_clk",
1845         "hscif2_ctrl",
1846 };
1847
1848 static const char * const hscif3_groups[] = {
1849         "hscif3_data",
1850         "hscif3_clk",
1851         "hscif3_ctrl",
1852 };
1853
1854 static const char * const i2c0_groups[] = {
1855         "i2c0",
1856 };
1857
1858 static const char * const i2c1_groups[] = {
1859         "i2c1",
1860 };
1861
1862 static const char * const i2c2_groups[] = {
1863         "i2c2",
1864 };
1865
1866 static const char * const i2c3_groups[] = {
1867         "i2c3_a",
1868         "i2c3_b",
1869 };
1870
1871 static const char * const i2c4_groups[] = {
1872         "i2c4",
1873 };
1874
1875 static const char * const intc_ex_groups[] = {
1876         "intc_ex_irq0",
1877         "intc_ex_irq1",
1878         "intc_ex_irq2",
1879         "intc_ex_irq3",
1880         "intc_ex_irq4",
1881         "intc_ex_irq5",
1882 };
1883
1884 static const char * const mmc_groups[] = {
1885         "mmc_data1",
1886         "mmc_data4",
1887         "mmc_data8",
1888         "mmc_ctrl",
1889         "mmc_cd",
1890         "mmc_wp",
1891 };
1892
1893 static const char * const msiof0_groups[] = {
1894         "msiof0_clk",
1895         "msiof0_sync",
1896         "msiof0_ss1",
1897         "msiof0_ss2",
1898         "msiof0_txd",
1899         "msiof0_rxd",
1900 };
1901
1902 static const char * const msiof1_groups[] = {
1903         "msiof1_clk",
1904         "msiof1_sync",
1905         "msiof1_ss1",
1906         "msiof1_ss2",
1907         "msiof1_txd",
1908         "msiof1_rxd",
1909 };
1910
1911 static const char * const msiof2_groups[] = {
1912         "msiof2_clk",
1913         "msiof2_sync",
1914         "msiof2_ss1",
1915         "msiof2_ss2",
1916         "msiof2_txd",
1917         "msiof2_rxd",
1918 };
1919
1920 static const char * const msiof3_groups[] = {
1921         "msiof3_clk",
1922         "msiof3_sync",
1923         "msiof3_ss1",
1924         "msiof3_ss2",
1925         "msiof3_txd",
1926         "msiof3_rxd",
1927 };
1928
1929 static const char * const pwm0_groups[] = {
1930         "pwm0_a",
1931         "pwm0_b",
1932 };
1933
1934 static const char * const pwm1_groups[] = {
1935         "pwm1_a",
1936         "pwm1_b",
1937 };
1938
1939 static const char * const pwm2_groups[] = {
1940         "pwm2_a",
1941         "pwm2_b",
1942 };
1943
1944 static const char * const pwm3_groups[] = {
1945         "pwm3_a",
1946         "pwm3_b",
1947 };
1948
1949 static const char * const pwm4_groups[] = {
1950         "pwm4_a",
1951         "pwm4_b",
1952 };
1953
1954 static const char * const scif_clk_groups[] = {
1955         "scif_clk_a",
1956         "scif_clk_b",
1957 };
1958
1959 static const char * const scif0_groups[] = {
1960         "scif0_data",
1961         "scif0_clk",
1962         "scif0_ctrl",
1963 };
1964
1965 static const char * const scif1_groups[] = {
1966         "scif1_data_a",
1967         "scif1_clk",
1968         "scif1_ctrl",
1969         "scif1_data_b",
1970 };
1971
1972 static const char * const scif3_groups[] = {
1973         "scif3_data",
1974         "scif3_clk",
1975         "scif3_ctrl",
1976 };
1977
1978 static const char * const scif4_groups[] = {
1979         "scif4_data",
1980         "scif4_clk",
1981         "scif4_ctrl",
1982 };
1983
1984 static const char * const tmu_groups[] = {
1985         "tmu_tclk1_a",
1986         "tmu_tclk1_b",
1987         "tmu_tclk2_a",
1988         "tmu_tclk2_b",
1989 };
1990
1991 static const char * const vin0_groups[] = {
1992         "vin0_data8",
1993         "vin0_data10",
1994         "vin0_data12",
1995         "vin0_sync",
1996         "vin0_field",
1997         "vin0_clkenb",
1998         "vin0_clk",
1999 };
2000
2001 static const char * const vin1_groups[] = {
2002         "vin1_data8",
2003         "vin1_data10",
2004         "vin1_data12",
2005         "vin1_sync",
2006         "vin1_field",
2007         "vin1_clkenb",
2008         "vin1_clk",
2009 };
2010
2011 static const struct sh_pfc_function pinmux_functions[] = {
2012         SH_PFC_FUNCTION(avb0),
2013         SH_PFC_FUNCTION(canfd_clk),
2014         SH_PFC_FUNCTION(canfd0),
2015         SH_PFC_FUNCTION(canfd1),
2016         SH_PFC_FUNCTION(du),
2017         SH_PFC_FUNCTION(hscif0),
2018         SH_PFC_FUNCTION(hscif1),
2019         SH_PFC_FUNCTION(hscif2),
2020         SH_PFC_FUNCTION(hscif3),
2021         SH_PFC_FUNCTION(i2c0),
2022         SH_PFC_FUNCTION(i2c1),
2023         SH_PFC_FUNCTION(i2c2),
2024         SH_PFC_FUNCTION(i2c3),
2025         SH_PFC_FUNCTION(i2c4),
2026         SH_PFC_FUNCTION(intc_ex),
2027         SH_PFC_FUNCTION(mmc),
2028         SH_PFC_FUNCTION(msiof0),
2029         SH_PFC_FUNCTION(msiof1),
2030         SH_PFC_FUNCTION(msiof2),
2031         SH_PFC_FUNCTION(msiof3),
2032         SH_PFC_FUNCTION(pwm0),
2033         SH_PFC_FUNCTION(pwm1),
2034         SH_PFC_FUNCTION(pwm2),
2035         SH_PFC_FUNCTION(pwm3),
2036         SH_PFC_FUNCTION(pwm4),
2037         SH_PFC_FUNCTION(scif_clk),
2038         SH_PFC_FUNCTION(scif0),
2039         SH_PFC_FUNCTION(scif1),
2040         SH_PFC_FUNCTION(scif3),
2041         SH_PFC_FUNCTION(scif4),
2042         SH_PFC_FUNCTION(tmu),
2043         SH_PFC_FUNCTION(vin0),
2044         SH_PFC_FUNCTION(vin1),
2045 };
2046
2047 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2048 #define F_(x, y)        FN_##y
2049 #define FM(x)           FN_##x
2050         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2051                 0, 0,
2052                 0, 0,
2053                 0, 0,
2054                 0, 0,
2055                 0, 0,
2056                 0, 0,
2057                 0, 0,
2058                 0, 0,
2059                 0, 0,
2060                 0, 0,
2061                 GP_0_21_FN,     GPSR0_21,
2062                 GP_0_20_FN,     GPSR0_20,
2063                 GP_0_19_FN,     GPSR0_19,
2064                 GP_0_18_FN,     GPSR0_18,
2065                 GP_0_17_FN,     GPSR0_17,
2066                 GP_0_16_FN,     GPSR0_16,
2067                 GP_0_15_FN,     GPSR0_15,
2068                 GP_0_14_FN,     GPSR0_14,
2069                 GP_0_13_FN,     GPSR0_13,
2070                 GP_0_12_FN,     GPSR0_12,
2071                 GP_0_11_FN,     GPSR0_11,
2072                 GP_0_10_FN,     GPSR0_10,
2073                 GP_0_9_FN,      GPSR0_9,
2074                 GP_0_8_FN,      GPSR0_8,
2075                 GP_0_7_FN,      GPSR0_7,
2076                 GP_0_6_FN,      GPSR0_6,
2077                 GP_0_5_FN,      GPSR0_5,
2078                 GP_0_4_FN,      GPSR0_4,
2079                 GP_0_3_FN,      GPSR0_3,
2080                 GP_0_2_FN,      GPSR0_2,
2081                 GP_0_1_FN,      GPSR0_1,
2082                 GP_0_0_FN,      GPSR0_0, }
2083         },
2084         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2085                 0, 0,
2086                 0, 0,
2087                 0, 0,
2088                 0, 0,
2089                 GP_1_27_FN,     GPSR1_27,
2090                 GP_1_26_FN,     GPSR1_26,
2091                 GP_1_25_FN,     GPSR1_25,
2092                 GP_1_24_FN,     GPSR1_24,
2093                 GP_1_23_FN,     GPSR1_23,
2094                 GP_1_22_FN,     GPSR1_22,
2095                 GP_1_21_FN,     GPSR1_21,
2096                 GP_1_20_FN,     GPSR1_20,
2097                 GP_1_19_FN,     GPSR1_19,
2098                 GP_1_18_FN,     GPSR1_18,
2099                 GP_1_17_FN,     GPSR1_17,
2100                 GP_1_16_FN,     GPSR1_16,
2101                 GP_1_15_FN,     GPSR1_15,
2102                 GP_1_14_FN,     GPSR1_14,
2103                 GP_1_13_FN,     GPSR1_13,
2104                 GP_1_12_FN,     GPSR1_12,
2105                 GP_1_11_FN,     GPSR1_11,
2106                 GP_1_10_FN,     GPSR1_10,
2107                 GP_1_9_FN,      GPSR1_9,
2108                 GP_1_8_FN,      GPSR1_8,
2109                 GP_1_7_FN,      GPSR1_7,
2110                 GP_1_6_FN,      GPSR1_6,
2111                 GP_1_5_FN,      GPSR1_5,
2112                 GP_1_4_FN,      GPSR1_4,
2113                 GP_1_3_FN,      GPSR1_3,
2114                 GP_1_2_FN,      GPSR1_2,
2115                 GP_1_1_FN,      GPSR1_1,
2116                 GP_1_0_FN,      GPSR1_0, }
2117         },
2118         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2119                 0, 0,
2120                 0, 0,
2121                 0, 0,
2122                 0, 0,
2123                 0, 0,
2124                 0, 0,
2125                 0, 0,
2126                 0, 0,
2127                 0, 0,
2128                 0, 0,
2129                 0, 0,
2130                 0, 0,
2131                 0, 0,
2132                 0, 0,
2133                 0, 0,
2134                 GP_2_16_FN,     GPSR2_16,
2135                 GP_2_15_FN,     GPSR2_15,
2136                 GP_2_14_FN,     GPSR2_14,
2137                 GP_2_13_FN,     GPSR2_13,
2138                 GP_2_12_FN,     GPSR2_12,
2139                 GP_2_11_FN,     GPSR2_11,
2140                 GP_2_10_FN,     GPSR2_10,
2141                 GP_2_9_FN,      GPSR2_9,
2142                 GP_2_8_FN,      GPSR2_8,
2143                 GP_2_7_FN,      GPSR2_7,
2144                 GP_2_6_FN,      GPSR2_6,
2145                 GP_2_5_FN,      GPSR2_5,
2146                 GP_2_4_FN,      GPSR2_4,
2147                 GP_2_3_FN,      GPSR2_3,
2148                 GP_2_2_FN,      GPSR2_2,
2149                 GP_2_1_FN,      GPSR2_1,
2150                 GP_2_0_FN,      GPSR2_0, }
2151         },
2152         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2153                 0, 0,
2154                 0, 0,
2155                 0, 0,
2156                 0, 0,
2157                 0, 0,
2158                 0, 0,
2159                 0, 0,
2160                 0, 0,
2161                 0, 0,
2162                 0, 0,
2163                 0, 0,
2164                 0, 0,
2165                 0, 0,
2166                 0, 0,
2167                 0, 0,
2168                 GP_3_16_FN,     GPSR3_16,
2169                 GP_3_15_FN,     GPSR3_15,
2170                 GP_3_14_FN,     GPSR3_14,
2171                 GP_3_13_FN,     GPSR3_13,
2172                 GP_3_12_FN,     GPSR3_12,
2173                 GP_3_11_FN,     GPSR3_11,
2174                 GP_3_10_FN,     GPSR3_10,
2175                 GP_3_9_FN,      GPSR3_9,
2176                 GP_3_8_FN,      GPSR3_8,
2177                 GP_3_7_FN,      GPSR3_7,
2178                 GP_3_6_FN,      GPSR3_6,
2179                 GP_3_5_FN,      GPSR3_5,
2180                 GP_3_4_FN,      GPSR3_4,
2181                 GP_3_3_FN,      GPSR3_3,
2182                 GP_3_2_FN,      GPSR3_2,
2183                 GP_3_1_FN,      GPSR3_1,
2184                 GP_3_0_FN,      GPSR3_0, }
2185         },
2186         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2187                 0, 0,
2188                 0, 0,
2189                 0, 0,
2190                 0, 0,
2191                 0, 0,
2192                 0, 0,
2193                 0, 0,
2194                 0, 0,
2195                 0, 0,
2196                 0, 0,
2197                 0, 0,
2198                 0, 0,
2199                 0, 0,
2200                 0, 0,
2201                 0, 0,
2202                 0, 0,
2203                 0, 0,
2204                 0, 0,
2205                 0, 0,
2206                 0, 0,
2207                 0, 0,
2208                 0, 0,
2209                 0, 0,
2210                 0, 0,
2211                 0, 0,
2212                 0, 0,
2213                 GP_4_5_FN,      GPSR4_5,
2214                 GP_4_4_FN,      GPSR4_4,
2215                 GP_4_3_FN,      GPSR4_3,
2216                 GP_4_2_FN,      GPSR4_2,
2217                 GP_4_1_FN,      GPSR4_1,
2218                 GP_4_0_FN,      GPSR4_0, }
2219         },
2220         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2221                 0, 0,
2222                 0, 0,
2223                 0, 0,
2224                 0, 0,
2225                 0, 0,
2226                 0, 0,
2227                 0, 0,
2228                 0, 0,
2229                 0, 0,
2230                 0, 0,
2231                 0, 0,
2232                 0, 0,
2233                 0, 0,
2234                 0, 0,
2235                 0, 0,
2236                 0, 0,
2237                 0, 0,
2238                 GP_5_14_FN,     GPSR5_14,
2239                 GP_5_13_FN,     GPSR5_13,
2240                 GP_5_12_FN,     GPSR5_12,
2241                 GP_5_11_FN,     GPSR5_11,
2242                 GP_5_10_FN,     GPSR5_10,
2243                 GP_5_9_FN,      GPSR5_9,
2244                 GP_5_8_FN,      GPSR5_8,
2245                 GP_5_7_FN,      GPSR5_7,
2246                 GP_5_6_FN,      GPSR5_6,
2247                 GP_5_5_FN,      GPSR5_5,
2248                 GP_5_4_FN,      GPSR5_4,
2249                 GP_5_3_FN,      GPSR5_3,
2250                 GP_5_2_FN,      GPSR5_2,
2251                 GP_5_1_FN,      GPSR5_1,
2252                 GP_5_0_FN,      GPSR5_0, }
2253         },
2254 #undef F_
2255 #undef FM
2256
2257 #define F_(x, y)        x,
2258 #define FM(x)           FN_##x,
2259         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2260                 IP0_31_28
2261                 IP0_27_24
2262                 IP0_23_20
2263                 IP0_19_16
2264                 IP0_15_12
2265                 IP0_11_8
2266                 IP0_7_4
2267                 IP0_3_0 }
2268         },
2269         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2270                 IP1_31_28
2271                 IP1_27_24
2272                 IP1_23_20
2273                 IP1_19_16
2274                 IP1_15_12
2275                 IP1_11_8
2276                 IP1_7_4
2277                 IP1_3_0 }
2278         },
2279         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2280                 IP2_31_28
2281                 IP2_27_24
2282                 IP2_23_20
2283                 IP2_19_16
2284                 IP2_15_12
2285                 IP2_11_8
2286                 IP2_7_4
2287                 IP2_3_0 }
2288         },
2289         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2290                 IP3_31_28
2291                 IP3_27_24
2292                 IP3_23_20
2293                 IP3_19_16
2294                 IP3_15_12
2295                 IP3_11_8
2296                 IP3_7_4
2297                 IP3_3_0 }
2298         },
2299         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2300                 IP4_31_28
2301                 IP4_27_24
2302                 IP4_23_20
2303                 IP4_19_16
2304                 IP4_15_12
2305                 IP4_11_8
2306                 IP4_7_4
2307                 IP4_3_0 }
2308         },
2309         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2310                 IP5_31_28
2311                 IP5_27_24
2312                 IP5_23_20
2313                 IP5_19_16
2314                 IP5_15_12
2315                 IP5_11_8
2316                 IP5_7_4
2317                 IP5_3_0 }
2318         },
2319         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2320                 IP6_31_28
2321                 IP6_27_24
2322                 IP6_23_20
2323                 IP6_19_16
2324                 IP6_15_12
2325                 IP6_11_8
2326                 IP6_7_4
2327                 IP6_3_0 }
2328         },
2329         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2330                 IP7_31_28
2331                 IP7_27_24
2332                 IP7_23_20
2333                 IP7_19_16
2334                 IP7_15_12
2335                 IP7_11_8
2336                 IP7_7_4
2337                 IP7_3_0 }
2338         },
2339         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2340                 IP8_31_28
2341                 IP8_27_24
2342                 IP8_23_20
2343                 IP8_19_16
2344                 IP8_15_12
2345                 IP8_11_8
2346                 IP8_7_4
2347                 IP8_3_0 }
2348         },
2349 #undef F_
2350 #undef FM
2351
2352 #define F_(x, y)        x,
2353 #define FM(x)           FN_##x,
2354         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2355                              4, 4, 4, 4,
2356                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2357                 /* RESERVED 31, 30, 29, 28 */
2358                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2359                 /* RESERVED 27, 26, 25, 24 */
2360                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2361                 /* RESERVED 23, 22, 21, 20 */
2362                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2363                 /* RESERVED 19, 18, 17, 16 */
2364                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2365                 /* RESERVED 15, 14, 13, 12 */
2366                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2367                 MOD_SEL0_11
2368                 MOD_SEL0_10
2369                 MOD_SEL0_9
2370                 MOD_SEL0_8
2371                 MOD_SEL0_7
2372                 MOD_SEL0_6
2373                 MOD_SEL0_5
2374                 MOD_SEL0_4
2375                 MOD_SEL0_3
2376                 MOD_SEL0_2
2377                 MOD_SEL0_1
2378                 MOD_SEL0_0 }
2379         },
2380         { },
2381 };
2382
2383 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2384                                    u32 *pocctrl)
2385 {
2386         int bit = pin & 0x1f;
2387
2388         *pocctrl = 0xe6060380;
2389         if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2390                 return bit;
2391         if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2392                 return bit + 22;
2393
2394         *pocctrl += 4;
2395         if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2396                 return bit - 10;
2397         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2398                 return bit + 7;
2399
2400         return -EINVAL;
2401 }
2402
2403 static const struct sh_pfc_soc_operations pinmux_ops = {
2404         .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2405 };
2406
2407 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2408         .name = "r8a77970_pfc",
2409         .ops = &pinmux_ops,
2410         .unlock_reg = 0xe6060000, /* PMMR */
2411
2412         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2413
2414         .pins = pinmux_pins,
2415         .nr_pins = ARRAY_SIZE(pinmux_pins),
2416         .groups = pinmux_groups,
2417         .nr_groups = ARRAY_SIZE(pinmux_groups),
2418         .functions = pinmux_functions,
2419         .nr_functions = ARRAY_SIZE(pinmux_functions),
2420
2421         .cfg_regs = pinmux_config_regs,
2422
2423         .pinmux_data = pinmux_data,
2424         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2425 };